1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Owen Chen <owen.chen@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9
10#include "clk-mtk.h"
11#include "clk-gate.h"
12
13#include <dt-bindings/clock/mt6765-clk.h>
14
15static const struct mtk_gate_regs img_cg_regs = {
16	.set_ofs = 0x4,
17	.clr_ofs = 0x8,
18	.sta_ofs = 0x0,
19};
20
21#define GATE_IMG(_id, _name, _parent, _shift) {		\
22		.id = _id,				\
23		.name = _name,				\
24		.parent_name = _parent,			\
25		.regs = &img_cg_regs,			\
26		.shift = _shift,			\
27		.ops = &mtk_clk_gate_ops_setclr,	\
28	}
29
30static const struct mtk_gate img_clks[] = {
31	GATE_IMG(CLK_IMG_LARB2, "img_larb2", "mm_ck", 0),
32	GATE_IMG(CLK_IMG_DIP, "img_dip", "mm_ck", 2),
33	GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_ck", 3),
34	GATE_IMG(CLK_IMG_DPE, "img_dpe", "mm_ck", 4),
35	GATE_IMG(CLK_IMG_RSC, "img_rsc", "mm_ck", 5),
36};
37
38static int clk_mt6765_img_probe(struct platform_device *pdev)
39{
40	struct clk_onecell_data *clk_data;
41	int r;
42	struct device_node *node = pdev->dev.of_node;
43
44	clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
45
46	mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), clk_data);
47
48	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
49
50	if (r)
51		pr_err("%s(): could not register clock provider: %d\n",
52		       __func__, r);
53
54	return r;
55}
56
57static const struct of_device_id of_match_clk_mt6765_img[] = {
58	{ .compatible = "mediatek,mt6765-imgsys", },
59	{}
60};
61
62static struct platform_driver clk_mt6765_img_drv = {
63	.probe = clk_mt6765_img_probe,
64	.driver = {
65		.name = "clk-mt6765-img",
66		.of_match_table = of_match_clk_mt6765_img,
67	},
68};
69
70builtin_platform_driver(clk_mt6765_img_drv);
71