1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Shunli Wang <shunli.wang@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9
10#include "clk-mtk.h"
11#include "clk-gate.h"
12
13#include <dt-bindings/clock/mt2701-clk.h>
14
15static const struct mtk_gate_regs disp0_cg_regs = {
16	.set_ofs = 0x0104,
17	.clr_ofs = 0x0108,
18	.sta_ofs = 0x0100,
19};
20
21static const struct mtk_gate_regs disp1_cg_regs = {
22	.set_ofs = 0x0114,
23	.clr_ofs = 0x0118,
24	.sta_ofs = 0x0110,
25};
26
27#define GATE_DISP0(_id, _name, _parent, _shift) {	\
28		.id = _id,				\
29		.name = _name,				\
30		.parent_name = _parent,			\
31		.regs = &disp0_cg_regs,			\
32		.shift = _shift,			\
33		.ops = &mtk_clk_gate_ops_setclr,	\
34	}
35
36#define GATE_DISP1(_id, _name, _parent, _shift) {	\
37		.id = _id,				\
38		.name = _name,				\
39		.parent_name = _parent,			\
40		.regs = &disp1_cg_regs,			\
41		.shift = _shift,			\
42		.ops = &mtk_clk_gate_ops_setclr,	\
43	}
44
45static const struct mtk_gate mm_clks[] = {
46	GATE_DISP0(CLK_MM_SMI_COMMON, "mm_smi_comm", "mm_sel", 0),
47	GATE_DISP0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
48	GATE_DISP0(CLK_MM_CMDQ, "mm_cmdq", "mm_sel", 2),
49	GATE_DISP0(CLK_MM_MUTEX, "mm_mutex", "mm_sel", 3),
50	GATE_DISP0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 4),
51	GATE_DISP0(CLK_MM_DISP_BLS, "mm_disp_bls", "mm_sel", 5),
52	GATE_DISP0(CLK_MM_DISP_WDMA, "mm_disp_wdma", "mm_sel", 6),
53	GATE_DISP0(CLK_MM_DISP_RDMA, "mm_disp_rdma", "mm_sel", 7),
54	GATE_DISP0(CLK_MM_DISP_OVL, "mm_disp_ovl", "mm_sel", 8),
55	GATE_DISP0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 9),
56	GATE_DISP0(CLK_MM_MDP_WROT, "mm_mdp_wrot", "mm_sel", 10),
57	GATE_DISP0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
58	GATE_DISP0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 12),
59	GATE_DISP0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 13),
60	GATE_DISP0(CLK_MM_MDP_RDMA, "mm_mdp_rdma", "mm_sel", 14),
61	GATE_DISP0(CLK_MM_MDP_BLS_26M, "mm_mdp_bls_26m", "pwm_sel", 15),
62	GATE_DISP0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 16),
63	GATE_DISP0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 17),
64	GATE_DISP0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 18),
65	GATE_DISP0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
66	GATE_DISP0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 20),
67	GATE_DISP1(CLK_MM_DSI_ENGINE, "mm_dsi_eng", "mm_sel", 0),
68	GATE_DISP1(CLK_MM_DSI_DIG, "mm_dsi_dig", "dsi0_lntc_dsi", 1),
69	GATE_DISP1(CLK_MM_DPI_DIGL, "mm_dpi_digl", "dpi0_sel", 2),
70	GATE_DISP1(CLK_MM_DPI_ENGINE, "mm_dpi_eng", "mm_sel", 3),
71	GATE_DISP1(CLK_MM_DPI1_DIGL, "mm_dpi1_digl", "dpi1_sel", 4),
72	GATE_DISP1(CLK_MM_DPI1_ENGINE, "mm_dpi1_eng", "mm_sel", 5),
73	GATE_DISP1(CLK_MM_TVE_OUTPUT, "mm_tve_output", "tve_sel", 6),
74	GATE_DISP1(CLK_MM_TVE_INPUT, "mm_tve_input", "dpi0_sel", 7),
75	GATE_DISP1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi1_sel", 8),
76	GATE_DISP1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmi_sel", 9),
77	GATE_DISP1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll_sel", 10),
78	GATE_DISP1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll_sel", 11),
79	GATE_DISP1(CLK_MM_TVE_FMM, "mm_tve_fmm", "mm_sel", 14),
80};
81
82static int clk_mt2701_mm_probe(struct platform_device *pdev)
83{
84	struct device *dev = &pdev->dev;
85	struct device_node *node = dev->parent->of_node;
86	struct clk_onecell_data *clk_data;
87	int r;
88
89	clk_data = mtk_alloc_clk_data(CLK_MM_NR);
90
91	mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
92						clk_data);
93
94	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
95	if (r)
96		dev_err(&pdev->dev,
97			"could not register clock provider: %s: %d\n",
98			pdev->name, r);
99
100	return r;
101}
102
103static struct platform_driver clk_mt2701_mm_drv = {
104	.probe = clk_mt2701_mm_probe,
105	.driver = {
106		.name = "clk-mt2701-mm",
107	},
108};
109
110builtin_platform_driver(clk_mt2701_mm_drv);
111