18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-only
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * Copyright (c) 2014 MediaTek Inc.
48c2ecf20Sopenharmony_ci * Author: Shunli Wang <shunli.wang@mediatek.com>
58c2ecf20Sopenharmony_ci */
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ci#include <linux/clk-provider.h>
88c2ecf20Sopenharmony_ci#include <linux/platform_device.h>
98c2ecf20Sopenharmony_ci
108c2ecf20Sopenharmony_ci#include "clk-mtk.h"
118c2ecf20Sopenharmony_ci#include "clk-gate.h"
128c2ecf20Sopenharmony_ci
138c2ecf20Sopenharmony_ci#include <dt-bindings/clock/mt2701-clk.h>
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_cistatic const struct mtk_gate_regs hif_cg_regs = {
168c2ecf20Sopenharmony_ci	.sta_ofs = 0x0030,
178c2ecf20Sopenharmony_ci};
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ci#define GATE_HIF(_id, _name, _parent, _shift) {		\
208c2ecf20Sopenharmony_ci		.id = _id,				\
218c2ecf20Sopenharmony_ci		.name = _name,				\
228c2ecf20Sopenharmony_ci		.parent_name = _parent,			\
238c2ecf20Sopenharmony_ci		.regs = &hif_cg_regs,			\
248c2ecf20Sopenharmony_ci		.shift = _shift,			\
258c2ecf20Sopenharmony_ci		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
268c2ecf20Sopenharmony_ci	}
278c2ecf20Sopenharmony_ci
288c2ecf20Sopenharmony_cistatic const struct mtk_gate hif_clks[] = {
298c2ecf20Sopenharmony_ci	GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
308c2ecf20Sopenharmony_ci	GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
318c2ecf20Sopenharmony_ci	GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
328c2ecf20Sopenharmony_ci	GATE_HIF(CLK_HIFSYS_PCIE1, "pcie1_clk", "ethpll_500m_ck", 25),
338c2ecf20Sopenharmony_ci	GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
348c2ecf20Sopenharmony_ci};
358c2ecf20Sopenharmony_ci
368c2ecf20Sopenharmony_cistatic const struct of_device_id of_match_clk_mt2701_hif[] = {
378c2ecf20Sopenharmony_ci	{ .compatible = "mediatek,mt2701-hifsys", },
388c2ecf20Sopenharmony_ci	{}
398c2ecf20Sopenharmony_ci};
408c2ecf20Sopenharmony_ci
418c2ecf20Sopenharmony_cistatic int clk_mt2701_hif_probe(struct platform_device *pdev)
428c2ecf20Sopenharmony_ci{
438c2ecf20Sopenharmony_ci	struct clk_onecell_data *clk_data;
448c2ecf20Sopenharmony_ci	int r;
458c2ecf20Sopenharmony_ci	struct device_node *node = pdev->dev.of_node;
468c2ecf20Sopenharmony_ci
478c2ecf20Sopenharmony_ci	clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
488c2ecf20Sopenharmony_ci
498c2ecf20Sopenharmony_ci	mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
508c2ecf20Sopenharmony_ci						clk_data);
518c2ecf20Sopenharmony_ci
528c2ecf20Sopenharmony_ci	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
538c2ecf20Sopenharmony_ci	if (r) {
548c2ecf20Sopenharmony_ci		dev_err(&pdev->dev,
558c2ecf20Sopenharmony_ci			"could not register clock provider: %s: %d\n",
568c2ecf20Sopenharmony_ci			pdev->name, r);
578c2ecf20Sopenharmony_ci		return r;
588c2ecf20Sopenharmony_ci	}
598c2ecf20Sopenharmony_ci
608c2ecf20Sopenharmony_ci	mtk_register_reset_controller(node, 1, 0x34);
618c2ecf20Sopenharmony_ci
628c2ecf20Sopenharmony_ci	return 0;
638c2ecf20Sopenharmony_ci}
648c2ecf20Sopenharmony_ci
658c2ecf20Sopenharmony_cistatic struct platform_driver clk_mt2701_hif_drv = {
668c2ecf20Sopenharmony_ci	.probe = clk_mt2701_hif_probe,
678c2ecf20Sopenharmony_ci	.driver = {
688c2ecf20Sopenharmony_ci		.name = "clk-mt2701-hif",
698c2ecf20Sopenharmony_ci		.of_match_table = of_match_clk_mt2701_hif,
708c2ecf20Sopenharmony_ci	},
718c2ecf20Sopenharmony_ci};
728c2ecf20Sopenharmony_ci
738c2ecf20Sopenharmony_cibuiltin_platform_driver(clk_mt2701_hif_drv);
74