1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Ingenic JZ4740 SoC CGU driver
4 *
5 * Copyright (c) 2015 Imagination Technologies
6 * Author: Paul Burton <paul.burton@mips.com>
7 */
8
9#include <linux/clk-provider.h>
10#include <linux/delay.h>
11#include <linux/io.h>
12#include <linux/of.h>
13
14#include <dt-bindings/clock/jz4740-cgu.h>
15
16#include "cgu.h"
17#include "pm.h"
18
19/* CGU register offsets */
20#define CGU_REG_CPCCR		0x00
21#define CGU_REG_LCR		0x04
22#define CGU_REG_CPPCR		0x10
23#define CGU_REG_CLKGR		0x20
24#define CGU_REG_SCR		0x24
25#define CGU_REG_I2SCDR		0x60
26#define CGU_REG_LPCDR		0x64
27#define CGU_REG_MSCCDR		0x68
28#define CGU_REG_UHCCDR		0x6c
29#define CGU_REG_SSICDR		0x74
30
31/* bits within a PLL control register */
32#define PLLCTL_M_SHIFT		23
33#define PLLCTL_M_MASK		(0x1ff << PLLCTL_M_SHIFT)
34#define PLLCTL_N_SHIFT		18
35#define PLLCTL_N_MASK		(0x1f << PLLCTL_N_SHIFT)
36#define PLLCTL_OD_SHIFT		16
37#define PLLCTL_OD_MASK		(0x3 << PLLCTL_OD_SHIFT)
38#define PLLCTL_STABLE		(1 << 10)
39#define PLLCTL_BYPASS		(1 << 9)
40#define PLLCTL_ENABLE		(1 << 8)
41
42/* bits within the LCR register */
43#define LCR_SLEEP		(1 << 0)
44
45/* bits within the CLKGR register */
46#define CLKGR_UDC		(1 << 11)
47
48static struct ingenic_cgu *cgu;
49
50static const s8 pll_od_encoding[4] = {
51	0x0, 0x1, -1, 0x3,
52};
53
54static const u8 jz4740_cgu_cpccr_div_table[] = {
55	1, 2, 3, 4, 6, 8, 12, 16, 24, 32,
56};
57
58static const u8 jz4740_cgu_pll_half_div_table[] = {
59	2, 1,
60};
61
62static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
63
64	/* External clocks */
65
66	[JZ4740_CLK_EXT] = { "ext", CGU_CLK_EXT },
67	[JZ4740_CLK_RTC] = { "rtc", CGU_CLK_EXT },
68
69	[JZ4740_CLK_PLL] = {
70		"pll", CGU_CLK_PLL,
71		.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
72		.pll = {
73			.reg = CGU_REG_CPPCR,
74			.rate_multiplier = 1,
75			.m_shift = 23,
76			.m_bits = 9,
77			.m_offset = 2,
78			.n_shift = 18,
79			.n_bits = 5,
80			.n_offset = 2,
81			.od_shift = 16,
82			.od_bits = 2,
83			.od_max = 4,
84			.od_encoding = pll_od_encoding,
85			.stable_bit = 10,
86			.bypass_reg = CGU_REG_CPPCR,
87			.bypass_bit = 9,
88			.enable_bit = 8,
89		},
90	},
91
92	/* Muxes & dividers */
93
94	[JZ4740_CLK_PLL_HALF] = {
95		"pll half", CGU_CLK_DIV,
96		.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
97		.div = {
98			CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
99			jz4740_cgu_pll_half_div_table,
100		},
101	},
102
103	[JZ4740_CLK_CCLK] = {
104		"cclk", CGU_CLK_DIV,
105		.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
106		.div = {
107			CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
108			jz4740_cgu_cpccr_div_table,
109		},
110	},
111
112	[JZ4740_CLK_HCLK] = {
113		"hclk", CGU_CLK_DIV,
114		.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
115		.div = {
116			CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
117			jz4740_cgu_cpccr_div_table,
118		},
119	},
120
121	[JZ4740_CLK_PCLK] = {
122		"pclk", CGU_CLK_DIV,
123		.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
124		.div = {
125			CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
126			jz4740_cgu_cpccr_div_table,
127		},
128	},
129
130	[JZ4740_CLK_MCLK] = {
131		"mclk", CGU_CLK_DIV,
132		.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
133		.div = {
134			CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
135			jz4740_cgu_cpccr_div_table,
136		},
137	},
138
139	[JZ4740_CLK_LCD] = {
140		"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
141		.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
142		.div = {
143			CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1,
144			jz4740_cgu_cpccr_div_table,
145		},
146		.gate = { CGU_REG_CLKGR, 10 },
147	},
148
149	[JZ4740_CLK_LCD_PCLK] = {
150		"lcd_pclk", CGU_CLK_DIV,
151		.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
152		.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
153	},
154
155	[JZ4740_CLK_I2S] = {
156		"i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
157		.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
158		.mux = { CGU_REG_CPCCR, 31, 1 },
159		.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
160		.gate = { CGU_REG_CLKGR, 6 },
161	},
162
163	[JZ4740_CLK_SPI] = {
164		"spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
165		.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 },
166		.mux = { CGU_REG_SSICDR, 31, 1 },
167		.div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
168		.gate = { CGU_REG_CLKGR, 4 },
169	},
170
171	[JZ4740_CLK_MMC] = {
172		"mmc", CGU_CLK_DIV | CGU_CLK_GATE,
173		.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
174		.div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
175		.gate = { CGU_REG_CLKGR, 7 },
176	},
177
178	[JZ4740_CLK_UHC] = {
179		"uhc", CGU_CLK_DIV | CGU_CLK_GATE,
180		.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
181		.div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
182		.gate = { CGU_REG_CLKGR, 14 },
183	},
184
185	[JZ4740_CLK_UDC] = {
186		"udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
187		.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
188		.mux = { CGU_REG_CPCCR, 29, 1 },
189		.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
190		.gate = { CGU_REG_SCR, 6, true },
191	},
192
193	/* Gate-only clocks */
194
195	[JZ4740_CLK_UART0] = {
196		"uart0", CGU_CLK_GATE,
197		.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
198		.gate = { CGU_REG_CLKGR, 0 },
199	},
200
201	[JZ4740_CLK_UART1] = {
202		"uart1", CGU_CLK_GATE,
203		.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
204		.gate = { CGU_REG_CLKGR, 15 },
205	},
206
207	[JZ4740_CLK_DMA] = {
208		"dma", CGU_CLK_GATE,
209		.parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
210		.gate = { CGU_REG_CLKGR, 12 },
211	},
212
213	[JZ4740_CLK_IPU] = {
214		"ipu", CGU_CLK_GATE,
215		.parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
216		.gate = { CGU_REG_CLKGR, 13 },
217	},
218
219	[JZ4740_CLK_ADC] = {
220		"adc", CGU_CLK_GATE,
221		.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
222		.gate = { CGU_REG_CLKGR, 8 },
223	},
224
225	[JZ4740_CLK_I2C] = {
226		"i2c", CGU_CLK_GATE,
227		.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
228		.gate = { CGU_REG_CLKGR, 3 },
229	},
230
231	[JZ4740_CLK_AIC] = {
232		"aic", CGU_CLK_GATE,
233		.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
234		.gate = { CGU_REG_CLKGR, 5 },
235	},
236
237	[JZ4740_CLK_TCU] = {
238		"tcu", CGU_CLK_GATE,
239		.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
240		.gate = { CGU_REG_CLKGR, 1 },
241	},
242};
243
244static void __init jz4740_cgu_init(struct device_node *np)
245{
246	int retval;
247
248	cgu = ingenic_cgu_new(jz4740_cgu_clocks,
249			      ARRAY_SIZE(jz4740_cgu_clocks), np);
250	if (!cgu) {
251		pr_err("%s: failed to initialise CGU\n", __func__);
252		return;
253	}
254
255	retval = ingenic_cgu_register_clocks(cgu);
256	if (retval)
257		pr_err("%s: failed to register CGU Clocks\n", __func__);
258
259	ingenic_cgu_register_syscore_ops(cgu);
260}
261CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);
262