1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Ingenic SoC CGU driver
4 *
5 * Copyright (c) 2013-2015 Imagination Technologies
6 * Author: Paul Burton <paul.burton@mips.com>
7 */
8
9#ifndef __DRIVERS_CLK_INGENIC_CGU_H__
10#define __DRIVERS_CLK_INGENIC_CGU_H__
11
12#include <linux/bitops.h>
13#include <linux/clk-provider.h>
14#include <linux/of.h>
15#include <linux/spinlock.h>
16
17/**
18 * struct ingenic_cgu_pll_info - information about a PLL
19 * @reg: the offset of the PLL's control register within the CGU
20 * @rate_multiplier: the multiplier needed by pll rate calculation
21 * @m_shift: the number of bits to shift the multiplier value by (ie. the
22 *           index of the lowest bit of the multiplier value in the PLL's
23 *           control register)
24 * @m_bits: the size of the multiplier field in bits
25 * @m_offset: the multiplier value which encodes to 0 in the PLL's control
26 *            register
27 * @n_shift: the number of bits to shift the divider value by (ie. the
28 *           index of the lowest bit of the divider value in the PLL's
29 *           control register)
30 * @n_bits: the size of the divider field in bits
31 * @n_offset: the divider value which encodes to 0 in the PLL's control
32 *            register
33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
34 *            the index of the lowest bit of the post-VCO divider value in
35 *            the PLL's control register)
36 * @od_bits: the size of the post-VCO divider field in bits
37 * @od_max: the maximum post-VCO divider value
38 * @od_encoding: a pointer to an array mapping post-VCO divider values to
39 *               their encoded values in the PLL control register, or -1 for
40 *               unsupported values
41 * @bypass_reg: the offset of the bypass control register within the CGU
42 * @bypass_bit: the index of the bypass bit in the PLL control register
43 * @enable_bit: the index of the enable bit in the PLL control register
44 * @stable_bit: the index of the stable bit in the PLL control register
45 * @no_bypass_bit: if set, the PLL has no bypass functionality
46 */
47struct ingenic_cgu_pll_info {
48	unsigned reg;
49	unsigned rate_multiplier;
50	const s8 *od_encoding;
51	u8 m_shift, m_bits, m_offset;
52	u8 n_shift, n_bits, n_offset;
53	u8 od_shift, od_bits, od_max;
54	unsigned bypass_reg;
55	u8 bypass_bit;
56	u8 enable_bit;
57	u8 stable_bit;
58	bool no_bypass_bit;
59};
60
61/**
62 * struct ingenic_cgu_mux_info - information about a clock mux
63 * @reg: offset of the mux control register within the CGU
64 * @shift: number of bits to shift the mux value by (ie. the index of
65 *         the lowest bit of the mux value within its control register)
66 * @bits: the size of the mux value in bits
67 */
68struct ingenic_cgu_mux_info {
69	unsigned reg;
70	u8 shift;
71	u8 bits;
72};
73
74/**
75 * struct ingenic_cgu_div_info - information about a divider
76 * @reg: offset of the divider control register within the CGU
77 * @shift: number of bits to left shift the divide value by (ie. the index of
78 *         the lowest bit of the divide value within its control register)
79 * @div: number to divide the divider value by (i.e. if the
80 *	 effective divider value is the value written to the register
81 *	 multiplied by some constant)
82 * @bits: the size of the divide value in bits
83 * @ce_bit: the index of the change enable bit within reg, or -1 if there
84 *          isn't one
85 * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one
86 * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one
87 * @div_table: optional table to map the value read from the register to the
88 *             actual divider value
89 */
90struct ingenic_cgu_div_info {
91	unsigned reg;
92	u8 shift;
93	u8 div;
94	u8 bits;
95	s8 ce_bit;
96	s8 busy_bit;
97	s8 stop_bit;
98	const u8 *div_table;
99};
100
101/**
102 * struct ingenic_cgu_fixdiv_info - information about a fixed divider
103 * @div: the divider applied to the parent clock
104 */
105struct ingenic_cgu_fixdiv_info {
106	unsigned div;
107};
108
109/**
110 * struct ingenic_cgu_gate_info - information about a clock gate
111 * @reg: offset of the gate control register within the CGU
112 * @bit: offset of the bit in the register that controls the gate
113 * @clear_to_gate: if set, the clock is gated when the bit is cleared
114 * @delay_us: delay in microseconds after which the clock is considered stable
115 */
116struct ingenic_cgu_gate_info {
117	unsigned reg;
118	u8 bit;
119	bool clear_to_gate;
120	u16 delay_us;
121};
122
123/**
124 * struct ingenic_cgu_custom_info - information about a custom (SoC) clock
125 * @clk_ops: custom clock operation callbacks
126 */
127struct ingenic_cgu_custom_info {
128	const struct clk_ops *clk_ops;
129};
130
131/**
132 * struct ingenic_cgu_clk_info - information about a clock
133 * @name: name of the clock
134 * @type: a bitmask formed from CGU_CLK_* values
135 * @parents: an array of the indices of potential parents of this clock
136 *           within the clock_info array of the CGU, or -1 in entries
137 *           which correspond to no valid parent
138 * @pll: information valid if type includes CGU_CLK_PLL
139 * @gate: information valid if type includes CGU_CLK_GATE
140 * @mux: information valid if type includes CGU_CLK_MUX
141 * @div: information valid if type includes CGU_CLK_DIV
142 * @fixdiv: information valid if type includes CGU_CLK_FIXDIV
143 * @custom: information valid if type includes CGU_CLK_CUSTOM
144 */
145struct ingenic_cgu_clk_info {
146	const char *name;
147
148	enum {
149		CGU_CLK_NONE		= 0,
150		CGU_CLK_EXT		= BIT(0),
151		CGU_CLK_PLL		= BIT(1),
152		CGU_CLK_GATE		= BIT(2),
153		CGU_CLK_MUX		= BIT(3),
154		CGU_CLK_MUX_GLITCHFREE	= BIT(4),
155		CGU_CLK_DIV		= BIT(5),
156		CGU_CLK_FIXDIV		= BIT(6),
157		CGU_CLK_CUSTOM		= BIT(7),
158	} type;
159
160	int parents[4];
161
162	union {
163		struct ingenic_cgu_pll_info pll;
164
165		struct {
166			struct ingenic_cgu_gate_info gate;
167			struct ingenic_cgu_mux_info mux;
168			struct ingenic_cgu_div_info div;
169			struct ingenic_cgu_fixdiv_info fixdiv;
170		};
171
172		struct ingenic_cgu_custom_info custom;
173	};
174};
175
176/**
177 * struct ingenic_cgu - data about the CGU
178 * @np: the device tree node that caused the CGU to be probed
179 * @base: the ioremap'ed base address of the CGU registers
180 * @clock_info: an array containing information about implemented clocks
181 * @clocks: used to provide clocks to DT, allows lookup of struct clk*
182 * @lock: lock to be held whilst manipulating CGU registers
183 */
184struct ingenic_cgu {
185	struct device_node *np;
186	void __iomem *base;
187
188	const struct ingenic_cgu_clk_info *clock_info;
189	struct clk_onecell_data clocks;
190
191	spinlock_t lock;
192};
193
194/**
195 * struct ingenic_clk - private data for a clock
196 * @hw: see Documentation/driver-api/clk.rst
197 * @cgu: a pointer to the CGU data
198 * @idx: the index of this clock in cgu->clock_info
199 */
200struct ingenic_clk {
201	struct clk_hw hw;
202	struct ingenic_cgu *cgu;
203	unsigned idx;
204};
205
206#define to_ingenic_clk(_hw) container_of(_hw, struct ingenic_clk, hw)
207
208/**
209 * ingenic_cgu_new() - create a new CGU instance
210 * @clock_info: an array of clock information structures describing the clocks
211 *              which are implemented by the CGU
212 * @num_clocks: the number of entries in clock_info
213 * @np: the device tree node which causes this CGU to be probed
214 *
215 * Return: a pointer to the CGU instance if initialisation is successful,
216 *         otherwise NULL.
217 */
218struct ingenic_cgu *
219ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info,
220		unsigned num_clocks, struct device_node *np);
221
222/**
223 * ingenic_cgu_register_clocks() - Registers the clocks
224 * @cgu: pointer to cgu data
225 *
226 * Register the clocks described by the CGU with the common clock framework.
227 *
228 * Return: 0 on success or -errno if unsuccesful.
229 */
230int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu);
231
232#endif /* __DRIVERS_CLK_INGENIC_CGU_H__ */
233