1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2016-2017 Linaro Ltd.
4 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
5 */
6
7#include <dt-bindings/clock/hi3660-clock.h>
8#include <linux/clk-provider.h>
9#include <linux/of_device.h>
10#include <linux/platform_device.h>
11#include "clk.h"
12
13static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = {
14	{ HI3660_CLKIN_SYS, "clkin_sys", NULL, 0, 19200000, },
15	{ HI3660_CLKIN_REF, "clkin_ref", NULL, 0, 32764, },
16	{ HI3660_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 128000000, },
17	{ HI3660_CLK_PPLL0, "clk_ppll0", NULL, 0, 1600000000, },
18	{ HI3660_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, },
19	{ HI3660_CLK_PPLL2, "clk_ppll2", NULL, 0, 2880000000UL, },
20	{ HI3660_CLK_PPLL3, "clk_ppll3", NULL, 0, 1290000000, },
21	{ HI3660_CLK_SCPLL, "clk_scpll", NULL, 0, 245760000, },
22	{ HI3660_PCLK, "pclk", NULL, 0, 20000000, },
23	{ HI3660_CLK_UART0_DBG, "clk_uart0_dbg", NULL, 0, 19200000, },
24	{ HI3660_CLK_UART6, "clk_uart6", NULL, 0, 19200000, },
25	{ HI3660_OSC32K, "osc32k", NULL, 0, 32764, },
26	{ HI3660_OSC19M, "osc19m", NULL, 0, 19200000, },
27	{ HI3660_CLK_480M, "clk_480m", NULL, 0, 480000000, },
28	{ HI3660_CLK_INV, "clk_inv", NULL, 0, 10000000, },
29};
30
31/* crgctrl */
32static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = {
33	{ HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 16, 0, },
34	{ HI3660_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys", 1, 6, 0, },
35	{ HI3660_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_iomcu", 1, 4, 0, },
36	{ HI3660_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_iomcu", 1, 4, 0, },
37	{ HI3660_CLK_GATE_I2C2, "clk_gate_i2c2", "clk_i2c2_iomcu", 1, 4, 0, },
38	{ HI3660_CLK_GATE_I2C6, "clk_gate_i2c6", "clk_i2c6_iomcu", 1, 4, 0, },
39	{ HI3660_CLK_DIV_SYSBUS, "clk_div_sysbus", "clk_mux_sysbus", 1, 7, 0, },
40	{ HI3660_CLK_DIV_320M, "clk_div_320m", "clk_320m_pll_gt", 1, 5, 0, },
41	{ HI3660_CLK_DIV_A53, "clk_div_a53hpm", "clk_a53hpm_andgt", 1, 6, 0, },
42	{ HI3660_CLK_GATE_SPI0, "clk_gate_spi0", "clk_ppll0", 1, 8, 0, },
43	{ HI3660_CLK_GATE_SPI2, "clk_gate_spi2", "clk_ppll0", 1, 8, 0, },
44	{ HI3660_PCIEPHY_REF, "clk_pciephy_ref", "clk_div_pciephy", 1, 1, 0, },
45	{ HI3660_CLK_ABB_USB, "clk_abb_usb", "clk_gate_usb_tcxo_en", 1, 1, 0 },
46	{ HI3660_VENC_VOLT_HOLD, "venc_volt_hold", "peri_volt_hold", 1, 1, 0, },
47	{ HI3660_CLK_FAC_ISP_SNCLK, "clk_isp_snclk_fac", "clk_isp_snclk_angt",
48	  1, 10, 0, },
49};
50
51static const struct hisi_gate_clock hi3660_crgctrl_gate_sep_clks[] = {
52	{ HI3660_PERI_VOLT_HOLD, "peri_volt_hold", "clkin_sys",
53	  CLK_SET_RATE_PARENT, 0x0, 0, 0, },
54	{ HI3660_HCLK_GATE_SDIO0, "hclk_gate_sdio0", "clk_div_sysbus",
55	  CLK_SET_RATE_PARENT, 0x0, 21, 0, },
56	{ HI3660_HCLK_GATE_SD, "hclk_gate_sd", "clk_div_sysbus",
57	  CLK_SET_RATE_PARENT, 0x0, 30, 0, },
58	{ HI3660_CLK_GATE_AOMM, "clk_gate_aomm", "clk_div_aomm",
59	  CLK_SET_RATE_PARENT, 0x0, 31, 0, },
60	{ HI3660_PCLK_GPIO0, "pclk_gpio0", "clk_div_cfgbus",
61	  CLK_SET_RATE_PARENT, 0x10, 0, 0, },
62	{ HI3660_PCLK_GPIO1, "pclk_gpio1", "clk_div_cfgbus",
63	  CLK_SET_RATE_PARENT, 0x10, 1, 0, },
64	{ HI3660_PCLK_GPIO2, "pclk_gpio2", "clk_div_cfgbus",
65	  CLK_SET_RATE_PARENT, 0x10, 2, 0, },
66	{ HI3660_PCLK_GPIO3, "pclk_gpio3", "clk_div_cfgbus",
67	  CLK_SET_RATE_PARENT, 0x10, 3, 0, },
68	{ HI3660_PCLK_GPIO4, "pclk_gpio4", "clk_div_cfgbus",
69	  CLK_SET_RATE_PARENT, 0x10, 4, 0, },
70	{ HI3660_PCLK_GPIO5, "pclk_gpio5", "clk_div_cfgbus",
71	  CLK_SET_RATE_PARENT, 0x10, 5, 0, },
72	{ HI3660_PCLK_GPIO6, "pclk_gpio6", "clk_div_cfgbus",
73	  CLK_SET_RATE_PARENT, 0x10, 6, 0, },
74	{ HI3660_PCLK_GPIO7, "pclk_gpio7", "clk_div_cfgbus",
75	  CLK_SET_RATE_PARENT, 0x10, 7, 0, },
76	{ HI3660_PCLK_GPIO8, "pclk_gpio8", "clk_div_cfgbus",
77	  CLK_SET_RATE_PARENT, 0x10, 8, 0, },
78	{ HI3660_PCLK_GPIO9, "pclk_gpio9", "clk_div_cfgbus",
79	  CLK_SET_RATE_PARENT, 0x10, 9, 0, },
80	{ HI3660_PCLK_GPIO10, "pclk_gpio10", "clk_div_cfgbus",
81	  CLK_SET_RATE_PARENT, 0x10, 10, 0, },
82	{ HI3660_PCLK_GPIO11, "pclk_gpio11", "clk_div_cfgbus",
83	  CLK_SET_RATE_PARENT, 0x10, 11, 0, },
84	{ HI3660_PCLK_GPIO12, "pclk_gpio12", "clk_div_cfgbus",
85	  CLK_SET_RATE_PARENT, 0x10, 12, 0, },
86	{ HI3660_PCLK_GPIO13, "pclk_gpio13", "clk_div_cfgbus",
87	  CLK_SET_RATE_PARENT, 0x10, 13, 0, },
88	{ HI3660_PCLK_GPIO14, "pclk_gpio14", "clk_div_cfgbus",
89	  CLK_SET_RATE_PARENT, 0x10, 14, 0, },
90	{ HI3660_PCLK_GPIO15, "pclk_gpio15", "clk_div_cfgbus",
91	  CLK_SET_RATE_PARENT, 0x10, 15, 0, },
92	{ HI3660_PCLK_GPIO16, "pclk_gpio16", "clk_div_cfgbus",
93	  CLK_SET_RATE_PARENT, 0x10, 16, 0, },
94	{ HI3660_PCLK_GPIO17, "pclk_gpio17", "clk_div_cfgbus",
95	  CLK_SET_RATE_PARENT, 0x10, 17, 0, },
96	{ HI3660_PCLK_GPIO18, "pclk_gpio18", "clk_div_ioperi",
97	  CLK_SET_RATE_PARENT, 0x10, 18, 0, },
98	{ HI3660_PCLK_GPIO19, "pclk_gpio19", "clk_div_ioperi",
99	  CLK_SET_RATE_PARENT, 0x10, 19, 0, },
100	{ HI3660_PCLK_GPIO20, "pclk_gpio20", "clk_div_cfgbus",
101	  CLK_SET_RATE_PARENT, 0x10, 20, 0, },
102	{ HI3660_PCLK_GPIO21, "pclk_gpio21", "clk_div_cfgbus",
103	  CLK_SET_RATE_PARENT, 0x10, 21, 0, },
104	{ HI3660_CLK_GATE_SPI3, "clk_gate_spi3", "clk_div_ioperi",
105	  CLK_SET_RATE_PARENT, 0x10, 30, 0, },
106	{ HI3660_CLK_GATE_I2C7, "clk_gate_i2c7", "clk_mux_i2c",
107	  CLK_SET_RATE_PARENT, 0x10, 31, 0, },
108	{ HI3660_CLK_GATE_I2C3, "clk_gate_i2c3", "clk_mux_i2c",
109	  CLK_SET_RATE_PARENT, 0x20, 7, 0, },
110	{ HI3660_CLK_GATE_SPI1, "clk_gate_spi1", "clk_mux_spi",
111	  CLK_SET_RATE_PARENT, 0x20, 9, 0, },
112	{ HI3660_CLK_GATE_UART1, "clk_gate_uart1", "clk_mux_uarth",
113	  CLK_SET_RATE_PARENT, 0x20, 11, 0, },
114	{ HI3660_CLK_GATE_UART2, "clk_gate_uart2", "clk_mux_uart1",
115	  CLK_SET_RATE_PARENT, 0x20, 12, 0, },
116	{ HI3660_CLK_GATE_UART4, "clk_gate_uart4", "clk_mux_uarth",
117	  CLK_SET_RATE_PARENT, 0x20, 14, 0, },
118	{ HI3660_CLK_GATE_UART5, "clk_gate_uart5", "clk_mux_uart1",
119	  CLK_SET_RATE_PARENT, 0x20, 15, 0, },
120	{ HI3660_CLK_GATE_I2C4, "clk_gate_i2c4", "clk_mux_i2c",
121	  CLK_SET_RATE_PARENT, 0x20, 27, 0, },
122	{ HI3660_CLK_GATE_DMAC, "clk_gate_dmac", "clk_div_sysbus",
123	  CLK_SET_RATE_PARENT, 0x30, 1, 0, },
124	{ HI3660_CLK_GATE_VENC, "clk_gate_venc", "clk_div_venc",
125	  CLK_SET_RATE_PARENT, 0x30, 10, 0, },
126	{ HI3660_CLK_GATE_VDEC, "clk_gate_vdec", "clk_div_vdec",
127	  CLK_SET_RATE_PARENT, 0x30, 11, 0, },
128	{ HI3660_PCLK_GATE_DSS, "pclk_gate_dss", "clk_div_cfgbus",
129	  CLK_SET_RATE_PARENT, 0x30, 12, 0, },
130	{ HI3660_ACLK_GATE_DSS, "aclk_gate_dss", "clk_gate_vivobus",
131	  CLK_SET_RATE_PARENT, 0x30, 13, 0, },
132	{ HI3660_CLK_GATE_LDI1, "clk_gate_ldi1", "clk_div_ldi1",
133	  CLK_SET_RATE_PARENT, 0x30, 14, 0, },
134	{ HI3660_CLK_GATE_LDI0, "clk_gate_ldi0", "clk_div_ldi0",
135	  CLK_SET_RATE_PARENT, 0x30, 15, 0, },
136	{ HI3660_CLK_GATE_VIVOBUS, "clk_gate_vivobus", "clk_div_vivobus",
137	  CLK_SET_RATE_PARENT, 0x30, 16, 0, },
138	{ HI3660_CLK_GATE_EDC0, "clk_gate_edc0", "clk_div_edc0",
139	  CLK_SET_RATE_PARENT, 0x30, 17, 0, },
140	{ HI3660_CLK_GATE_TXDPHY0_CFG, "clk_gate_txdphy0_cfg", "clkin_sys",
141	  CLK_SET_RATE_PARENT, 0x30, 28, 0, },
142	{ HI3660_CLK_GATE_TXDPHY0_REF, "clk_gate_txdphy0_ref", "clkin_sys",
143	  CLK_SET_RATE_PARENT, 0x30, 29, 0, },
144	{ HI3660_CLK_GATE_TXDPHY1_CFG, "clk_gate_txdphy1_cfg", "clkin_sys",
145	  CLK_SET_RATE_PARENT, 0x30, 30, 0, },
146	{ HI3660_CLK_GATE_TXDPHY1_REF, "clk_gate_txdphy1_ref", "clkin_sys",
147	  CLK_SET_RATE_PARENT, 0x30, 31, 0, },
148	{ HI3660_ACLK_GATE_USB3OTG, "aclk_gate_usb3otg", "clk_div_mmc0bus",
149	  CLK_SET_RATE_PARENT, 0x40, 1, 0, },
150	{ HI3660_CLK_GATE_SPI4, "clk_gate_spi4", "clk_mux_spi",
151	  CLK_SET_RATE_PARENT, 0x40, 4, 0, },
152	{ HI3660_CLK_GATE_SD, "clk_gate_sd", "clk_mux_sd_sys",
153	  CLK_SET_RATE_PARENT, 0x40, 17, 0, },
154	{ HI3660_CLK_GATE_SDIO0, "clk_gate_sdio0", "clk_mux_sdio_sys",
155	  CLK_SET_RATE_PARENT, 0x40, 19, 0, },
156	{ HI3660_CLK_GATE_ISP_SNCLK0, "clk_gate_isp_snclk0",
157	  "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 16, 0, },
158	{ HI3660_CLK_GATE_ISP_SNCLK1, "clk_gate_isp_snclk1",
159	  "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 17, 0, },
160	{ HI3660_CLK_GATE_ISP_SNCLK2, "clk_gate_isp_snclk2",
161	  "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 18, 0, },
162	/*
163	 * clk_gate_ufs_subsys is a system bus clock, mark it as critical
164	 * clock and keep it on for system suspend and resume.
165	 */
166	{ HI3660_CLK_GATE_UFS_SUBSYS, "clk_gate_ufs_subsys", "clk_div_sysbus",
167	  CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x50, 21, 0, },
168	{ HI3660_PCLK_GATE_DSI0, "pclk_gate_dsi0", "clk_div_cfgbus",
169	  CLK_SET_RATE_PARENT, 0x50, 28, 0, },
170	{ HI3660_PCLK_GATE_DSI1, "pclk_gate_dsi1", "clk_div_cfgbus",
171	  CLK_SET_RATE_PARENT, 0x50, 29, 0, },
172	{ HI3660_ACLK_GATE_PCIE, "aclk_gate_pcie", "clk_div_mmc1bus",
173	  CLK_SET_RATE_PARENT, 0x420, 5, 0, },
174	{ HI3660_PCLK_GATE_PCIE_SYS, "pclk_gate_pcie_sys", "clk_div_mmc1bus",
175	  CLK_SET_RATE_PARENT, 0x420, 7, 0, },
176	{ HI3660_CLK_GATE_PCIEAUX, "clk_gate_pcieaux", "clkin_sys",
177	  CLK_SET_RATE_PARENT, 0x420, 8, 0, },
178	{ HI3660_PCLK_GATE_PCIE_PHY, "pclk_gate_pcie_phy", "clk_div_mmc1bus",
179	  CLK_SET_RATE_PARENT, 0x420, 9, 0, },
180};
181
182static const struct hisi_gate_clock hi3660_crgctrl_gate_clks[] = {
183	{ HI3660_CLK_ANDGT_LDI0, "clk_andgt_ldi0", "clk_mux_ldi0",
184	  CLK_SET_RATE_PARENT, 0xf0, 6, CLK_GATE_HIWORD_MASK, },
185	{ HI3660_CLK_ANDGT_LDI1, "clk_andgt_ldi1", "clk_mux_ldi1",
186	  CLK_SET_RATE_PARENT, 0xf0, 7, CLK_GATE_HIWORD_MASK, },
187	{ HI3660_CLK_ANDGT_EDC0, "clk_andgt_edc0", "clk_mux_edc0",
188	  CLK_SET_RATE_PARENT, 0xf0, 8, CLK_GATE_HIWORD_MASK, },
189	{ HI3660_CLK_ANDGT_VDEC, "clk_andgt_vdec", "clk_mux_vdec",
190	  CLK_SET_RATE_PARENT, 0xf0, 15, CLK_GATE_HIWORD_MASK, },
191	{ HI3660_CLK_ANDGT_VENC, "clk_andgt_venc", "clk_mux_venc",
192	  CLK_SET_RATE_PARENT, 0xf4, 0, CLK_GATE_HIWORD_MASK, },
193	{ HI3660_CLK_GATE_UFSPHY_GT, "clk_gate_ufsphy_gt", "clk_div_ufsperi",
194	  CLK_SET_RATE_PARENT, 0xf4, 1, CLK_GATE_HIWORD_MASK, },
195	{ HI3660_CLK_ANDGT_MMC, "clk_andgt_mmc", "clk_mux_mmc_pll",
196	  CLK_SET_RATE_PARENT, 0xf4, 2, CLK_GATE_HIWORD_MASK, },
197	{ HI3660_CLK_ANDGT_SD, "clk_andgt_sd", "clk_mux_sd_pll",
198	  CLK_SET_RATE_PARENT, 0xf4, 3, CLK_GATE_HIWORD_MASK, },
199	{ HI3660_CLK_A53HPM_ANDGT, "clk_a53hpm_andgt", "clk_mux_a53hpm",
200	  CLK_SET_RATE_PARENT, 0xf4, 7, CLK_GATE_HIWORD_MASK, },
201	{ HI3660_CLK_ANDGT_SDIO, "clk_andgt_sdio", "clk_mux_sdio_pll",
202	  CLK_SET_RATE_PARENT, 0xf4, 8, CLK_GATE_HIWORD_MASK, },
203	{ HI3660_CLK_ANDGT_UART0, "clk_andgt_uart0", "clk_div_320m",
204	  CLK_SET_RATE_PARENT, 0xf4, 9, CLK_GATE_HIWORD_MASK, },
205	{ HI3660_CLK_ANDGT_UART1, "clk_andgt_uart1", "clk_div_320m",
206	  CLK_SET_RATE_PARENT, 0xf4, 10, CLK_GATE_HIWORD_MASK, },
207	{ HI3660_CLK_ANDGT_UARTH, "clk_andgt_uarth", "clk_div_320m",
208	  CLK_SET_RATE_PARENT, 0xf4, 11, CLK_GATE_HIWORD_MASK, },
209	{ HI3660_CLK_ANDGT_SPI, "clk_andgt_spi", "clk_div_320m",
210	  CLK_SET_RATE_PARENT, 0xf4, 13, CLK_GATE_HIWORD_MASK, },
211	{ HI3660_CLK_VIVOBUS_ANDGT, "clk_vivobus_andgt", "clk_mux_vivobus",
212	  CLK_SET_RATE_PARENT, 0xf8, 1, CLK_GATE_HIWORD_MASK, },
213	{ HI3660_CLK_AOMM_ANDGT, "clk_aomm_andgt", "clk_ppll2",
214	  CLK_SET_RATE_PARENT, 0xf8, 3, CLK_GATE_HIWORD_MASK, },
215	{ HI3660_CLK_320M_PLL_GT, "clk_320m_pll_gt", "clk_mux_320m",
216	  CLK_SET_RATE_PARENT, 0xf8, 10, 0, },
217	{ HI3660_CLK_ANGT_ISP_SNCLK, "clk_isp_snclk_angt", "clk_div_a53hpm",
218	  CLK_SET_RATE_PARENT, 0x108, 2, CLK_GATE_HIWORD_MASK, },
219	{ HI3660_AUTODIV_EMMC0BUS, "autodiv_emmc0bus", "autodiv_sysbus",
220	  CLK_SET_RATE_PARENT, 0x404, 1, CLK_GATE_HIWORD_MASK, },
221	{ HI3660_AUTODIV_SYSBUS, "autodiv_sysbus", "clk_div_sysbus",
222	  CLK_SET_RATE_PARENT, 0x404, 5, CLK_GATE_HIWORD_MASK, },
223	{ HI3660_CLK_GATE_UFSPHY_CFG, "clk_gate_ufsphy_cfg",
224	  "clk_div_ufsphy_cfg", CLK_SET_RATE_PARENT, 0x420, 12, 0, },
225	{ HI3660_CLK_GATE_UFSIO_REF, "clk_gate_ufsio_ref",
226	  "clk_gate_ufs_tcxo_en", CLK_SET_RATE_PARENT, 0x420, 14, 0, },
227};
228
229static const char *const
230clk_mux_sysbus_p[] = {"clk_ppll1", "clk_ppll0"};
231static const char *const
232clk_mux_sdio_sys_p[] = {"clk_factor_mmc", "clk_div_sdio",};
233static const char *const
234clk_mux_sd_sys_p[] = {"clk_factor_mmc", "clk_div_sd",};
235static const char *const
236clk_mux_pll_p[] = {"clk_ppll0", "clk_ppll1", "clk_ppll2", "clk_ppll2",};
237static const char *const
238clk_mux_pll0123_p[] = {"clk_ppll0", "clk_ppll1", "clk_ppll2", "clk_ppll3",};
239static const char *const
240clk_mux_edc0_p[] = {"clk_inv", "clk_ppll0", "clk_ppll1", "clk_inv",
241		    "clk_ppll2", "clk_inv", "clk_inv", "clk_inv",
242		    "clk_ppll3", "clk_inv", "clk_inv", "clk_inv",
243		    "clk_inv", "clk_inv", "clk_inv", "clk_inv",};
244static const char *const
245clk_mux_ldi0_p[] = {"clk_inv", "clk_ppll0", "clk_ppll2", "clk_inv",
246		    "clk_ppll1", "clk_inv", "clk_inv", "clk_inv",
247		    "clk_ppll3", "clk_inv", "clk_inv", "clk_inv",
248		    "clk_inv", "clk_inv", "clk_inv", "clk_inv",};
249static const char *const
250clk_mux_uart0_p[] = {"clkin_sys", "clk_div_uart0",};
251static const char *const
252clk_mux_uart1_p[] = {"clkin_sys", "clk_div_uart1",};
253static const char *const
254clk_mux_uarth_p[] = {"clkin_sys", "clk_div_uarth",};
255static const char *const
256clk_mux_pll02p[] = {"clk_ppll0", "clk_ppll2",};
257static const char *const
258clk_mux_ioperi_p[] = {"clk_div_320m", "clk_div_a53hpm",};
259static const char *const
260clk_mux_spi_p[] = {"clkin_sys", "clk_div_spi",};
261static const char *const
262clk_mux_i2c_p[] = {"clkin_sys", "clk_div_i2c",};
263static const char *const
264clk_mux_venc_p[] = {"clk_ppll0", "clk_ppll1", "clk_ppll3", "clk_ppll3",};
265static const char *const
266clk_mux_isp_snclk_p[] = {"clkin_sys", "clk_isp_snclk_div"};
267
268static const struct hisi_mux_clock hi3660_crgctrl_mux_clks[] = {
269	{ HI3660_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sysbus_p,
270	  ARRAY_SIZE(clk_mux_sysbus_p), CLK_SET_RATE_PARENT, 0xac, 0, 1,
271	  CLK_MUX_HIWORD_MASK, },
272	{ HI3660_CLK_MUX_UART0, "clk_mux_uart0", clk_mux_uart0_p,
273	  ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT, 0xac, 2, 1,
274	  CLK_MUX_HIWORD_MASK, },
275	{ HI3660_CLK_MUX_UART1, "clk_mux_uart1", clk_mux_uart1_p,
276	  ARRAY_SIZE(clk_mux_uart1_p), CLK_SET_RATE_PARENT, 0xac, 3, 1,
277	  CLK_MUX_HIWORD_MASK, },
278	{ HI3660_CLK_MUX_UARTH, "clk_mux_uarth", clk_mux_uarth_p,
279	  ARRAY_SIZE(clk_mux_uarth_p), CLK_SET_RATE_PARENT, 0xac, 4, 1,
280	  CLK_MUX_HIWORD_MASK, },
281	{ HI3660_CLK_MUX_SPI, "clk_mux_spi", clk_mux_spi_p,
282	  ARRAY_SIZE(clk_mux_spi_p), CLK_SET_RATE_PARENT, 0xac, 8, 1,
283	  CLK_MUX_HIWORD_MASK, },
284	{ HI3660_CLK_MUX_I2C, "clk_mux_i2c", clk_mux_i2c_p,
285	  ARRAY_SIZE(clk_mux_i2c_p), CLK_SET_RATE_PARENT, 0xac, 13, 1,
286	  CLK_MUX_HIWORD_MASK, },
287	{ HI3660_CLK_MUX_MMC_PLL, "clk_mux_mmc_pll", clk_mux_pll02p,
288	  ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0xb4, 0, 1,
289	  CLK_MUX_HIWORD_MASK, },
290	{ HI3660_CLK_MUX_LDI1, "clk_mux_ldi1", clk_mux_ldi0_p,
291	  ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT, 0xb4, 8, 4,
292	  CLK_MUX_HIWORD_MASK, },
293	{ HI3660_CLK_MUX_LDI0, "clk_mux_ldi0", clk_mux_ldi0_p,
294	  ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT, 0xb4, 12, 4,
295	  CLK_MUX_HIWORD_MASK, },
296	{ HI3660_CLK_MUX_SD_PLL, "clk_mux_sd_pll", clk_mux_pll_p,
297	  ARRAY_SIZE(clk_mux_pll_p), CLK_SET_RATE_PARENT, 0xb8, 4, 2,
298	  CLK_MUX_HIWORD_MASK, },
299	{ HI3660_CLK_MUX_SD_SYS, "clk_mux_sd_sys", clk_mux_sd_sys_p,
300	  ARRAY_SIZE(clk_mux_sd_sys_p), CLK_SET_RATE_PARENT, 0xb8, 6, 1,
301	  CLK_MUX_HIWORD_MASK, },
302	{ HI3660_CLK_MUX_EDC0, "clk_mux_edc0", clk_mux_edc0_p,
303	  ARRAY_SIZE(clk_mux_edc0_p), CLK_SET_RATE_PARENT, 0xbc, 6, 4,
304	  CLK_MUX_HIWORD_MASK, },
305	{ HI3660_CLK_MUX_SDIO_SYS, "clk_mux_sdio_sys", clk_mux_sdio_sys_p,
306	  ARRAY_SIZE(clk_mux_sdio_sys_p), CLK_SET_RATE_PARENT, 0xc0, 6, 1,
307	  CLK_MUX_HIWORD_MASK, },
308	{ HI3660_CLK_MUX_SDIO_PLL, "clk_mux_sdio_pll", clk_mux_pll_p,
309	  ARRAY_SIZE(clk_mux_pll_p), CLK_SET_RATE_PARENT, 0xc0, 4, 2,
310	  CLK_MUX_HIWORD_MASK, },
311	{ HI3660_CLK_MUX_VENC, "clk_mux_venc", clk_mux_venc_p,
312	  ARRAY_SIZE(clk_mux_venc_p), CLK_SET_RATE_PARENT, 0xc8, 11, 2,
313	  CLK_MUX_HIWORD_MASK, },
314	{ HI3660_CLK_MUX_VDEC, "clk_mux_vdec", clk_mux_pll0123_p,
315	  ARRAY_SIZE(clk_mux_pll0123_p), CLK_SET_RATE_PARENT, 0xcc, 5, 2,
316	  CLK_MUX_HIWORD_MASK, },
317	{ HI3660_CLK_MUX_VIVOBUS, "clk_mux_vivobus", clk_mux_pll0123_p,
318	  ARRAY_SIZE(clk_mux_pll0123_p), CLK_SET_RATE_PARENT, 0xd0, 12, 2,
319	  CLK_MUX_HIWORD_MASK, },
320	{ HI3660_CLK_MUX_A53HPM, "clk_mux_a53hpm", clk_mux_pll02p,
321	  ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0xd4, 9, 1,
322	  CLK_MUX_HIWORD_MASK, },
323	{ HI3660_CLK_MUX_320M, "clk_mux_320m", clk_mux_pll02p,
324	  ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0x100, 0, 1,
325	  CLK_MUX_HIWORD_MASK, },
326	{ HI3660_CLK_MUX_ISP_SNCLK, "clk_isp_snclk_mux", clk_mux_isp_snclk_p,
327	  ARRAY_SIZE(clk_mux_isp_snclk_p), CLK_SET_RATE_PARENT, 0x108, 3, 1,
328	  CLK_MUX_HIWORD_MASK, },
329	{ HI3660_CLK_MUX_IOPERI, "clk_mux_ioperi", clk_mux_ioperi_p,
330	  ARRAY_SIZE(clk_mux_ioperi_p), CLK_SET_RATE_PARENT, 0x108, 10, 1,
331	  CLK_MUX_HIWORD_MASK, },
332};
333
334static const struct hisi_divider_clock hi3660_crgctrl_divider_clks[] = {
335	{ HI3660_CLK_DIV_UART0, "clk_div_uart0", "clk_andgt_uart0",
336	  CLK_SET_RATE_PARENT, 0xb0, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
337	{ HI3660_CLK_DIV_UART1, "clk_div_uart1", "clk_andgt_uart1",
338	  CLK_SET_RATE_PARENT, 0xb0, 8, 4, CLK_DIVIDER_HIWORD_MASK, },
339	{ HI3660_CLK_DIV_UARTH, "clk_div_uarth", "clk_andgt_uarth",
340	  CLK_SET_RATE_PARENT, 0xb0, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
341	{ HI3660_CLK_DIV_MMC, "clk_div_mmc", "clk_andgt_mmc",
342	  CLK_SET_RATE_PARENT, 0xb4, 3, 4, CLK_DIVIDER_HIWORD_MASK, },
343	{ HI3660_CLK_DIV_SD, "clk_div_sd", "clk_andgt_sd",
344	  CLK_SET_RATE_PARENT, 0xb8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
345	{ HI3660_CLK_DIV_EDC0, "clk_div_edc0", "clk_andgt_edc0",
346	  CLK_SET_RATE_PARENT, 0xbc, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
347	{ HI3660_CLK_DIV_LDI0, "clk_div_ldi0", "clk_andgt_ldi0",
348	  CLK_SET_RATE_PARENT, 0xbc, 10, 6, CLK_DIVIDER_HIWORD_MASK, },
349	{ HI3660_CLK_DIV_SDIO, "clk_div_sdio", "clk_andgt_sdio",
350	  CLK_SET_RATE_PARENT, 0xc0, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
351	{ HI3660_CLK_DIV_LDI1, "clk_div_ldi1", "clk_andgt_ldi1",
352	  CLK_SET_RATE_PARENT, 0xc0, 8, 6, CLK_DIVIDER_HIWORD_MASK, },
353	{ HI3660_CLK_DIV_SPI, "clk_div_spi", "clk_andgt_spi",
354	  CLK_SET_RATE_PARENT, 0xc4, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
355	{ HI3660_CLK_DIV_VENC, "clk_div_venc", "clk_andgt_venc",
356	  CLK_SET_RATE_PARENT, 0xc8, 6, 5, CLK_DIVIDER_HIWORD_MASK, },
357	{ HI3660_CLK_DIV_VDEC, "clk_div_vdec", "clk_andgt_vdec",
358	  CLK_SET_RATE_PARENT, 0xcc, 0, 5, CLK_DIVIDER_HIWORD_MASK,  },
359	{ HI3660_CLK_DIV_VIVOBUS, "clk_div_vivobus", "clk_vivobus_andgt",
360	  CLK_SET_RATE_PARENT, 0xd0, 7, 5, CLK_DIVIDER_HIWORD_MASK, },
361	{ HI3660_CLK_DIV_I2C, "clk_div_i2c", "clk_div_320m",
362	  CLK_SET_RATE_PARENT, 0xe8, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
363	{ HI3660_CLK_DIV_UFSPHY, "clk_div_ufsphy_cfg", "clk_gate_ufsphy_gt",
364	  CLK_SET_RATE_PARENT, 0xe8, 9, 2, CLK_DIVIDER_HIWORD_MASK, },
365	{ HI3660_CLK_DIV_CFGBUS, "clk_div_cfgbus", "clk_div_sysbus",
366	  CLK_SET_RATE_PARENT, 0xec, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
367	{ HI3660_CLK_DIV_MMC0BUS, "clk_div_mmc0bus", "autodiv_emmc0bus",
368	  CLK_SET_RATE_PARENT, 0xec, 2, 1, CLK_DIVIDER_HIWORD_MASK, },
369	{ HI3660_CLK_DIV_MMC1BUS, "clk_div_mmc1bus", "clk_div_sysbus",
370	  CLK_SET_RATE_PARENT, 0xec, 3, 1, CLK_DIVIDER_HIWORD_MASK, },
371	{ HI3660_CLK_DIV_UFSPERI, "clk_div_ufsperi", "clk_gate_ufs_subsys",
372	  CLK_SET_RATE_PARENT, 0xec, 14, 1, CLK_DIVIDER_HIWORD_MASK, },
373	{ HI3660_CLK_DIV_AOMM, "clk_div_aomm", "clk_aomm_andgt",
374	  CLK_SET_RATE_PARENT, 0x100, 7, 4, CLK_DIVIDER_HIWORD_MASK, },
375	{ HI3660_CLK_DIV_ISP_SNCLK, "clk_isp_snclk_div", "clk_isp_snclk_fac",
376	  CLK_SET_RATE_PARENT, 0x108, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
377	{ HI3660_CLK_DIV_IOPERI, "clk_div_ioperi", "clk_mux_ioperi",
378	  CLK_SET_RATE_PARENT, 0x108, 11, 4, CLK_DIVIDER_HIWORD_MASK, },
379};
380
381/* clk_pmuctrl */
382/* pmu register need shift 2 bits */
383static const struct hisi_gate_clock hi3660_pmu_gate_clks[] = {
384	{ HI3660_GATE_ABB_192, "clk_gate_abb_192", "clkin_sys",
385	  CLK_SET_RATE_PARENT, (0x10a << 2), 3, 0, },
386};
387
388/* clk_pctrl */
389static const struct hisi_gate_clock hi3660_pctrl_gate_clks[] = {
390	{ HI3660_GATE_UFS_TCXO_EN, "clk_gate_ufs_tcxo_en",
391	  "clk_gate_abb_192", CLK_SET_RATE_PARENT, 0x10, 0,
392	  CLK_GATE_HIWORD_MASK, },
393	{ HI3660_GATE_USB_TCXO_EN, "clk_gate_usb_tcxo_en", "clk_gate_abb_192",
394	  CLK_SET_RATE_PARENT, 0x10, 1, CLK_GATE_HIWORD_MASK, },
395};
396
397/* clk_sctrl */
398static const struct hisi_gate_clock hi3660_sctrl_gate_sep_clks[] = {
399	{ HI3660_PCLK_AO_GPIO0, "pclk_ao_gpio0", "clk_div_aobus",
400	  CLK_SET_RATE_PARENT, 0x160, 11, 0, },
401	{ HI3660_PCLK_AO_GPIO1, "pclk_ao_gpio1", "clk_div_aobus",
402	  CLK_SET_RATE_PARENT, 0x160, 12, 0, },
403	{ HI3660_PCLK_AO_GPIO2, "pclk_ao_gpio2", "clk_div_aobus",
404	  CLK_SET_RATE_PARENT, 0x160, 13, 0, },
405	{ HI3660_PCLK_AO_GPIO3, "pclk_ao_gpio3", "clk_div_aobus",
406	  CLK_SET_RATE_PARENT, 0x160, 14, 0, },
407	{ HI3660_PCLK_AO_GPIO4, "pclk_ao_gpio4", "clk_div_aobus",
408	  CLK_SET_RATE_PARENT, 0x160, 21, 0, },
409	{ HI3660_PCLK_AO_GPIO5, "pclk_ao_gpio5", "clk_div_aobus",
410	  CLK_SET_RATE_PARENT, 0x160, 22, 0, },
411	{ HI3660_PCLK_AO_GPIO6, "pclk_ao_gpio6", "clk_div_aobus",
412	  CLK_SET_RATE_PARENT, 0x160, 25, 0, },
413	{ HI3660_PCLK_GATE_MMBUF, "pclk_gate_mmbuf", "pclk_div_mmbuf",
414	  CLK_SET_RATE_PARENT, 0x170, 23, 0, },
415	{ HI3660_CLK_GATE_DSS_AXI_MM, "clk_gate_dss_axi_mm", "aclk_mux_mmbuf",
416	  CLK_SET_RATE_PARENT, 0x170, 24, 0, },
417};
418
419static const struct hisi_gate_clock hi3660_sctrl_gate_clks[] = {
420	{ HI3660_PCLK_MMBUF_ANDGT, "pclk_mmbuf_andgt", "clk_sw_mmbuf",
421	  CLK_SET_RATE_PARENT, 0x258, 7, CLK_GATE_HIWORD_MASK, },
422	{ HI3660_CLK_MMBUF_PLL_ANDGT, "clk_mmbuf_pll_andgt", "clk_ppll0",
423	  CLK_SET_RATE_PARENT, 0x260, 11, CLK_DIVIDER_HIWORD_MASK, },
424	{ HI3660_CLK_FLL_MMBUF_ANDGT, "clk_fll_mmbuf_andgt", "clk_fll_src",
425	  CLK_SET_RATE_PARENT, 0x260, 12, CLK_DIVIDER_HIWORD_MASK, },
426	{ HI3660_CLK_SYS_MMBUF_ANDGT, "clk_sys_mmbuf_andgt", "clkin_sys",
427	  CLK_SET_RATE_PARENT, 0x260, 13, CLK_DIVIDER_HIWORD_MASK, },
428	{ HI3660_CLK_GATE_PCIEPHY_GT, "clk_gate_pciephy_gt", "clk_ppll0",
429	  CLK_SET_RATE_PARENT, 0x268, 11, CLK_DIVIDER_HIWORD_MASK, },
430};
431
432static const char *const
433aclk_mux_mmbuf_p[] = {"aclk_div_mmbuf", "clk_gate_aomm",};
434static const char *const
435clk_sw_mmbuf_p[] = {"clk_sys_mmbuf_andgt", "clk_fll_mmbuf_andgt",
436		    "aclk_mux_mmbuf", "aclk_mux_mmbuf"};
437
438static const struct hisi_mux_clock hi3660_sctrl_mux_clks[] = {
439	{ HI3660_ACLK_MUX_MMBUF, "aclk_mux_mmbuf", aclk_mux_mmbuf_p,
440	  ARRAY_SIZE(aclk_mux_mmbuf_p), CLK_SET_RATE_PARENT, 0x250, 12, 1,
441	  CLK_MUX_HIWORD_MASK, },
442	{ HI3660_CLK_SW_MMBUF, "clk_sw_mmbuf", clk_sw_mmbuf_p,
443	  ARRAY_SIZE(clk_sw_mmbuf_p), CLK_SET_RATE_PARENT, 0x258, 8, 2,
444	  CLK_MUX_HIWORD_MASK, },
445};
446
447static const struct hisi_divider_clock hi3660_sctrl_divider_clks[] = {
448	{ HI3660_CLK_DIV_AOBUS, "clk_div_aobus", "clk_ppll0",
449	  CLK_SET_RATE_PARENT, 0x254, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
450	{ HI3660_PCLK_DIV_MMBUF, "pclk_div_mmbuf", "pclk_mmbuf_andgt",
451	  CLK_SET_RATE_PARENT, 0x258, 10, 2, CLK_DIVIDER_HIWORD_MASK, },
452	{ HI3660_ACLK_DIV_MMBUF, "aclk_div_mmbuf", "clk_mmbuf_pll_andgt",
453	  CLK_SET_RATE_PARENT, 0x258, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
454	{ HI3660_CLK_DIV_PCIEPHY, "clk_div_pciephy", "clk_gate_pciephy_gt",
455	  CLK_SET_RATE_PARENT, 0x268, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
456};
457
458/* clk_iomcu */
459static const struct hisi_gate_clock hi3660_iomcu_gate_sep_clks[] = {
460	{ HI3660_CLK_I2C0_IOMCU, "clk_i2c0_iomcu", "clk_fll_src",
461	  CLK_SET_RATE_PARENT, 0x10, 3, 0, },
462	{ HI3660_CLK_I2C1_IOMCU, "clk_i2c1_iomcu", "clk_fll_src",
463	  CLK_SET_RATE_PARENT, 0x10, 4, 0, },
464	{ HI3660_CLK_I2C2_IOMCU, "clk_i2c2_iomcu", "clk_fll_src",
465	  CLK_SET_RATE_PARENT, 0x10, 5, 0, },
466	{ HI3660_CLK_I2C6_IOMCU, "clk_i2c6_iomcu", "clk_fll_src",
467	  CLK_SET_RATE_PARENT, 0x10, 27, 0, },
468	{ HI3660_CLK_IOMCU_PERI0, "iomcu_peri0", "clk_ppll0",
469	  CLK_SET_RATE_PARENT, 0x90, 0, 0, },
470};
471
472static struct hisi_clock_data *clk_crgctrl_data;
473
474static void hi3660_clk_iomcu_init(struct device_node *np)
475{
476	struct hisi_clock_data *clk_data;
477	int nr = ARRAY_SIZE(hi3660_iomcu_gate_sep_clks);
478
479	clk_data = hisi_clk_init(np, nr);
480	if (!clk_data)
481		return;
482
483	hisi_clk_register_gate_sep(hi3660_iomcu_gate_sep_clks,
484				   ARRAY_SIZE(hi3660_iomcu_gate_sep_clks),
485				   clk_data);
486}
487
488static void hi3660_clk_pmuctrl_init(struct device_node *np)
489{
490	struct hisi_clock_data *clk_data;
491	int nr = ARRAY_SIZE(hi3660_pmu_gate_clks);
492
493	clk_data = hisi_clk_init(np, nr);
494	if (!clk_data)
495		return;
496
497	hisi_clk_register_gate(hi3660_pmu_gate_clks,
498			       ARRAY_SIZE(hi3660_pmu_gate_clks), clk_data);
499}
500
501static void hi3660_clk_pctrl_init(struct device_node *np)
502{
503	struct hisi_clock_data *clk_data;
504	int nr = ARRAY_SIZE(hi3660_pctrl_gate_clks);
505
506	clk_data = hisi_clk_init(np, nr);
507	if (!clk_data)
508		return;
509	hisi_clk_register_gate(hi3660_pctrl_gate_clks,
510			       ARRAY_SIZE(hi3660_pctrl_gate_clks), clk_data);
511}
512
513static void hi3660_clk_sctrl_init(struct device_node *np)
514{
515	struct hisi_clock_data *clk_data;
516	int nr = ARRAY_SIZE(hi3660_sctrl_gate_clks) +
517		 ARRAY_SIZE(hi3660_sctrl_gate_sep_clks) +
518		 ARRAY_SIZE(hi3660_sctrl_mux_clks) +
519		 ARRAY_SIZE(hi3660_sctrl_divider_clks);
520
521	clk_data = hisi_clk_init(np, nr);
522	if (!clk_data)
523		return;
524	hisi_clk_register_gate(hi3660_sctrl_gate_clks,
525			       ARRAY_SIZE(hi3660_sctrl_gate_clks), clk_data);
526	hisi_clk_register_gate_sep(hi3660_sctrl_gate_sep_clks,
527				   ARRAY_SIZE(hi3660_sctrl_gate_sep_clks),
528				   clk_data);
529	hisi_clk_register_mux(hi3660_sctrl_mux_clks,
530			      ARRAY_SIZE(hi3660_sctrl_mux_clks), clk_data);
531	hisi_clk_register_divider(hi3660_sctrl_divider_clks,
532				  ARRAY_SIZE(hi3660_sctrl_divider_clks),
533				  clk_data);
534}
535
536static void hi3660_clk_crgctrl_early_init(struct device_node *np)
537{
538	int nr = ARRAY_SIZE(hi3660_fixed_rate_clks) +
539		 ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks) +
540		 ARRAY_SIZE(hi3660_crgctrl_gate_clks) +
541		 ARRAY_SIZE(hi3660_crgctrl_mux_clks) +
542		 ARRAY_SIZE(hi3660_crg_fixed_factor_clks) +
543		 ARRAY_SIZE(hi3660_crgctrl_divider_clks);
544	int i;
545
546	clk_crgctrl_data = hisi_clk_init(np, nr);
547	if (!clk_crgctrl_data)
548		return;
549
550	for (i = 0; i < nr; i++)
551		clk_crgctrl_data->clk_data.clks[i] = ERR_PTR(-EPROBE_DEFER);
552
553	hisi_clk_register_fixed_rate(hi3660_fixed_rate_clks,
554				     ARRAY_SIZE(hi3660_fixed_rate_clks),
555				     clk_crgctrl_data);
556}
557CLK_OF_DECLARE_DRIVER(hi3660_clk_crgctrl, "hisilicon,hi3660-crgctrl",
558		      hi3660_clk_crgctrl_early_init);
559
560static void hi3660_clk_crgctrl_init(struct device_node *np)
561{
562	struct clk **clks;
563	int i;
564
565	if (!clk_crgctrl_data)
566		hi3660_clk_crgctrl_early_init(np);
567
568	/* clk_crgctrl_data initialization failed */
569	if (!clk_crgctrl_data)
570		return;
571
572	hisi_clk_register_gate_sep(hi3660_crgctrl_gate_sep_clks,
573				   ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks),
574				   clk_crgctrl_data);
575	hisi_clk_register_gate(hi3660_crgctrl_gate_clks,
576			       ARRAY_SIZE(hi3660_crgctrl_gate_clks),
577			       clk_crgctrl_data);
578	hisi_clk_register_mux(hi3660_crgctrl_mux_clks,
579			      ARRAY_SIZE(hi3660_crgctrl_mux_clks),
580			      clk_crgctrl_data);
581	hisi_clk_register_fixed_factor(hi3660_crg_fixed_factor_clks,
582				       ARRAY_SIZE(hi3660_crg_fixed_factor_clks),
583				       clk_crgctrl_data);
584	hisi_clk_register_divider(hi3660_crgctrl_divider_clks,
585				  ARRAY_SIZE(hi3660_crgctrl_divider_clks),
586				  clk_crgctrl_data);
587
588	clks = clk_crgctrl_data->clk_data.clks;
589	for (i = 0; i < clk_crgctrl_data->clk_data.clk_num; i++) {
590		if (IS_ERR(clks[i]) && PTR_ERR(clks[i]) != -EPROBE_DEFER)
591			pr_err("Failed to register crgctrl clock[%d] err=%ld\n",
592			       i, PTR_ERR(clks[i]));
593	}
594}
595
596static const struct of_device_id hi3660_clk_match_table[] = {
597	{ .compatible = "hisilicon,hi3660-crgctrl",
598	  .data = hi3660_clk_crgctrl_init },
599	{ .compatible = "hisilicon,hi3660-pctrl",
600	  .data = hi3660_clk_pctrl_init },
601	{ .compatible = "hisilicon,hi3660-pmuctrl",
602	  .data = hi3660_clk_pmuctrl_init },
603	{ .compatible = "hisilicon,hi3660-sctrl",
604	  .data = hi3660_clk_sctrl_init },
605	{ .compatible = "hisilicon,hi3660-iomcu",
606	  .data = hi3660_clk_iomcu_init },
607	{ }
608};
609
610static int hi3660_clk_probe(struct platform_device *pdev)
611{
612	struct device *dev = &pdev->dev;
613	struct device_node *np = pdev->dev.of_node;
614	void (*init_func)(struct device_node *np);
615
616	init_func = of_device_get_match_data(dev);
617	if (!init_func)
618		return -ENODEV;
619
620	init_func(np);
621
622	return 0;
623}
624
625static struct platform_driver hi3660_clk_driver = {
626	.probe          = hi3660_clk_probe,
627	.driver         = {
628		.name   = "hi3660-clk",
629		.of_match_table = hi3660_clk_match_table,
630	},
631};
632
633static int __init hi3660_clk_init(void)
634{
635	return platform_driver_register(&hi3660_clk_driver);
636}
637core_initcall(hi3660_clk_init);
638