1// SPDX-License-Identifier: GPL-2.0
2#include <linux/kernel.h>
3#include <linux/clk-provider.h>
4#include <linux/of_address.h>
5#include <linux/init.h>
6#include <linux/io.h>
7
8#define CLK_COUNT 4 /* cpu_clk, sys_clk, usb_clk, sdio_clk */
9static struct clk *clks[CLK_COUNT];
10static struct clk_onecell_data clk_data = { clks, CLK_COUNT };
11
12#define SYSCLK_DIV	0x20
13#define CPUCLK_DIV	0x24
14#define DIV_BYPASS	BIT(23)
15
16/*** CLKGEN_PLL ***/
17#define extract_pll_n(val)	((val >>  0) & ((1u << 7) - 1))
18#define extract_pll_k(val)	((val >> 13) & ((1u << 3) - 1))
19#define extract_pll_m(val)	((val >> 16) & ((1u << 3) - 1))
20#define extract_pll_isel(val)	((val >> 24) & ((1u << 3) - 1))
21
22static void __init make_pll(int idx, const char *parent, void __iomem *base)
23{
24	char name[8];
25	u32 val, mul, div;
26
27	sprintf(name, "pll%d", idx);
28	val = readl(base + idx * 8);
29	mul =  extract_pll_n(val) + 1;
30	div = (extract_pll_m(val) + 1) << extract_pll_k(val);
31	clk_register_fixed_factor(NULL, name, parent, 0, mul, div);
32	if (extract_pll_isel(val) != 1)
33		panic("%s: input not set to XTAL_IN\n", name);
34}
35
36static void __init make_cd(int idx, void __iomem *base)
37{
38	char name[8];
39	u32 val, mul, div;
40
41	sprintf(name, "cd%d", idx);
42	val = readl(base + idx * 8);
43	mul =  1 << 27;
44	div = (2 << 27) + val;
45	clk_register_fixed_factor(NULL, name, "pll2", 0, mul, div);
46	if (val > 0xf0000000)
47		panic("%s: unsupported divider %x\n", name, val);
48}
49
50static void __init tango4_clkgen_setup(struct device_node *np)
51{
52	struct clk **pp = clk_data.clks;
53	void __iomem *base = of_iomap(np, 0);
54	const char *parent = of_clk_get_parent_name(np, 0);
55
56	if (!base)
57		panic("%pOFn: invalid address\n", np);
58
59	if (readl(base + CPUCLK_DIV) & DIV_BYPASS)
60		panic("%pOFn: unsupported cpuclk setup\n", np);
61
62	if (readl(base + SYSCLK_DIV) & DIV_BYPASS)
63		panic("%pOFn: unsupported sysclk setup\n", np);
64
65	writel(0x100, base + CPUCLK_DIV); /* disable frequency ramping */
66
67	make_pll(0, parent, base);
68	make_pll(1, parent, base);
69	make_pll(2, parent, base);
70	make_cd(2, base + 0x80);
71	make_cd(6, base + 0x80);
72
73	pp[0] = clk_register_divider(NULL, "cpu_clk", "pll0", 0,
74			base + CPUCLK_DIV, 8, 8, CLK_DIVIDER_ONE_BASED, NULL);
75	pp[1] = clk_register_fixed_factor(NULL, "sys_clk", "pll1", 0, 1, 4);
76	pp[2] = clk_register_fixed_factor(NULL,  "usb_clk", "cd2", 0, 1, 2);
77	pp[3] = clk_register_fixed_factor(NULL, "sdio_clk", "cd6", 0, 1, 2);
78
79	if (IS_ERR(pp[0]) || IS_ERR(pp[1]) || IS_ERR(pp[2]) || IS_ERR(pp[3]))
80		panic("%pOFn: clk registration failed\n", np);
81
82	if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data))
83		panic("%pOFn: clk provider registration failed\n", np);
84}
85CLK_OF_DECLARE(tango4_clkgen, "sigma,tango4-clkgen", tango4_clkgen_setup);
86