1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * AXI clkgen driver
4 *
5 * Copyright 2012-2013 Analog Devices Inc.
6 *  Author: Lars-Peter Clausen <lars@metafoo.de>
7 */
8
9#include <linux/platform_device.h>
10#include <linux/clk-provider.h>
11#include <linux/slab.h>
12#include <linux/io.h>
13#include <linux/of.h>
14#include <linux/module.h>
15#include <linux/err.h>
16
17#define AXI_CLKGEN_V2_REG_RESET		0x40
18#define AXI_CLKGEN_V2_REG_CLKSEL	0x44
19#define AXI_CLKGEN_V2_REG_DRP_CNTRL	0x70
20#define AXI_CLKGEN_V2_REG_DRP_STATUS	0x74
21
22#define AXI_CLKGEN_V2_RESET_MMCM_ENABLE	BIT(1)
23#define AXI_CLKGEN_V2_RESET_ENABLE	BIT(0)
24
25#define AXI_CLKGEN_V2_DRP_CNTRL_SEL	BIT(29)
26#define AXI_CLKGEN_V2_DRP_CNTRL_READ	BIT(28)
27
28#define AXI_CLKGEN_V2_DRP_STATUS_BUSY	BIT(16)
29
30#define MMCM_REG_CLKOUT5_2	0x07
31#define MMCM_REG_CLKOUT0_1	0x08
32#define MMCM_REG_CLKOUT0_2	0x09
33#define MMCM_REG_CLKOUT6_2	0x13
34#define MMCM_REG_CLK_FB1	0x14
35#define MMCM_REG_CLK_FB2	0x15
36#define MMCM_REG_CLK_DIV	0x16
37#define MMCM_REG_LOCK1		0x18
38#define MMCM_REG_LOCK2		0x19
39#define MMCM_REG_LOCK3		0x1a
40#define MMCM_REG_POWER		0x28
41#define MMCM_REG_FILTER1	0x4e
42#define MMCM_REG_FILTER2	0x4f
43
44#define MMCM_CLKOUT_NOCOUNT	BIT(6)
45
46#define MMCM_CLK_DIV_DIVIDE	BIT(11)
47#define MMCM_CLK_DIV_NOCOUNT	BIT(12)
48
49struct axi_clkgen {
50	void __iomem *base;
51	struct clk_hw clk_hw;
52};
53
54static uint32_t axi_clkgen_lookup_filter(unsigned int m)
55{
56	switch (m) {
57	case 0:
58		return 0x01001990;
59	case 1:
60		return 0x01001190;
61	case 2:
62		return 0x01009890;
63	case 3:
64		return 0x01001890;
65	case 4:
66		return 0x01008890;
67	case 5 ... 8:
68		return 0x01009090;
69	case 9 ... 11:
70		return 0x01000890;
71	case 12:
72		return 0x08009090;
73	case 13 ... 22:
74		return 0x01001090;
75	case 23 ... 36:
76		return 0x01008090;
77	case 37 ... 46:
78		return 0x08001090;
79	default:
80		return 0x08008090;
81	}
82}
83
84static const uint32_t axi_clkgen_lock_table[] = {
85	0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,
86	0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,
87	0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
88	0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271,
89	0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4,
90	0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190,
91	0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e,
92	0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c,
93	0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,
94};
95
96static uint32_t axi_clkgen_lookup_lock(unsigned int m)
97{
98	if (m < ARRAY_SIZE(axi_clkgen_lock_table))
99		return axi_clkgen_lock_table[m];
100	return 0x1f1f00fa;
101}
102
103static const unsigned int fpfd_min = 10000;
104static const unsigned int fpfd_max = 300000;
105static const unsigned int fvco_min = 600000;
106static const unsigned int fvco_max = 1200000;
107
108static void axi_clkgen_calc_params(unsigned long fin, unsigned long fout,
109	unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout)
110{
111	unsigned long d, d_min, d_max, _d_min, _d_max;
112	unsigned long m, m_min, m_max;
113	unsigned long f, dout, best_f, fvco;
114	unsigned long fract_shift = 0;
115	unsigned long fvco_min_fract, fvco_max_fract;
116
117	fin /= 1000;
118	fout /= 1000;
119
120	best_f = ULONG_MAX;
121	*best_d = 0;
122	*best_m = 0;
123	*best_dout = 0;
124
125	d_min = max_t(unsigned long, DIV_ROUND_UP(fin, fpfd_max), 1);
126	d_max = min_t(unsigned long, fin / fpfd_min, 80);
127
128again:
129	fvco_min_fract = fvco_min << fract_shift;
130	fvco_max_fract = fvco_max << fract_shift;
131
132	m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min_fract, fin) * d_min, 1);
133	m_max = min_t(unsigned long, fvco_max_fract * d_max / fin, 64 << fract_shift);
134
135	for (m = m_min; m <= m_max; m++) {
136		_d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max_fract));
137		_d_max = min(d_max, fin * m / fvco_min_fract);
138
139		for (d = _d_min; d <= _d_max; d++) {
140			fvco = fin * m / d;
141
142			dout = DIV_ROUND_CLOSEST(fvco, fout);
143			dout = clamp_t(unsigned long, dout, 1, 128 << fract_shift);
144			f = fvco / dout;
145			if (abs(f - fout) < abs(best_f - fout)) {
146				best_f = f;
147				*best_d = d;
148				*best_m = m << (3 - fract_shift);
149				*best_dout = dout << (3 - fract_shift);
150				if (best_f == fout)
151					return;
152			}
153		}
154	}
155
156	/* Lets see if we find a better setting in fractional mode */
157	if (fract_shift == 0) {
158		fract_shift = 3;
159		goto again;
160	}
161}
162
163struct axi_clkgen_div_params {
164	unsigned int low;
165	unsigned int high;
166	unsigned int edge;
167	unsigned int nocount;
168	unsigned int frac_en;
169	unsigned int frac;
170	unsigned int frac_wf_f;
171	unsigned int frac_wf_r;
172	unsigned int frac_phase;
173};
174
175static void axi_clkgen_calc_clk_params(unsigned int divider,
176	unsigned int frac_divider, struct axi_clkgen_div_params *params)
177{
178
179	memset(params, 0x0, sizeof(*params));
180
181	if (divider == 1) {
182		params->nocount = 1;
183		return;
184	}
185
186	if (frac_divider == 0) {
187		params->high = divider / 2;
188		params->edge = divider % 2;
189		params->low = divider - params->high;
190	} else {
191		params->frac_en = 1;
192		params->frac = frac_divider;
193
194		params->high = divider / 2;
195		params->edge = divider % 2;
196		params->low = params->high;
197
198		if (params->edge == 0) {
199			params->high--;
200			params->frac_wf_r = 1;
201		}
202
203		if (params->edge == 0 || frac_divider == 1)
204			params->low--;
205		if (((params->edge == 0) ^ (frac_divider == 1)) ||
206			(divider == 2 && frac_divider == 1))
207			params->frac_wf_f = 1;
208
209		params->frac_phase = params->edge * 4 + frac_divider / 2;
210	}
211}
212
213static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
214	unsigned int reg, unsigned int val)
215{
216	writel(val, axi_clkgen->base + reg);
217}
218
219static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
220	unsigned int reg, unsigned int *val)
221{
222	*val = readl(axi_clkgen->base + reg);
223}
224
225static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen)
226{
227	unsigned int timeout = 10000;
228	unsigned int val;
229
230	do {
231		axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val);
232	} while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout);
233
234	if (val & AXI_CLKGEN_V2_DRP_STATUS_BUSY)
235		return -EIO;
236
237	return val & 0xffff;
238}
239
240static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen,
241	unsigned int reg, unsigned int *val)
242{
243	unsigned int reg_val;
244	int ret;
245
246	ret = axi_clkgen_wait_non_busy(axi_clkgen);
247	if (ret < 0)
248		return ret;
249
250	reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL | AXI_CLKGEN_V2_DRP_CNTRL_READ;
251	reg_val |= (reg << 16);
252
253	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
254
255	ret = axi_clkgen_wait_non_busy(axi_clkgen);
256	if (ret < 0)
257		return ret;
258
259	*val = ret;
260
261	return 0;
262}
263
264static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen,
265	unsigned int reg, unsigned int val, unsigned int mask)
266{
267	unsigned int reg_val = 0;
268	int ret;
269
270	ret = axi_clkgen_wait_non_busy(axi_clkgen);
271	if (ret < 0)
272		return ret;
273
274	if (mask != 0xffff) {
275		axi_clkgen_mmcm_read(axi_clkgen, reg, &reg_val);
276		reg_val &= ~mask;
277	}
278
279	reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask);
280
281	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
282
283	return 0;
284}
285
286static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen,
287	bool enable)
288{
289	unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE;
290
291	if (enable)
292		val |= AXI_CLKGEN_V2_RESET_MMCM_ENABLE;
293
294	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_RESET, val);
295}
296
297static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw)
298{
299	return container_of(clk_hw, struct axi_clkgen, clk_hw);
300}
301
302static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen,
303	unsigned int reg1, unsigned int reg2, unsigned int reg3,
304	struct axi_clkgen_div_params *params)
305{
306	axi_clkgen_mmcm_write(axi_clkgen, reg1,
307		(params->high << 6) | params->low, 0xefff);
308	axi_clkgen_mmcm_write(axi_clkgen, reg2,
309		(params->frac << 12) | (params->frac_en << 11) |
310		(params->frac_wf_r << 10) | (params->edge << 7) |
311		(params->nocount << 6), 0x7fff);
312	if (reg3 != 0) {
313		axi_clkgen_mmcm_write(axi_clkgen, reg3,
314			(params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00);
315	}
316}
317
318static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
319	unsigned long rate, unsigned long parent_rate)
320{
321	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
322	unsigned int d, m, dout;
323	struct axi_clkgen_div_params params;
324	uint32_t power = 0;
325	uint32_t filter;
326	uint32_t lock;
327
328	if (parent_rate == 0 || rate == 0)
329		return -EINVAL;
330
331	axi_clkgen_calc_params(parent_rate, rate, &d, &m, &dout);
332
333	if (d == 0 || dout == 0 || m == 0)
334		return -EINVAL;
335
336	if ((dout & 0x7) != 0 || (m & 0x7) != 0)
337		power |= 0x9800;
338
339	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_POWER, power, 0x9800);
340
341	filter = axi_clkgen_lookup_filter(m - 1);
342	lock = axi_clkgen_lookup_lock(m - 1);
343
344	axi_clkgen_calc_clk_params(dout >> 3, dout & 0x7, &params);
345	axi_clkgen_set_div(axi_clkgen,  MMCM_REG_CLKOUT0_1, MMCM_REG_CLKOUT0_2,
346		MMCM_REG_CLKOUT5_2, &params);
347
348	axi_clkgen_calc_clk_params(d, 0, &params);
349	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV,
350		(params.edge << 13) | (params.nocount << 12) |
351		(params.high << 6) | params.low, 0x3fff);
352
353	axi_clkgen_calc_clk_params(m >> 3, m & 0x7, &params);
354	axi_clkgen_set_div(axi_clkgen,  MMCM_REG_CLK_FB1, MMCM_REG_CLK_FB2,
355		MMCM_REG_CLKOUT6_2, &params);
356
357	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff);
358	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2,
359		(((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff);
360	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3,
361		(((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff);
362	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900);
363	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900);
364
365	return 0;
366}
367
368static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
369	unsigned long *parent_rate)
370{
371	unsigned int d, m, dout;
372	unsigned long long tmp;
373
374	axi_clkgen_calc_params(*parent_rate, rate, &d, &m, &dout);
375
376	if (d == 0 || dout == 0 || m == 0)
377		return -EINVAL;
378
379	tmp = (unsigned long long)*parent_rate * m;
380	tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
381
382	return min_t(unsigned long long, tmp, LONG_MAX);
383}
384
385static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen,
386	unsigned int reg1, unsigned int reg2)
387{
388	unsigned int val1, val2;
389	unsigned int div;
390
391	axi_clkgen_mmcm_read(axi_clkgen, reg2, &val2);
392	if (val2 & MMCM_CLKOUT_NOCOUNT)
393		return 8;
394
395	axi_clkgen_mmcm_read(axi_clkgen, reg1, &val1);
396
397	div = (val1 & 0x3f) + ((val1 >> 6) & 0x3f);
398	div <<= 3;
399
400	if (val2 & MMCM_CLK_DIV_DIVIDE) {
401		if ((val2 & BIT(7)) && (val2 & 0x7000) != 0x1000)
402			div += 8;
403		else
404			div += 16;
405
406		div += (val2 >> 12) & 0x7;
407	}
408
409	return div;
410}
411
412static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
413	unsigned long parent_rate)
414{
415	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
416	unsigned int d, m, dout;
417	unsigned long long tmp;
418	unsigned int val;
419
420	dout = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLKOUT0_1,
421		MMCM_REG_CLKOUT0_2);
422	m = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLK_FB1,
423		MMCM_REG_CLK_FB2);
424
425	axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &val);
426	if (val & MMCM_CLK_DIV_NOCOUNT)
427		d = 1;
428	else
429		d = (val & 0x3f) + ((val >> 6) & 0x3f);
430
431	if (d == 0 || dout == 0)
432		return 0;
433
434	tmp = (unsigned long long)parent_rate * m;
435	tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
436
437	return min_t(unsigned long long, tmp, ULONG_MAX);
438}
439
440static int axi_clkgen_enable(struct clk_hw *clk_hw)
441{
442	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
443
444	axi_clkgen_mmcm_enable(axi_clkgen, true);
445
446	return 0;
447}
448
449static void axi_clkgen_disable(struct clk_hw *clk_hw)
450{
451	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
452
453	axi_clkgen_mmcm_enable(axi_clkgen, false);
454}
455
456static int axi_clkgen_set_parent(struct clk_hw *clk_hw, u8 index)
457{
458	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
459
460	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, index);
461
462	return 0;
463}
464
465static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw)
466{
467	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
468	unsigned int parent;
469
470	axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, &parent);
471
472	return parent;
473}
474
475static const struct clk_ops axi_clkgen_ops = {
476	.recalc_rate = axi_clkgen_recalc_rate,
477	.round_rate = axi_clkgen_round_rate,
478	.set_rate = axi_clkgen_set_rate,
479	.enable = axi_clkgen_enable,
480	.disable = axi_clkgen_disable,
481	.set_parent = axi_clkgen_set_parent,
482	.get_parent = axi_clkgen_get_parent,
483};
484
485static const struct of_device_id axi_clkgen_ids[] = {
486	{
487		.compatible = "adi,axi-clkgen-2.00.a",
488	},
489	{ },
490};
491MODULE_DEVICE_TABLE(of, axi_clkgen_ids);
492
493static int axi_clkgen_probe(struct platform_device *pdev)
494{
495	const struct of_device_id *id;
496	struct axi_clkgen *axi_clkgen;
497	struct clk_init_data init;
498	const char *parent_names[2];
499	const char *clk_name;
500	struct resource *mem;
501	unsigned int i;
502	int ret;
503
504	if (!pdev->dev.of_node)
505		return -ENODEV;
506
507	id = of_match_node(axi_clkgen_ids, pdev->dev.of_node);
508	if (!id)
509		return -ENODEV;
510
511	axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);
512	if (!axi_clkgen)
513		return -ENOMEM;
514
515	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
516	axi_clkgen->base = devm_ioremap_resource(&pdev->dev, mem);
517	if (IS_ERR(axi_clkgen->base))
518		return PTR_ERR(axi_clkgen->base);
519
520	init.num_parents = of_clk_get_parent_count(pdev->dev.of_node);
521	if (init.num_parents < 1 || init.num_parents > 2)
522		return -EINVAL;
523
524	for (i = 0; i < init.num_parents; i++) {
525		parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i);
526		if (!parent_names[i])
527			return -EINVAL;
528	}
529
530	clk_name = pdev->dev.of_node->name;
531	of_property_read_string(pdev->dev.of_node, "clock-output-names",
532		&clk_name);
533
534	init.name = clk_name;
535	init.ops = &axi_clkgen_ops;
536	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
537	init.parent_names = parent_names;
538
539	axi_clkgen_mmcm_enable(axi_clkgen, false);
540
541	axi_clkgen->clk_hw.init = &init;
542	ret = devm_clk_hw_register(&pdev->dev, &axi_clkgen->clk_hw);
543	if (ret)
544		return ret;
545
546	return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_simple_get,
547				      &axi_clkgen->clk_hw);
548}
549
550static int axi_clkgen_remove(struct platform_device *pdev)
551{
552	of_clk_del_provider(pdev->dev.of_node);
553
554	return 0;
555}
556
557static struct platform_driver axi_clkgen_driver = {
558	.driver = {
559		.name = "adi-axi-clkgen",
560		.of_match_table = axi_clkgen_ids,
561	},
562	.probe = axi_clkgen_probe,
563	.remove = axi_clkgen_remove,
564};
565module_platform_driver(axi_clkgen_driver);
566
567MODULE_LICENSE("GPL v2");
568MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
569MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");
570