18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0-only 28c2ecf20Sopenharmony_ciconfig CLK_BAIKAL_T1 38c2ecf20Sopenharmony_ci bool "Baikal-T1 Clocks Control Unit interface" 48c2ecf20Sopenharmony_ci depends on (MIPS_BAIKAL_T1 && OF) || COMPILE_TEST 58c2ecf20Sopenharmony_ci default MIPS_BAIKAL_T1 68c2ecf20Sopenharmony_ci help 78c2ecf20Sopenharmony_ci Clocks Control Unit is the core of Baikal-T1 SoC System Controller 88c2ecf20Sopenharmony_ci responsible for the chip subsystems clocking and resetting. It 98c2ecf20Sopenharmony_ci consists of multiple global clock domains, which can be reset by 108c2ecf20Sopenharmony_ci means of the CCU control registers. These domains and devices placed 118c2ecf20Sopenharmony_ci in them are fed with clocks generated by a hierarchy of PLLs, 128c2ecf20Sopenharmony_ci configurable and fixed clock dividers. Enable this option to be able 138c2ecf20Sopenharmony_ci to select Baikal-T1 CCU PLLs and Dividers drivers. 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ciif CLK_BAIKAL_T1 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ciconfig CLK_BT1_CCU_PLL 188c2ecf20Sopenharmony_ci bool "Baikal-T1 CCU PLLs support" 198c2ecf20Sopenharmony_ci select MFD_SYSCON 208c2ecf20Sopenharmony_ci default MIPS_BAIKAL_T1 218c2ecf20Sopenharmony_ci help 228c2ecf20Sopenharmony_ci Enable this to support the PLLs embedded into the Baikal-T1 SoC 238c2ecf20Sopenharmony_ci System Controller. These are five PLLs placed at the root of the 248c2ecf20Sopenharmony_ci clocks hierarchy, right after an external reference oscillator 258c2ecf20Sopenharmony_ci (normally of 25MHz). They are used to generate high frequency 268c2ecf20Sopenharmony_ci signals, which are either directly wired to the consumers (like 278c2ecf20Sopenharmony_ci CPUs, DDR, etc.) or passed over the clock dividers to be only 288c2ecf20Sopenharmony_ci then used as an individual reference clock of a target device. 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_ciconfig CLK_BT1_CCU_DIV 318c2ecf20Sopenharmony_ci bool "Baikal-T1 CCU Dividers support" 328c2ecf20Sopenharmony_ci select RESET_CONTROLLER 338c2ecf20Sopenharmony_ci select MFD_SYSCON 348c2ecf20Sopenharmony_ci default MIPS_BAIKAL_T1 358c2ecf20Sopenharmony_ci help 368c2ecf20Sopenharmony_ci Enable this to support the CCU dividers used to distribute clocks 378c2ecf20Sopenharmony_ci between AXI-bus and system devices coming from CCU PLLs of Baikal-T1 388c2ecf20Sopenharmony_ci SoC. CCU dividers can be either configurable or with fixed divider, 398c2ecf20Sopenharmony_ci either gateable or ungateable. Some of the CCU dividers can be as well 408c2ecf20Sopenharmony_ci used to reset the domains they're supplying clock to. 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ciendif 43