1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * drivers/clk/at91/pmc.h 4 * 5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 6 */ 7 8#ifndef __PMC_H_ 9#define __PMC_H_ 10 11#include <linux/io.h> 12#include <linux/irqdomain.h> 13#include <linux/regmap.h> 14#include <linux/spinlock.h> 15 16extern spinlock_t pmc_pcr_lock; 17 18struct pmc_data { 19 unsigned int ncore; 20 struct clk_hw **chws; 21 unsigned int nsystem; 22 struct clk_hw **shws; 23 unsigned int nperiph; 24 struct clk_hw **phws; 25 unsigned int ngck; 26 struct clk_hw **ghws; 27 unsigned int npck; 28 struct clk_hw **pchws; 29 30 struct clk_hw *hwtable[]; 31}; 32 33struct clk_range { 34 unsigned long min; 35 unsigned long max; 36}; 37 38#define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,} 39 40struct clk_master_layout { 41 u32 offset; 42 u32 mask; 43 u8 pres_shift; 44}; 45 46extern const struct clk_master_layout at91rm9200_master_layout; 47extern const struct clk_master_layout at91sam9x5_master_layout; 48 49struct clk_master_characteristics { 50 struct clk_range output; 51 u32 divisors[4]; 52 u8 have_div3_pres; 53}; 54 55struct clk_pll_layout { 56 u32 pllr_mask; 57 u32 mul_mask; 58 u32 frac_mask; 59 u32 div_mask; 60 u32 endiv_mask; 61 u8 mul_shift; 62 u8 frac_shift; 63 u8 div_shift; 64 u8 endiv_shift; 65}; 66 67extern const struct clk_pll_layout at91rm9200_pll_layout; 68extern const struct clk_pll_layout at91sam9g45_pll_layout; 69extern const struct clk_pll_layout at91sam9g20_pllb_layout; 70extern const struct clk_pll_layout sama5d3_pll_layout; 71 72struct clk_pll_characteristics { 73 struct clk_range input; 74 int num_output; 75 const struct clk_range *output; 76 u16 *icpll; 77 u8 *out; 78 u8 upll : 1; 79}; 80 81struct clk_programmable_layout { 82 u8 pres_mask; 83 u8 pres_shift; 84 u8 css_mask; 85 u8 have_slck_mck; 86 u8 is_pres_direct; 87}; 88 89extern const struct clk_programmable_layout at91rm9200_programmable_layout; 90extern const struct clk_programmable_layout at91sam9g45_programmable_layout; 91extern const struct clk_programmable_layout at91sam9x5_programmable_layout; 92 93struct clk_pcr_layout { 94 u32 offset; 95 u32 cmd; 96 u32 div_mask; 97 u32 gckcss_mask; 98 u32 pid_mask; 99}; 100 101#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) 102#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) 103 104#define ndck(a, s) (a[s - 1].id + 1) 105#define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1) 106struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem, 107 unsigned int nperiph, unsigned int ngck, 108 unsigned int npck); 109 110int of_at91_get_clk_range(struct device_node *np, const char *propname, 111 struct clk_range *range); 112 113struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data); 114 115struct clk_hw * __init 116at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name, 117 const char *parent_name); 118 119struct clk_hw * __init 120at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name, 121 const char *parent_name); 122 123struct clk_hw * __init 124at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name, 125 const char *parent_name); 126 127struct clk_hw * __init 128at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, 129 const struct clk_pcr_layout *layout, 130 const char *name, const char **parent_names, 131 u32 *mux_table, u8 num_parents, u8 id, 132 const struct clk_range *range, int chg_pid); 133 134struct clk_hw * __init 135at91_clk_register_h32mx(struct regmap *regmap, const char *name, 136 const char *parent_name); 137 138struct clk_hw * __init 139at91_clk_i2s_mux_register(struct regmap *regmap, const char *name, 140 const char * const *parent_names, 141 unsigned int num_parents, u8 bus_id); 142 143struct clk_hw * __init 144at91_clk_register_main_rc_osc(struct regmap *regmap, const char *name, 145 u32 frequency, u32 accuracy); 146struct clk_hw * __init 147at91_clk_register_main_osc(struct regmap *regmap, const char *name, 148 const char *parent_name, bool bypass); 149struct clk_hw * __init 150at91_clk_register_rm9200_main(struct regmap *regmap, 151 const char *name, 152 const char *parent_name); 153struct clk_hw * __init 154at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name, 155 const char **parent_names, int num_parents); 156 157struct clk_hw * __init 158at91_clk_register_master(struct regmap *regmap, const char *name, 159 int num_parents, const char **parent_names, 160 const struct clk_master_layout *layout, 161 const struct clk_master_characteristics *characteristics); 162 163struct clk_hw * __init 164at91_clk_sama7g5_register_master(struct regmap *regmap, 165 const char *name, int num_parents, 166 const char **parent_names, u32 *mux_table, 167 spinlock_t *lock, u8 id, bool critical, 168 int chg_pid); 169 170struct clk_hw * __init 171at91_clk_register_peripheral(struct regmap *regmap, const char *name, 172 const char *parent_name, u32 id); 173struct clk_hw * __init 174at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock, 175 const struct clk_pcr_layout *layout, 176 const char *name, const char *parent_name, 177 u32 id, const struct clk_range *range, 178 int chg_pid); 179 180struct clk_hw * __init 181at91_clk_register_pll(struct regmap *regmap, const char *name, 182 const char *parent_name, u8 id, 183 const struct clk_pll_layout *layout, 184 const struct clk_pll_characteristics *characteristics); 185struct clk_hw * __init 186at91_clk_register_plldiv(struct regmap *regmap, const char *name, 187 const char *parent_name); 188 189struct clk_hw * __init 190sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, 191 const char *name, const char *parent_name, u8 id, 192 const struct clk_pll_characteristics *characteristics, 193 const struct clk_pll_layout *layout, bool critical); 194 195struct clk_hw * __init 196sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, 197 const char *name, const char *parent_name, 198 struct clk_hw *parent_hw, u8 id, 199 const struct clk_pll_characteristics *characteristics, 200 const struct clk_pll_layout *layout, bool critical); 201 202struct clk_hw * __init 203at91_clk_register_programmable(struct regmap *regmap, const char *name, 204 const char **parent_names, u8 num_parents, u8 id, 205 const struct clk_programmable_layout *layout, 206 u32 *mux_table); 207 208struct clk_hw * __init 209at91_clk_register_sam9260_slow(struct regmap *regmap, 210 const char *name, 211 const char **parent_names, 212 int num_parents); 213 214struct clk_hw * __init 215at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name, 216 const char **parent_names, u8 num_parents); 217 218struct clk_hw * __init 219at91_clk_register_system(struct regmap *regmap, const char *name, 220 const char *parent_name, u8 id); 221 222struct clk_hw * __init 223at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, 224 const char **parent_names, u8 num_parents); 225struct clk_hw * __init 226at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name, 227 const char *parent_name); 228struct clk_hw * __init 229sam9x60_clk_register_usb(struct regmap *regmap, const char *name, 230 const char **parent_names, u8 num_parents); 231struct clk_hw * __init 232at91rm9200_clk_register_usb(struct regmap *regmap, const char *name, 233 const char *parent_name, const u32 *divisors); 234 235struct clk_hw * __init 236at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr, 237 const char *name, const char *parent_name); 238 239struct clk_hw * __init 240at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name, 241 const char *parent_name); 242 243#ifdef CONFIG_PM 244void pmc_register_id(u8 id); 245void pmc_register_pck(u8 pck); 246#else 247static inline void pmc_register_id(u8 id) {} 248static inline void pmc_register_pck(u8 pck) {} 249#endif 250 251#endif /* __PMC_H_ */ 252