1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 4 */ 5 6#include <linux/clk-provider.h> 7#include <linux/clkdev.h> 8#include <linux/clk/at91_pmc.h> 9#include <linux/of.h> 10#include <linux/mfd/syscon.h> 11#include <linux/platform_device.h> 12#include <linux/regmap.h> 13#include <linux/syscore_ops.h> 14 15#include <asm/proc-fns.h> 16 17#include <dt-bindings/clock/at91.h> 18 19#include "pmc.h" 20 21#define PMC_MAX_IDS 128 22#define PMC_MAX_PCKS 8 23 24int of_at91_get_clk_range(struct device_node *np, const char *propname, 25 struct clk_range *range) 26{ 27 u32 min, max; 28 int ret; 29 30 ret = of_property_read_u32_index(np, propname, 0, &min); 31 if (ret) 32 return ret; 33 34 ret = of_property_read_u32_index(np, propname, 1, &max); 35 if (ret) 36 return ret; 37 38 if (range) { 39 range->min = min; 40 range->max = max; 41 } 42 43 return 0; 44} 45EXPORT_SYMBOL_GPL(of_at91_get_clk_range); 46 47struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data) 48{ 49 unsigned int type = clkspec->args[0]; 50 unsigned int idx = clkspec->args[1]; 51 struct pmc_data *pmc_data = data; 52 53 switch (type) { 54 case PMC_TYPE_CORE: 55 if (idx < pmc_data->ncore) 56 return pmc_data->chws[idx]; 57 break; 58 case PMC_TYPE_SYSTEM: 59 if (idx < pmc_data->nsystem) 60 return pmc_data->shws[idx]; 61 break; 62 case PMC_TYPE_PERIPHERAL: 63 if (idx < pmc_data->nperiph) 64 return pmc_data->phws[idx]; 65 break; 66 case PMC_TYPE_GCK: 67 if (idx < pmc_data->ngck) 68 return pmc_data->ghws[idx]; 69 break; 70 case PMC_TYPE_PROGRAMMABLE: 71 if (idx < pmc_data->npck) 72 return pmc_data->pchws[idx]; 73 break; 74 default: 75 break; 76 } 77 78 pr_err("%s: invalid type (%u) or index (%u)\n", __func__, type, idx); 79 80 return ERR_PTR(-EINVAL); 81} 82 83struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem, 84 unsigned int nperiph, unsigned int ngck, 85 unsigned int npck) 86{ 87 unsigned int num_clks = ncore + nsystem + nperiph + ngck + npck; 88 struct pmc_data *pmc_data; 89 90 pmc_data = kzalloc(struct_size(pmc_data, hwtable, num_clks), 91 GFP_KERNEL); 92 if (!pmc_data) 93 return NULL; 94 95 pmc_data->ncore = ncore; 96 pmc_data->chws = pmc_data->hwtable; 97 98 pmc_data->nsystem = nsystem; 99 pmc_data->shws = pmc_data->chws + ncore; 100 101 pmc_data->nperiph = nperiph; 102 pmc_data->phws = pmc_data->shws + nsystem; 103 104 pmc_data->ngck = ngck; 105 pmc_data->ghws = pmc_data->phws + nperiph; 106 107 pmc_data->npck = npck; 108 pmc_data->pchws = pmc_data->ghws + ngck; 109 110 return pmc_data; 111} 112 113#ifdef CONFIG_PM 114static struct regmap *pmcreg; 115 116static u8 registered_ids[PMC_MAX_IDS]; 117static u8 registered_pcks[PMC_MAX_PCKS]; 118 119static struct 120{ 121 u32 scsr; 122 u32 pcsr0; 123 u32 uckr; 124 u32 mor; 125 u32 mcfr; 126 u32 pllar; 127 u32 mckr; 128 u32 usb; 129 u32 imr; 130 u32 pcsr1; 131 u32 pcr[PMC_MAX_IDS]; 132 u32 audio_pll0; 133 u32 audio_pll1; 134 u32 pckr[PMC_MAX_PCKS]; 135} pmc_cache; 136 137/* 138 * As Peripheral ID 0 is invalid on AT91 chips, the identifier is stored 139 * without alteration in the table, and 0 is for unused clocks. 140 */ 141void pmc_register_id(u8 id) 142{ 143 int i; 144 145 for (i = 0; i < PMC_MAX_IDS; i++) { 146 if (registered_ids[i] == 0) { 147 registered_ids[i] = id; 148 break; 149 } 150 if (registered_ids[i] == id) 151 break; 152 } 153} 154 155/* 156 * As Programmable Clock 0 is valid on AT91 chips, there is an offset 157 * of 1 between the stored value and the real clock ID. 158 */ 159void pmc_register_pck(u8 pck) 160{ 161 int i; 162 163 for (i = 0; i < PMC_MAX_PCKS; i++) { 164 if (registered_pcks[i] == 0) { 165 registered_pcks[i] = pck + 1; 166 break; 167 } 168 if (registered_pcks[i] == (pck + 1)) 169 break; 170 } 171} 172 173static int pmc_suspend(void) 174{ 175 int i; 176 u8 num; 177 178 regmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr); 179 regmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0); 180 regmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr); 181 regmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor); 182 regmap_read(pmcreg, AT91_CKGR_MCFR, &pmc_cache.mcfr); 183 regmap_read(pmcreg, AT91_CKGR_PLLAR, &pmc_cache.pllar); 184 regmap_read(pmcreg, AT91_PMC_MCKR, &pmc_cache.mckr); 185 regmap_read(pmcreg, AT91_PMC_USB, &pmc_cache.usb); 186 regmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.imr); 187 regmap_read(pmcreg, AT91_PMC_PCSR1, &pmc_cache.pcsr1); 188 189 for (i = 0; registered_ids[i]; i++) { 190 regmap_write(pmcreg, AT91_PMC_PCR, 191 (registered_ids[i] & AT91_PMC_PCR_PID_MASK)); 192 regmap_read(pmcreg, AT91_PMC_PCR, 193 &pmc_cache.pcr[registered_ids[i]]); 194 } 195 for (i = 0; registered_pcks[i]; i++) { 196 num = registered_pcks[i] - 1; 197 regmap_read(pmcreg, AT91_PMC_PCKR(num), &pmc_cache.pckr[num]); 198 } 199 200 return 0; 201} 202 203static bool pmc_ready(unsigned int mask) 204{ 205 unsigned int status; 206 207 regmap_read(pmcreg, AT91_PMC_SR, &status); 208 209 return ((status & mask) == mask) ? 1 : 0; 210} 211 212static void pmc_resume(void) 213{ 214 int i; 215 u8 num; 216 u32 tmp; 217 u32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA; 218 219 regmap_read(pmcreg, AT91_PMC_MCKR, &tmp); 220 if (pmc_cache.mckr != tmp) 221 pr_warn("MCKR was not configured properly by the firmware\n"); 222 regmap_read(pmcreg, AT91_CKGR_PLLAR, &tmp); 223 if (pmc_cache.pllar != tmp) 224 pr_warn("PLLAR was not configured properly by the firmware\n"); 225 226 regmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr); 227 regmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0); 228 regmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr); 229 regmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor); 230 regmap_write(pmcreg, AT91_CKGR_MCFR, pmc_cache.mcfr); 231 regmap_write(pmcreg, AT91_PMC_USB, pmc_cache.usb); 232 regmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.imr); 233 regmap_write(pmcreg, AT91_PMC_PCER1, pmc_cache.pcsr1); 234 235 for (i = 0; registered_ids[i]; i++) { 236 regmap_write(pmcreg, AT91_PMC_PCR, 237 pmc_cache.pcr[registered_ids[i]] | 238 AT91_PMC_PCR_CMD); 239 } 240 for (i = 0; registered_pcks[i]; i++) { 241 num = registered_pcks[i] - 1; 242 regmap_write(pmcreg, AT91_PMC_PCKR(num), pmc_cache.pckr[num]); 243 } 244 245 if (pmc_cache.uckr & AT91_PMC_UPLLEN) 246 mask |= AT91_PMC_LOCKU; 247 248 while (!pmc_ready(mask)) 249 cpu_relax(); 250} 251 252static struct syscore_ops pmc_syscore_ops = { 253 .suspend = pmc_suspend, 254 .resume = pmc_resume, 255}; 256 257static const struct of_device_id sama5d2_pmc_dt_ids[] = { 258 { .compatible = "atmel,sama5d2-pmc" }, 259 { /* sentinel */ } 260}; 261 262static int __init pmc_register_ops(void) 263{ 264 struct device_node *np; 265 266 np = of_find_matching_node(NULL, sama5d2_pmc_dt_ids); 267 if (!np) 268 return -ENODEV; 269 270 if (!of_device_is_available(np)) { 271 of_node_put(np); 272 return -ENODEV; 273 } 274 275 pmcreg = device_node_to_regmap(np); 276 of_node_put(np); 277 if (IS_ERR(pmcreg)) 278 return PTR_ERR(pmcreg); 279 280 register_syscore_ops(&pmc_syscore_ops); 281 282 return 0; 283} 284/* This has to happen before arch_initcall because of the tcb_clksrc driver */ 285postcore_initcall(pmc_register_ops); 286#endif 287