1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *  Copyright (C) 2015 Atmel Corporation,
4 *                     Nicolas Ferre <nicolas.ferre@atmel.com>
5 *
6 * Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON.
7 */
8
9#include <linux/bitfield.h>
10#include <linux/clk-provider.h>
11#include <linux/clkdev.h>
12#include <linux/clk/at91_pmc.h>
13#include <linux/of.h>
14#include <linux/mfd/syscon.h>
15#include <linux/regmap.h>
16
17#include "pmc.h"
18
19#define GENERATED_MAX_DIV	255
20
21struct clk_generated {
22	struct clk_hw hw;
23	struct regmap *regmap;
24	struct clk_range range;
25	spinlock_t *lock;
26	u32 *mux_table;
27	u32 id;
28	u32 gckdiv;
29	const struct clk_pcr_layout *layout;
30	u8 parent_id;
31	int chg_pid;
32};
33
34#define to_clk_generated(hw) \
35	container_of(hw, struct clk_generated, hw)
36
37static int clk_generated_enable(struct clk_hw *hw)
38{
39	struct clk_generated *gck = to_clk_generated(hw);
40	unsigned long flags;
41
42	pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n",
43		 __func__, gck->gckdiv, gck->parent_id);
44
45	spin_lock_irqsave(gck->lock, flags);
46	regmap_write(gck->regmap, gck->layout->offset,
47		     (gck->id & gck->layout->pid_mask));
48	regmap_update_bits(gck->regmap, gck->layout->offset,
49			   AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask |
50			   gck->layout->cmd | AT91_PMC_PCR_GCKEN,
51			   field_prep(gck->layout->gckcss_mask, gck->parent_id) |
52			   gck->layout->cmd |
53			   FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) |
54			   AT91_PMC_PCR_GCKEN);
55	spin_unlock_irqrestore(gck->lock, flags);
56	return 0;
57}
58
59static void clk_generated_disable(struct clk_hw *hw)
60{
61	struct clk_generated *gck = to_clk_generated(hw);
62	unsigned long flags;
63
64	spin_lock_irqsave(gck->lock, flags);
65	regmap_write(gck->regmap, gck->layout->offset,
66		     (gck->id & gck->layout->pid_mask));
67	regmap_update_bits(gck->regmap, gck->layout->offset,
68			   gck->layout->cmd | AT91_PMC_PCR_GCKEN,
69			   gck->layout->cmd);
70	spin_unlock_irqrestore(gck->lock, flags);
71}
72
73static int clk_generated_is_enabled(struct clk_hw *hw)
74{
75	struct clk_generated *gck = to_clk_generated(hw);
76	unsigned long flags;
77	unsigned int status;
78
79	spin_lock_irqsave(gck->lock, flags);
80	regmap_write(gck->regmap, gck->layout->offset,
81		     (gck->id & gck->layout->pid_mask));
82	regmap_read(gck->regmap, gck->layout->offset, &status);
83	spin_unlock_irqrestore(gck->lock, flags);
84
85	return !!(status & AT91_PMC_PCR_GCKEN);
86}
87
88static unsigned long
89clk_generated_recalc_rate(struct clk_hw *hw,
90			  unsigned long parent_rate)
91{
92	struct clk_generated *gck = to_clk_generated(hw);
93
94	return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1);
95}
96
97static void clk_generated_best_diff(struct clk_rate_request *req,
98				    struct clk_hw *parent,
99				    unsigned long parent_rate, u32 div,
100				    int *best_diff, long *best_rate)
101{
102	unsigned long tmp_rate;
103	int tmp_diff;
104
105	if (!div)
106		tmp_rate = parent_rate;
107	else
108		tmp_rate = parent_rate / div;
109
110	if (tmp_rate < req->min_rate || tmp_rate > req->max_rate)
111		return;
112
113	tmp_diff = abs(req->rate - tmp_rate);
114
115	if (*best_diff < 0 || *best_diff >= tmp_diff) {
116		*best_rate = tmp_rate;
117		*best_diff = tmp_diff;
118		req->best_parent_rate = parent_rate;
119		req->best_parent_hw = parent;
120	}
121}
122
123static int clk_generated_determine_rate(struct clk_hw *hw,
124					struct clk_rate_request *req)
125{
126	struct clk_generated *gck = to_clk_generated(hw);
127	struct clk_hw *parent = NULL;
128	struct clk_rate_request req_parent = *req;
129	long best_rate = -EINVAL;
130	unsigned long min_rate, parent_rate;
131	int best_diff = -1;
132	int i;
133	u32 div;
134
135	/* do not look for a rate that is outside of our range */
136	if (gck->range.max && req->rate > gck->range.max)
137		req->rate = gck->range.max;
138	if (gck->range.min && req->rate < gck->range.min)
139		req->rate = gck->range.min;
140
141	for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
142		if (gck->chg_pid == i)
143			continue;
144
145		parent = clk_hw_get_parent_by_index(hw, i);
146		if (!parent)
147			continue;
148
149		parent_rate = clk_hw_get_rate(parent);
150		min_rate = DIV_ROUND_CLOSEST(parent_rate, GENERATED_MAX_DIV + 1);
151		if (!parent_rate ||
152		    (gck->range.max && min_rate > gck->range.max))
153			continue;
154
155		div = DIV_ROUND_CLOSEST(parent_rate, req->rate);
156		if (div > GENERATED_MAX_DIV + 1)
157			div = GENERATED_MAX_DIV + 1;
158
159		clk_generated_best_diff(req, parent, parent_rate, div,
160					&best_diff, &best_rate);
161
162		if (!best_diff)
163			break;
164	}
165
166	/*
167	 * The audio_pll rate can be modified, unlike the five others clocks
168	 * that should never be altered.
169	 * The audio_pll can technically be used by multiple consumers. However,
170	 * with the rate locking, the first consumer to enable to clock will be
171	 * the one definitely setting the rate of the clock.
172	 * Since audio IPs are most likely to request the same rate, we enforce
173	 * that the only clks able to modify gck rate are those of audio IPs.
174	 */
175
176	if (gck->chg_pid < 0)
177		goto end;
178
179	parent = clk_hw_get_parent_by_index(hw, gck->chg_pid);
180	if (!parent)
181		goto end;
182
183	for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
184		req_parent.rate = req->rate * div;
185		if (__clk_determine_rate(parent, &req_parent))
186			continue;
187		clk_generated_best_diff(req, parent, req_parent.rate, div,
188					&best_diff, &best_rate);
189
190		if (!best_diff)
191			break;
192	}
193
194end:
195	pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
196		 __func__, best_rate,
197		 __clk_get_name((req->best_parent_hw)->clk),
198		 req->best_parent_rate);
199
200	if (best_rate < 0 || (gck->range.max && best_rate > gck->range.max))
201		return -EINVAL;
202
203	req->rate = best_rate;
204	return 0;
205}
206
207/* No modification of hardware as we have the flag CLK_SET_PARENT_GATE set */
208static int clk_generated_set_parent(struct clk_hw *hw, u8 index)
209{
210	struct clk_generated *gck = to_clk_generated(hw);
211
212	if (index >= clk_hw_get_num_parents(hw))
213		return -EINVAL;
214
215	if (gck->mux_table)
216		gck->parent_id = clk_mux_index_to_val(gck->mux_table, 0, index);
217	else
218		gck->parent_id = index;
219
220	return 0;
221}
222
223static u8 clk_generated_get_parent(struct clk_hw *hw)
224{
225	struct clk_generated *gck = to_clk_generated(hw);
226
227	return gck->parent_id;
228}
229
230/* No modification of hardware as we have the flag CLK_SET_RATE_GATE set */
231static int clk_generated_set_rate(struct clk_hw *hw,
232				  unsigned long rate,
233				  unsigned long parent_rate)
234{
235	struct clk_generated *gck = to_clk_generated(hw);
236	u32 div;
237
238	if (!rate)
239		return -EINVAL;
240
241	if (gck->range.max && rate > gck->range.max)
242		return -EINVAL;
243
244	div = DIV_ROUND_CLOSEST(parent_rate, rate);
245	if (div > GENERATED_MAX_DIV + 1 || !div)
246		return -EINVAL;
247
248	gck->gckdiv = div - 1;
249	return 0;
250}
251
252static const struct clk_ops generated_ops = {
253	.enable = clk_generated_enable,
254	.disable = clk_generated_disable,
255	.is_enabled = clk_generated_is_enabled,
256	.recalc_rate = clk_generated_recalc_rate,
257	.determine_rate = clk_generated_determine_rate,
258	.get_parent = clk_generated_get_parent,
259	.set_parent = clk_generated_set_parent,
260	.set_rate = clk_generated_set_rate,
261};
262
263/**
264 * clk_generated_startup - Initialize a given clock to its default parent and
265 * divisor parameter.
266 *
267 * @gck:	Generated clock to set the startup parameters for.
268 *
269 * Take parameters from the hardware and update local clock configuration
270 * accordingly.
271 */
272static void clk_generated_startup(struct clk_generated *gck)
273{
274	u32 tmp;
275	unsigned long flags;
276
277	spin_lock_irqsave(gck->lock, flags);
278	regmap_write(gck->regmap, gck->layout->offset,
279		     (gck->id & gck->layout->pid_mask));
280	regmap_read(gck->regmap, gck->layout->offset, &tmp);
281	spin_unlock_irqrestore(gck->lock, flags);
282
283	gck->parent_id = field_get(gck->layout->gckcss_mask, tmp);
284	gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp);
285}
286
287struct clk_hw * __init
288at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
289			    const struct clk_pcr_layout *layout,
290			    const char *name, const char **parent_names,
291			    u32 *mux_table, u8 num_parents, u8 id,
292			    const struct clk_range *range,
293			    int chg_pid)
294{
295	struct clk_generated *gck;
296	struct clk_init_data init;
297	struct clk_hw *hw;
298	int ret;
299
300	gck = kzalloc(sizeof(*gck), GFP_KERNEL);
301	if (!gck)
302		return ERR_PTR(-ENOMEM);
303
304	init.name = name;
305	init.ops = &generated_ops;
306	init.parent_names = parent_names;
307	init.num_parents = num_parents;
308	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
309	if (chg_pid >= 0)
310		init.flags |= CLK_SET_RATE_PARENT;
311
312	gck->id = id;
313	gck->hw.init = &init;
314	gck->regmap = regmap;
315	gck->lock = lock;
316	gck->range = *range;
317	gck->chg_pid = chg_pid;
318	gck->layout = layout;
319	gck->mux_table = mux_table;
320
321	clk_generated_startup(gck);
322	hw = &gck->hw;
323	ret = clk_hw_register(NULL, &gck->hw);
324	if (ret) {
325		kfree(gck);
326		hw = ERR_PTR(ret);
327	} else {
328		pmc_register_id(id);
329	}
330
331	return hw;
332}
333