1// SPDX-License-Identifier: GPL-2.0 2#include <linux/clk-provider.h> 3#include <linux/mfd/syscon.h> 4#include <linux/slab.h> 5 6#include <dt-bindings/clock/at91.h> 7 8#include "pmc.h" 9 10static const struct clk_master_characteristics mck_characteristics = { 11 .output = { .min = 0, .max = 133333333 }, 12 .divisors = { 1, 2, 4, 3 }, 13}; 14 15static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 }; 16 17static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 }; 18 19static const struct clk_range plla_outputs[] = { 20 { .min = 745000000, .max = 800000000 }, 21 { .min = 695000000, .max = 750000000 }, 22 { .min = 645000000, .max = 700000000 }, 23 { .min = 595000000, .max = 650000000 }, 24 { .min = 545000000, .max = 600000000 }, 25 { .min = 495000000, .max = 555000000 }, 26 { .min = 445000000, .max = 500000000 }, 27 { .min = 400000000, .max = 450000000 }, 28}; 29 30static const struct clk_pll_characteristics plla_characteristics = { 31 .input = { .min = 2000000, .max = 32000000 }, 32 .num_output = ARRAY_SIZE(plla_outputs), 33 .output = plla_outputs, 34 .icpll = plla_icpll, 35 .out = plla_out, 36}; 37 38static const struct { 39 char *n; 40 char *p; 41 u8 id; 42} at91sam9g45_systemck[] = { 43 { .n = "ddrck", .p = "masterck", .id = 2 }, 44 { .n = "uhpck", .p = "usbck", .id = 6 }, 45 { .n = "pck0", .p = "prog0", .id = 8 }, 46 { .n = "pck1", .p = "prog1", .id = 9 }, 47}; 48 49struct pck { 50 char *n; 51 u8 id; 52}; 53 54static const struct pck at91sam9g45_periphck[] = { 55 { .n = "pioA_clk", .id = 2, }, 56 { .n = "pioB_clk", .id = 3, }, 57 { .n = "pioC_clk", .id = 4, }, 58 { .n = "pioDE_clk", .id = 5, }, 59 { .n = "trng_clk", .id = 6, }, 60 { .n = "usart0_clk", .id = 7, }, 61 { .n = "usart1_clk", .id = 8, }, 62 { .n = "usart2_clk", .id = 9, }, 63 { .n = "usart3_clk", .id = 10, }, 64 { .n = "mci0_clk", .id = 11, }, 65 { .n = "twi0_clk", .id = 12, }, 66 { .n = "twi1_clk", .id = 13, }, 67 { .n = "spi0_clk", .id = 14, }, 68 { .n = "spi1_clk", .id = 15, }, 69 { .n = "ssc0_clk", .id = 16, }, 70 { .n = "ssc1_clk", .id = 17, }, 71 { .n = "tcb0_clk", .id = 18, }, 72 { .n = "pwm_clk", .id = 19, }, 73 { .n = "adc_clk", .id = 20, }, 74 { .n = "dma0_clk", .id = 21, }, 75 { .n = "uhphs_clk", .id = 22, }, 76 { .n = "lcd_clk", .id = 23, }, 77 { .n = "ac97_clk", .id = 24, }, 78 { .n = "macb0_clk", .id = 25, }, 79 { .n = "isi_clk", .id = 26, }, 80 { .n = "udphs_clk", .id = 27, }, 81 { .n = "aestdessha_clk", .id = 28, }, 82 { .n = "mci1_clk", .id = 29, }, 83 { .n = "vdec_clk", .id = 30, }, 84}; 85 86static void __init at91sam9g45_pmc_setup(struct device_node *np) 87{ 88 const char *slck_name, *mainxtal_name; 89 struct pmc_data *at91sam9g45_pmc; 90 const char *parent_names[6]; 91 struct regmap *regmap; 92 struct clk_hw *hw; 93 int i; 94 bool bypass; 95 96 i = of_property_match_string(np, "clock-names", "slow_clk"); 97 if (i < 0) 98 return; 99 100 slck_name = of_clk_get_parent_name(np, i); 101 102 i = of_property_match_string(np, "clock-names", "main_xtal"); 103 if (i < 0) 104 return; 105 mainxtal_name = of_clk_get_parent_name(np, i); 106 107 regmap = device_node_to_regmap(np); 108 if (IS_ERR(regmap)) 109 return; 110 111 at91sam9g45_pmc = pmc_data_allocate(PMC_PLLACK + 1, 112 nck(at91sam9g45_systemck), 113 nck(at91sam9g45_periphck), 0, 2); 114 if (!at91sam9g45_pmc) 115 return; 116 117 bypass = of_property_read_bool(np, "atmel,osc-bypass"); 118 119 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, 120 bypass); 121 if (IS_ERR(hw)) 122 goto err_free; 123 124 hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc"); 125 if (IS_ERR(hw)) 126 goto err_free; 127 128 at91sam9g45_pmc->chws[PMC_MAIN] = hw; 129 130 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, 131 &at91rm9200_pll_layout, &plla_characteristics); 132 if (IS_ERR(hw)) 133 goto err_free; 134 135 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack"); 136 if (IS_ERR(hw)) 137 goto err_free; 138 139 at91sam9g45_pmc->chws[PMC_PLLACK] = hw; 140 141 hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck"); 142 if (IS_ERR(hw)) 143 goto err_free; 144 145 at91sam9g45_pmc->chws[PMC_UTMI] = hw; 146 147 parent_names[0] = slck_name; 148 parent_names[1] = "mainck"; 149 parent_names[2] = "plladivck"; 150 parent_names[3] = "utmick"; 151 hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, 152 &at91rm9200_master_layout, 153 &mck_characteristics); 154 if (IS_ERR(hw)) 155 goto err_free; 156 157 at91sam9g45_pmc->chws[PMC_MCK] = hw; 158 159 parent_names[0] = "plladivck"; 160 parent_names[1] = "utmick"; 161 hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); 162 if (IS_ERR(hw)) 163 goto err_free; 164 165 parent_names[0] = slck_name; 166 parent_names[1] = "mainck"; 167 parent_names[2] = "plladivck"; 168 parent_names[3] = "utmick"; 169 parent_names[4] = "masterck"; 170 for (i = 0; i < 2; i++) { 171 char name[6]; 172 173 snprintf(name, sizeof(name), "prog%d", i); 174 175 hw = at91_clk_register_programmable(regmap, name, 176 parent_names, 5, i, 177 &at91sam9g45_programmable_layout, 178 NULL); 179 if (IS_ERR(hw)) 180 goto err_free; 181 182 at91sam9g45_pmc->pchws[i] = hw; 183 } 184 185 for (i = 0; i < ARRAY_SIZE(at91sam9g45_systemck); i++) { 186 hw = at91_clk_register_system(regmap, at91sam9g45_systemck[i].n, 187 at91sam9g45_systemck[i].p, 188 at91sam9g45_systemck[i].id); 189 if (IS_ERR(hw)) 190 goto err_free; 191 192 at91sam9g45_pmc->shws[at91sam9g45_systemck[i].id] = hw; 193 } 194 195 for (i = 0; i < ARRAY_SIZE(at91sam9g45_periphck); i++) { 196 hw = at91_clk_register_peripheral(regmap, 197 at91sam9g45_periphck[i].n, 198 "masterck", 199 at91sam9g45_periphck[i].id); 200 if (IS_ERR(hw)) 201 goto err_free; 202 203 at91sam9g45_pmc->phws[at91sam9g45_periphck[i].id] = hw; 204 } 205 206 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9g45_pmc); 207 208 return; 209 210err_free: 211 kfree(at91sam9g45_pmc); 212} 213/* 214 * The TCB is used as the clocksource so its clock is needed early. This means 215 * this can't be a platform driver. 216 */ 217CLK_OF_DECLARE_DRIVER(at91sam9g45_pmc, "atmel,at91sam9g45-pmc", 218 at91sam9g45_pmc_setup); 219