1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Actions Semi S700 clock driver 4 * 5 * Copyright (c) 2014 Actions Semi Inc. 6 * Author: David Liu <liuwei@actions-semi.com> 7 * 8 * Author: Pathiban Nallathambi <pn@denx.de> 9 * Author: Saravanan Sekar <sravanhome@gmail.com> 10 */ 11 12#include <linux/clk-provider.h> 13#include <linux/platform_device.h> 14 15#include "owl-common.h" 16#include "owl-composite.h" 17#include "owl-divider.h" 18#include "owl-factor.h" 19#include "owl-fixed-factor.h" 20#include "owl-gate.h" 21#include "owl-mux.h" 22#include "owl-pll.h" 23#include "owl-reset.h" 24 25#include <dt-bindings/clock/actions,s700-cmu.h> 26#include <dt-bindings/reset/actions,s700-reset.h> 27 28#define CMU_COREPLL (0x0000) 29#define CMU_DEVPLL (0x0004) 30#define CMU_DDRPLL (0x0008) 31#define CMU_NANDPLL (0x000C) 32#define CMU_DISPLAYPLL (0x0010) 33#define CMU_AUDIOPLL (0x0014) 34#define CMU_TVOUTPLL (0x0018) 35#define CMU_BUSCLK (0x001C) 36#define CMU_SENSORCLK (0x0020) 37#define CMU_LCDCLK (0x0024) 38#define CMU_DSIPLLCLK (0x0028) 39#define CMU_CSICLK (0x002C) 40#define CMU_DECLK (0x0030) 41#define CMU_SICLK (0x0034) 42#define CMU_BUSCLK1 (0x0038) 43#define CMU_HDECLK (0x003C) 44#define CMU_VDECLK (0x0040) 45#define CMU_VCECLK (0x0044) 46#define CMU_NANDCCLK (0x004C) 47#define CMU_SD0CLK (0x0050) 48#define CMU_SD1CLK (0x0054) 49#define CMU_SD2CLK (0x0058) 50#define CMU_UART0CLK (0x005C) 51#define CMU_UART1CLK (0x0060) 52#define CMU_UART2CLK (0x0064) 53#define CMU_UART3CLK (0x0068) 54#define CMU_UART4CLK (0x006C) 55#define CMU_UART5CLK (0x0070) 56#define CMU_UART6CLK (0x0074) 57#define CMU_PWM0CLK (0x0078) 58#define CMU_PWM1CLK (0x007C) 59#define CMU_PWM2CLK (0x0080) 60#define CMU_PWM3CLK (0x0084) 61#define CMU_PWM4CLK (0x0088) 62#define CMU_PWM5CLK (0x008C) 63#define CMU_GPU3DCLK (0x0090) 64#define CMU_CORECTL (0x009C) 65#define CMU_DEVCLKEN0 (0x00A0) 66#define CMU_DEVCLKEN1 (0x00A4) 67#define CMU_DEVRST0 (0x00A8) 68#define CMU_DEVRST1 (0x00AC) 69#define CMU_USBPLL (0x00B0) 70#define CMU_ETHERNETPLL (0x00B4) 71#define CMU_CVBSPLL (0x00B8) 72#define CMU_SSTSCLK (0x00C0) 73 74static struct clk_pll_table clk_audio_pll_table[] = { 75 {0, 45158400}, {1, 49152000}, 76 {0, 0}, 77}; 78 79static struct clk_pll_table clk_cvbs_pll_table[] = { 80 {27, 29 * 12000000}, {28, 30 * 12000000}, {29, 31 * 12000000}, 81 {30, 32 * 12000000}, {31, 33 * 12000000}, {32, 34 * 12000000}, 82 {33, 35 * 12000000}, {34, 36 * 12000000}, {35, 37 * 12000000}, 83 {36, 38 * 12000000}, {37, 39 * 12000000}, {38, 40 * 12000000}, 84 {39, 41 * 12000000}, {40, 42 * 12000000}, {41, 43 * 12000000}, 85 {42, 44 * 12000000}, {43, 45 * 12000000}, {0, 0}, 86}; 87 88/* pll clocks */ 89static OWL_PLL_NO_PARENT(clk_core_pll, "core_pll", CMU_COREPLL, 12000000, 9, 0, 8, 4, 174, NULL, CLK_IGNORE_UNUSED); 90static OWL_PLL_NO_PARENT(clk_dev_pll, "dev_pll", CMU_DEVPLL, 6000000, 8, 0, 8, 8, 126, NULL, CLK_IGNORE_UNUSED); 91static OWL_PLL_NO_PARENT(clk_ddr_pll, "ddr_pll", CMU_DDRPLL, 6000000, 8, 0, 8, 2, 180, NULL, CLK_IGNORE_UNUSED); 92static OWL_PLL_NO_PARENT(clk_nand_pll, "nand_pll", CMU_NANDPLL, 6000000, 8, 0, 8, 2, 86, NULL, CLK_IGNORE_UNUSED); 93static OWL_PLL_NO_PARENT(clk_display_pll, "display_pll", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 140, NULL, CLK_IGNORE_UNUSED); 94static OWL_PLL_NO_PARENT(clk_cvbs_pll, "cvbs_pll", CMU_CVBSPLL, 0, 8, 0, 8, 27, 43, clk_cvbs_pll_table, CLK_IGNORE_UNUSED); 95static OWL_PLL_NO_PARENT(clk_audio_pll, "audio_pll", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, clk_audio_pll_table, CLK_IGNORE_UNUSED); 96static OWL_PLL_NO_PARENT(clk_ethernet_pll, "ethernet_pll", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, NULL, CLK_IGNORE_UNUSED); 97 98static const char *cpu_clk_mux_p[] = {"losc", "hosc", "core_pll", "noc1_clk_div"}; 99static const char *dev_clk_p[] = { "hosc", "dev_pll"}; 100static const char *noc_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll", "cvbs_pll"}; 101 102static const char *csi_clk_mux_p[] = { "display_pll", "dev_clk"}; 103static const char *de_clk_mux_p[] = { "display_pll", "dev_clk"}; 104static const char *hde_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll"}; 105static const char *nand_clk_mux_p[] = { "nand_pll", "display_pll", "dev_clk", "ddr_pll"}; 106static const char *sd_clk_mux_p[] = { "dev_clk", "nand_pll", }; 107static const char *uart_clk_mux_p[] = { "hosc", "dev_pll"}; 108static const char *pwm_clk_mux_p[] = { "losc", "hosc"}; 109static const char *gpu_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_clk", "cvbs_pll"}; 110static const char *lcd_clk_mux_p[] = { "display_pll", "dev_clk" }; 111static const char *i2s_clk_mux_p[] = { "audio_pll" }; 112static const char *sensor_clk_mux_p[] = { "hosc", "si"}; 113 114/* mux clocks */ 115static OWL_MUX(clk_cpu, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT); 116static OWL_MUX(clk_dev, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT); 117static OWL_MUX(clk_noc0_clk_mux, "noc0_clk_mux", noc_clk_mux_p, CMU_BUSCLK, 4, 3, CLK_SET_RATE_PARENT); 118static OWL_MUX(clk_noc1_clk_mux, "noc1_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 4, 3, CLK_SET_RATE_PARENT); 119static OWL_MUX(clk_hp_clk_mux, "hp_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT); 120 121static struct clk_factor_table sd_factor_table[] = { 122 /* bit0 ~ 4 */ 123 {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4}, 124 {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8}, 125 {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12}, 126 {12, 1, 13}, {13, 1, 14}, {14, 1, 15}, {15, 1, 16}, 127 {16, 1, 17}, {17, 1, 18}, {18, 1, 19}, {19, 1, 20}, 128 {20, 1, 21}, {21, 1, 22}, {22, 1, 23}, {23, 1, 24}, 129 {24, 1, 25}, {25, 1, 26}, 130 131 /* bit8: /128 */ 132 {256, 1, 1 * 128}, {257, 1, 2 * 128}, {258, 1, 3 * 128}, {259, 1, 4 * 128}, 133 {260, 1, 5 * 128}, {261, 1, 6 * 128}, {262, 1, 7 * 128}, {263, 1, 8 * 128}, 134 {264, 1, 9 * 128}, {265, 1, 10 * 128}, {266, 1, 11 * 128}, {267, 1, 12 * 128}, 135 {268, 1, 13 * 128}, {269, 1, 14 * 128}, {270, 1, 15 * 128}, {271, 1, 16 * 128}, 136 {272, 1, 17 * 128}, {273, 1, 18 * 128}, {274, 1, 19 * 128}, {275, 1, 20 * 128}, 137 {276, 1, 21 * 128}, {277, 1, 22 * 128}, {278, 1, 23 * 128}, {279, 1, 24 * 128}, 138 {280, 1, 25 * 128}, {281, 1, 26 * 128}, 139 140 {0, 0}, 141}; 142 143static struct clk_factor_table lcd_factor_table[] = { 144 /* bit0 ~ 3 */ 145 {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4}, 146 {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8}, 147 {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12}, 148 149 /* bit8: /7 */ 150 {256, 1, 1 * 7}, {257, 1, 2 * 7}, {258, 1, 3 * 7}, {259, 1, 4 * 7}, 151 {260, 1, 5 * 7}, {261, 1, 6 * 7}, {262, 1, 7 * 7}, {263, 1, 8 * 7}, 152 {264, 1, 9 * 7}, {265, 1, 10 * 7}, {266, 1, 11 * 7}, {267, 1, 12 * 7}, 153 {0, 0}, 154}; 155 156static struct clk_div_table hdmia_div_table[] = { 157 {0, 1}, {1, 2}, {2, 3}, {3, 4}, 158 {4, 6}, {5, 8}, {6, 12}, {7, 16}, 159 {8, 24}, 160 {0, 0}, 161}; 162 163static struct clk_div_table rmii_div_table[] = { 164 {0, 4}, {1, 10}, 165 {0, 0} 166}; 167 168/* divider clocks */ 169static OWL_DIVIDER(clk_noc0, "noc0_clk", "noc0_clk_mux", CMU_BUSCLK, 16, 2, NULL, 0, 0); 170static OWL_DIVIDER(clk_noc1, "noc1_clk", "noc1_clk_mux", CMU_BUSCLK1, 16, 2, NULL, 0, 0); 171static OWL_DIVIDER(clk_noc1_clk_div, "noc1_clk_div", "noc1_clk", CMU_BUSCLK1, 20, 1, NULL, 0, 0); 172static OWL_DIVIDER(clk_hp_clk_div, "hp_clk_div", "hp_clk_mux", CMU_BUSCLK1, 12, 2, NULL, 0, 0); 173static OWL_DIVIDER(clk_ahb, "ahb_clk", "hp_clk_div", CMU_BUSCLK1, 2, 2, NULL, 0, 0); 174static OWL_DIVIDER(clk_apb, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0); 175static OWL_DIVIDER(clk_sensor0, "sensor0", "sensor_src", CMU_SENSORCLK, 0, 4, NULL, 0, 0); 176static OWL_DIVIDER(clk_sensor1, "sensor1", "sensor_src", CMU_SENSORCLK, 8, 4, NULL, 0, 0); 177static OWL_DIVIDER(clk_rmii_ref, "rmii_ref", "ethernet_pll", CMU_ETHERNETPLL, 2, 1, rmii_div_table, 0, 0); 178 179static struct clk_factor_table de_factor_table[] = { 180 {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5}, 181 {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8}, 182 {8, 1, 12}, {0, 0, 0}, 183}; 184 185static struct clk_factor_table hde_factor_table[] = { 186 {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5}, 187 {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8}, 188 {0, 0, 0}, 189}; 190 191/* gate clocks */ 192static OWL_GATE(clk_gpio, "gpio", "apb_clk", CMU_DEVCLKEN1, 25, 0, 0); 193static OWL_GATE(clk_dmac, "dmac", "hp_clk_div", CMU_DEVCLKEN0, 17, 0, 0); 194static OWL_GATE(clk_timer, "timer", "hosc", CMU_DEVCLKEN1, 22, 0, 0); 195static OWL_GATE_NO_PARENT(clk_dsi, "dsi_clk", CMU_DEVCLKEN0, 2, 0, 0); 196static OWL_GATE_NO_PARENT(clk_tvout, "tvout_clk", CMU_DEVCLKEN0, 3, 0, 0); 197static OWL_GATE_NO_PARENT(clk_hdmi_dev, "hdmi_dev", CMU_DEVCLKEN0, 5, 0, 0); 198static OWL_GATE_NO_PARENT(clk_usb3_480mpll0, "usb3_480mpll0", CMU_USBPLL, 3, 0, 0); 199static OWL_GATE_NO_PARENT(clk_usb3_480mphy0, "usb3_480mphy0", CMU_USBPLL, 2, 0, 0); 200static OWL_GATE_NO_PARENT(clk_usb3_5gphy, "usb3_5gphy", CMU_USBPLL, 1, 0, 0); 201static OWL_GATE_NO_PARENT(clk_usb3_cce, "usb3_cce", CMU_DEVCLKEN0, 25, 0, 0); 202static OWL_GATE(clk_i2c0, "i2c0", "hosc", CMU_DEVCLKEN1, 0, 0, 0); 203static OWL_GATE(clk_i2c1, "i2c1", "hosc", CMU_DEVCLKEN1, 1, 0, 0); 204static OWL_GATE(clk_i2c2, "i2c2", "hosc", CMU_DEVCLKEN1, 2, 0, 0); 205static OWL_GATE(clk_i2c3, "i2c3", "hosc", CMU_DEVCLKEN1, 3, 0, 0); 206static OWL_GATE(clk_spi0, "spi0", "ahb_clk", CMU_DEVCLKEN1, 4, 0, 0); 207static OWL_GATE(clk_spi1, "spi1", "ahb_clk", CMU_DEVCLKEN1, 5, 0, 0); 208static OWL_GATE(clk_spi2, "spi2", "ahb_clk", CMU_DEVCLKEN1, 6, 0, 0); 209static OWL_GATE(clk_spi3, "spi3", "ahb_clk", CMU_DEVCLKEN1, 7, 0, 0); 210static OWL_GATE_NO_PARENT(clk_usb2h0_pllen, "usbh0_pllen", CMU_USBPLL, 12, 0, 0); 211static OWL_GATE_NO_PARENT(clk_usb2h0_phy, "usbh0_phy", CMU_USBPLL, 10, 0, 0); 212static OWL_GATE_NO_PARENT(clk_usb2h0_cce, "usbh0_cce", CMU_DEVCLKEN0, 26, 0, 0); 213static OWL_GATE_NO_PARENT(clk_usb2h1_pllen, "usbh1_pllen", CMU_USBPLL, 13, 0, 0); 214static OWL_GATE_NO_PARENT(clk_usb2h1_phy, "usbh1_phy", CMU_USBPLL, 11, 0, 0); 215static OWL_GATE_NO_PARENT(clk_usb2h1_cce, "usbh1_cce", CMU_DEVCLKEN0, 27, 0, 0); 216static OWL_GATE_NO_PARENT(clk_irc_switch, "irc_switch", CMU_DEVCLKEN1, 15, 0, 0); 217 218/* composite clocks */ 219 220static OWL_COMP_DIV(clk_csi, "csi", csi_clk_mux_p, 221 OWL_MUX_HW(CMU_CSICLK, 4, 1), 222 OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0), 223 OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL), 224 0); 225 226static OWL_COMP_DIV(clk_si, "si", csi_clk_mux_p, 227 OWL_MUX_HW(CMU_SICLK, 4, 1), 228 OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), 229 OWL_DIVIDER_HW(CMU_SICLK, 0, 4, 0, NULL), 230 0); 231 232static OWL_COMP_FACTOR(clk_de, "de", de_clk_mux_p, 233 OWL_MUX_HW(CMU_DECLK, 12, 1), 234 OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0), 235 OWL_FACTOR_HW(CMU_DECLK, 0, 3, 0, de_factor_table), 236 0); 237 238static OWL_COMP_FACTOR(clk_hde, "hde", hde_clk_mux_p, 239 OWL_MUX_HW(CMU_HDECLK, 4, 2), 240 OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0), 241 OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, hde_factor_table), 242 0); 243 244static OWL_COMP_FACTOR(clk_vde, "vde", hde_clk_mux_p, 245 OWL_MUX_HW(CMU_VDECLK, 4, 2), 246 OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0), 247 OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table), 248 0); 249 250static OWL_COMP_FACTOR(clk_vce, "vce", hde_clk_mux_p, 251 OWL_MUX_HW(CMU_VCECLK, 4, 2), 252 OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0), 253 OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table), 254 0); 255 256static OWL_COMP_DIV(clk_nand, "nand", nand_clk_mux_p, 257 OWL_MUX_HW(CMU_NANDCCLK, 8, 2), 258 OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0), 259 OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, NULL), 260 CLK_SET_RATE_PARENT); 261 262static OWL_COMP_FACTOR(clk_sd0, "sd0", sd_clk_mux_p, 263 OWL_MUX_HW(CMU_SD0CLK, 9, 1), 264 OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0), 265 OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table), 266 0); 267 268static OWL_COMP_FACTOR(clk_sd1, "sd1", sd_clk_mux_p, 269 OWL_MUX_HW(CMU_SD1CLK, 9, 1), 270 OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0), 271 OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table), 272 0); 273 274static OWL_COMP_FACTOR(clk_sd2, "sd2", sd_clk_mux_p, 275 OWL_MUX_HW(CMU_SD2CLK, 9, 1), 276 OWL_GATE_HW(CMU_DEVCLKEN0, 24, 0), 277 OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table), 278 0); 279 280static OWL_COMP_DIV(clk_uart0, "uart0", uart_clk_mux_p, 281 OWL_MUX_HW(CMU_UART0CLK, 16, 1), 282 OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0), 283 OWL_DIVIDER_HW(CMU_UART0CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 284 0); 285 286static OWL_COMP_DIV(clk_uart1, "uart1", uart_clk_mux_p, 287 OWL_MUX_HW(CMU_UART1CLK, 16, 1), 288 OWL_GATE_HW(CMU_DEVCLKEN1, 9, 0), 289 OWL_DIVIDER_HW(CMU_UART1CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 290 0); 291 292static OWL_COMP_DIV(clk_uart2, "uart2", uart_clk_mux_p, 293 OWL_MUX_HW(CMU_UART2CLK, 16, 1), 294 OWL_GATE_HW(CMU_DEVCLKEN1, 10, 0), 295 OWL_DIVIDER_HW(CMU_UART2CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 296 0); 297 298static OWL_COMP_DIV(clk_uart3, "uart3", uart_clk_mux_p, 299 OWL_MUX_HW(CMU_UART3CLK, 16, 1), 300 OWL_GATE_HW(CMU_DEVCLKEN1, 11, 0), 301 OWL_DIVIDER_HW(CMU_UART3CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 302 0); 303 304static OWL_COMP_DIV(clk_uart4, "uart4", uart_clk_mux_p, 305 OWL_MUX_HW(CMU_UART4CLK, 16, 1), 306 OWL_GATE_HW(CMU_DEVCLKEN1, 12, 0), 307 OWL_DIVIDER_HW(CMU_UART4CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 308 0); 309 310static OWL_COMP_DIV(clk_uart5, "uart5", uart_clk_mux_p, 311 OWL_MUX_HW(CMU_UART5CLK, 16, 1), 312 OWL_GATE_HW(CMU_DEVCLKEN1, 13, 0), 313 OWL_DIVIDER_HW(CMU_UART5CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 314 0); 315 316static OWL_COMP_DIV(clk_uart6, "uart6", uart_clk_mux_p, 317 OWL_MUX_HW(CMU_UART6CLK, 16, 1), 318 OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0), 319 OWL_DIVIDER_HW(CMU_UART6CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 320 0); 321 322static OWL_COMP_DIV(clk_pwm0, "pwm0", pwm_clk_mux_p, 323 OWL_MUX_HW(CMU_PWM0CLK, 12, 1), 324 OWL_GATE_HW(CMU_DEVCLKEN1, 16, 0), 325 OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL), 326 CLK_IGNORE_UNUSED); 327 328static OWL_COMP_DIV(clk_pwm1, "pwm1", pwm_clk_mux_p, 329 OWL_MUX_HW(CMU_PWM1CLK, 12, 1), 330 OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0), 331 OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL), 332 0); 333 334static OWL_COMP_DIV(clk_pwm2, "pwm2", pwm_clk_mux_p, 335 OWL_MUX_HW(CMU_PWM2CLK, 12, 1), 336 OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0), 337 OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL), 338 0); 339 340static OWL_COMP_DIV(clk_pwm3, "pwm3", pwm_clk_mux_p, 341 OWL_MUX_HW(CMU_PWM3CLK, 12, 1), 342 OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0), 343 OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL), 344 0); 345 346static OWL_COMP_DIV(clk_pwm4, "pwm4", pwm_clk_mux_p, 347 OWL_MUX_HW(CMU_PWM4CLK, 12, 1), 348 OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0), 349 OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL), 350 0); 351 352static OWL_COMP_DIV(clk_pwm5, "pwm5", pwm_clk_mux_p, 353 OWL_MUX_HW(CMU_PWM5CLK, 12, 1), 354 OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0), 355 OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL), 356 0); 357 358static OWL_COMP_FACTOR(clk_gpu3d, "gpu3d", gpu_clk_mux_p, 359 OWL_MUX_HW(CMU_GPU3DCLK, 4, 3), 360 OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0), 361 OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, hde_factor_table), 362 0); 363 364static OWL_COMP_FACTOR(clk_lcd, "lcd", lcd_clk_mux_p, 365 OWL_MUX_HW(CMU_LCDCLK, 12, 2), 366 OWL_GATE_HW(CMU_DEVCLKEN0, 1, 0), 367 OWL_FACTOR_HW(CMU_LCDCLK, 0, 9, 0, lcd_factor_table), 368 0); 369 370static OWL_COMP_DIV(clk_hdmi_audio, "hdmia", i2s_clk_mux_p, 371 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), /*CMU_AUDIOPLL 24,1 unused*/ 372 OWL_GATE_HW(CMU_DEVCLKEN1, 28, 0), 373 OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table), 374 0); 375 376static OWL_COMP_DIV(clk_i2srx, "i2srx", i2s_clk_mux_p, 377 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), 378 OWL_GATE_HW(CMU_DEVCLKEN1, 27, 0), 379 OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, hdmia_div_table), 380 0); 381 382static OWL_COMP_DIV(clk_i2stx, "i2stx", i2s_clk_mux_p, 383 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), 384 OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0), 385 OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, hdmia_div_table), 386 0); 387 388/* for bluetooth pcm communication */ 389static OWL_COMP_FIXED_FACTOR(clk_pcm1, "pcm1", "audio_pll", 390 OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0), 391 1, 2, 0); 392 393static OWL_COMP_DIV(clk_sensor_src, "sensor_src", sensor_clk_mux_p, 394 OWL_MUX_HW(CMU_SENSORCLK, 4, 1), 395 {0}, 396 OWL_DIVIDER_HW(CMU_SENSORCLK, 5, 2, 0, NULL), 397 0); 398 399static OWL_COMP_FIXED_FACTOR(clk_ethernet, "ethernet", "ethernet_pll", 400 OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0), 401 1, 20, 0); 402 403static OWL_COMP_DIV_FIXED(clk_thermal_sensor, "thermal_sensor", "hosc", 404 OWL_GATE_HW(CMU_DEVCLKEN0, 31, 0), 405 OWL_DIVIDER_HW(CMU_SSTSCLK, 20, 10, 0, NULL), 406 0); 407 408static struct owl_clk_common *s700_clks[] = { 409 &clk_core_pll.common, 410 &clk_dev_pll.common, 411 &clk_ddr_pll.common, 412 &clk_nand_pll.common, 413 &clk_display_pll.common, 414 &clk_cvbs_pll .common, 415 &clk_audio_pll.common, 416 &clk_ethernet_pll.common, 417 &clk_cpu.common, 418 &clk_dev.common, 419 &clk_ahb.common, 420 &clk_apb.common, 421 &clk_dmac.common, 422 &clk_noc0_clk_mux.common, 423 &clk_noc1_clk_mux.common, 424 &clk_hp_clk_mux.common, 425 &clk_hp_clk_div.common, 426 &clk_noc1_clk_div.common, 427 &clk_noc0.common, 428 &clk_noc1.common, 429 &clk_sensor_src.common, 430 &clk_gpio.common, 431 &clk_timer.common, 432 &clk_dsi.common, 433 &clk_csi.common, 434 &clk_si.common, 435 &clk_de.common, 436 &clk_hde.common, 437 &clk_vde.common, 438 &clk_vce.common, 439 &clk_nand.common, 440 &clk_sd0.common, 441 &clk_sd1.common, 442 &clk_sd2.common, 443 &clk_uart0.common, 444 &clk_uart1.common, 445 &clk_uart2.common, 446 &clk_uart3.common, 447 &clk_uart4.common, 448 &clk_uart5.common, 449 &clk_uart6.common, 450 &clk_pwm0.common, 451 &clk_pwm1.common, 452 &clk_pwm2.common, 453 &clk_pwm3.common, 454 &clk_pwm4.common, 455 &clk_pwm5.common, 456 &clk_gpu3d.common, 457 &clk_i2c0.common, 458 &clk_i2c1.common, 459 &clk_i2c2.common, 460 &clk_i2c3.common, 461 &clk_spi0.common, 462 &clk_spi1.common, 463 &clk_spi2.common, 464 &clk_spi3.common, 465 &clk_usb3_480mpll0.common, 466 &clk_usb3_480mphy0.common, 467 &clk_usb3_5gphy.common, 468 &clk_usb3_cce.common, 469 &clk_lcd.common, 470 &clk_hdmi_audio.common, 471 &clk_i2srx.common, 472 &clk_i2stx.common, 473 &clk_sensor0.common, 474 &clk_sensor1.common, 475 &clk_hdmi_dev.common, 476 &clk_ethernet.common, 477 &clk_rmii_ref.common, 478 &clk_usb2h0_pllen.common, 479 &clk_usb2h0_phy.common, 480 &clk_usb2h0_cce.common, 481 &clk_usb2h1_pllen.common, 482 &clk_usb2h1_phy.common, 483 &clk_usb2h1_cce.common, 484 &clk_tvout.common, 485 &clk_thermal_sensor.common, 486 &clk_irc_switch.common, 487 &clk_pcm1.common, 488}; 489 490static struct clk_hw_onecell_data s700_hw_clks = { 491 .hws = { 492 [CLK_CORE_PLL] = &clk_core_pll.common.hw, 493 [CLK_DEV_PLL] = &clk_dev_pll.common.hw, 494 [CLK_DDR_PLL] = &clk_ddr_pll.common.hw, 495 [CLK_NAND_PLL] = &clk_nand_pll.common.hw, 496 [CLK_DISPLAY_PLL] = &clk_display_pll.common.hw, 497 [CLK_CVBS_PLL] = &clk_cvbs_pll .common.hw, 498 [CLK_AUDIO_PLL] = &clk_audio_pll.common.hw, 499 [CLK_ETHERNET_PLL] = &clk_ethernet_pll.common.hw, 500 [CLK_CPU] = &clk_cpu.common.hw, 501 [CLK_DEV] = &clk_dev.common.hw, 502 [CLK_AHB] = &clk_ahb.common.hw, 503 [CLK_APB] = &clk_apb.common.hw, 504 [CLK_DMAC] = &clk_dmac.common.hw, 505 [CLK_NOC0_CLK_MUX] = &clk_noc0_clk_mux.common.hw, 506 [CLK_NOC1_CLK_MUX] = &clk_noc1_clk_mux.common.hw, 507 [CLK_HP_CLK_MUX] = &clk_hp_clk_mux.common.hw, 508 [CLK_HP_CLK_DIV] = &clk_hp_clk_div.common.hw, 509 [CLK_NOC1_CLK_DIV] = &clk_noc1_clk_div.common.hw, 510 [CLK_NOC0] = &clk_noc0.common.hw, 511 [CLK_NOC1] = &clk_noc1.common.hw, 512 [CLK_SENOR_SRC] = &clk_sensor_src.common.hw, 513 [CLK_GPIO] = &clk_gpio.common.hw, 514 [CLK_TIMER] = &clk_timer.common.hw, 515 [CLK_DSI] = &clk_dsi.common.hw, 516 [CLK_CSI] = &clk_csi.common.hw, 517 [CLK_SI] = &clk_si.common.hw, 518 [CLK_DE] = &clk_de.common.hw, 519 [CLK_HDE] = &clk_hde.common.hw, 520 [CLK_VDE] = &clk_vde.common.hw, 521 [CLK_VCE] = &clk_vce.common.hw, 522 [CLK_NAND] = &clk_nand.common.hw, 523 [CLK_SD0] = &clk_sd0.common.hw, 524 [CLK_SD1] = &clk_sd1.common.hw, 525 [CLK_SD2] = &clk_sd2.common.hw, 526 [CLK_UART0] = &clk_uart0.common.hw, 527 [CLK_UART1] = &clk_uart1.common.hw, 528 [CLK_UART2] = &clk_uart2.common.hw, 529 [CLK_UART3] = &clk_uart3.common.hw, 530 [CLK_UART4] = &clk_uart4.common.hw, 531 [CLK_UART5] = &clk_uart5.common.hw, 532 [CLK_UART6] = &clk_uart6.common.hw, 533 [CLK_PWM0] = &clk_pwm0.common.hw, 534 [CLK_PWM1] = &clk_pwm1.common.hw, 535 [CLK_PWM2] = &clk_pwm2.common.hw, 536 [CLK_PWM3] = &clk_pwm3.common.hw, 537 [CLK_PWM4] = &clk_pwm4.common.hw, 538 [CLK_PWM5] = &clk_pwm5.common.hw, 539 [CLK_GPU3D] = &clk_gpu3d.common.hw, 540 [CLK_I2C0] = &clk_i2c0.common.hw, 541 [CLK_I2C1] = &clk_i2c1.common.hw, 542 [CLK_I2C2] = &clk_i2c2.common.hw, 543 [CLK_I2C3] = &clk_i2c3.common.hw, 544 [CLK_SPI0] = &clk_spi0.common.hw, 545 [CLK_SPI1] = &clk_spi1.common.hw, 546 [CLK_SPI2] = &clk_spi2.common.hw, 547 [CLK_SPI3] = &clk_spi3.common.hw, 548 [CLK_USB3_480MPLL0] = &clk_usb3_480mpll0.common.hw, 549 [CLK_USB3_480MPHY0] = &clk_usb3_480mphy0.common.hw, 550 [CLK_USB3_5GPHY] = &clk_usb3_5gphy.common.hw, 551 [CLK_USB3_CCE] = &clk_usb3_cce.common.hw, 552 [CLK_LCD] = &clk_lcd.common.hw, 553 [CLK_HDMI_AUDIO] = &clk_hdmi_audio.common.hw, 554 [CLK_I2SRX] = &clk_i2srx.common.hw, 555 [CLK_I2STX] = &clk_i2stx.common.hw, 556 [CLK_SENSOR0] = &clk_sensor0.common.hw, 557 [CLK_SENSOR1] = &clk_sensor1.common.hw, 558 [CLK_HDMI_DEV] = &clk_hdmi_dev.common.hw, 559 [CLK_ETHERNET] = &clk_ethernet.common.hw, 560 [CLK_RMII_REF] = &clk_rmii_ref.common.hw, 561 [CLK_USB2H0_PLLEN] = &clk_usb2h0_pllen.common.hw, 562 [CLK_USB2H0_PHY] = &clk_usb2h0_phy.common.hw, 563 [CLK_USB2H0_CCE] = &clk_usb2h0_cce.common.hw, 564 [CLK_USB2H1_PLLEN] = &clk_usb2h1_pllen.common.hw, 565 [CLK_USB2H1_PHY] = &clk_usb2h1_phy.common.hw, 566 [CLK_USB2H1_CCE] = &clk_usb2h1_cce.common.hw, 567 [CLK_TVOUT] = &clk_tvout.common.hw, 568 [CLK_THERMAL_SENSOR] = &clk_thermal_sensor.common.hw, 569 [CLK_IRC_SWITCH] = &clk_irc_switch.common.hw, 570 [CLK_PCM1] = &clk_pcm1.common.hw, 571 }, 572 .num = CLK_NR_CLKS, 573}; 574 575static const struct owl_reset_map s700_resets[] = { 576 [RESET_DE] = { CMU_DEVRST0, BIT(0) }, 577 [RESET_LCD0] = { CMU_DEVRST0, BIT(1) }, 578 [RESET_DSI] = { CMU_DEVRST0, BIT(2) }, 579 [RESET_CSI] = { CMU_DEVRST0, BIT(13) }, 580 [RESET_SI] = { CMU_DEVRST0, BIT(14) }, 581 [RESET_I2C0] = { CMU_DEVRST1, BIT(0) }, 582 [RESET_I2C1] = { CMU_DEVRST1, BIT(1) }, 583 [RESET_I2C2] = { CMU_DEVRST1, BIT(2) }, 584 [RESET_I2C3] = { CMU_DEVRST1, BIT(3) }, 585 [RESET_SPI0] = { CMU_DEVRST1, BIT(4) }, 586 [RESET_SPI1] = { CMU_DEVRST1, BIT(5) }, 587 [RESET_SPI2] = { CMU_DEVRST1, BIT(6) }, 588 [RESET_SPI3] = { CMU_DEVRST1, BIT(7) }, 589 [RESET_UART0] = { CMU_DEVRST1, BIT(8) }, 590 [RESET_UART1] = { CMU_DEVRST1, BIT(9) }, 591 [RESET_UART2] = { CMU_DEVRST1, BIT(10) }, 592 [RESET_UART3] = { CMU_DEVRST1, BIT(11) }, 593 [RESET_UART4] = { CMU_DEVRST1, BIT(12) }, 594 [RESET_UART5] = { CMU_DEVRST1, BIT(13) }, 595 [RESET_UART6] = { CMU_DEVRST1, BIT(14) }, 596 [RESET_KEY] = { CMU_DEVRST1, BIT(24) }, 597 [RESET_GPIO] = { CMU_DEVRST1, BIT(25) }, 598 [RESET_AUDIO] = { CMU_DEVRST1, BIT(29) }, 599}; 600 601static struct owl_clk_desc s700_clk_desc = { 602 .clks = s700_clks, 603 .num_clks = ARRAY_SIZE(s700_clks), 604 605 .hw_clks = &s700_hw_clks, 606 607 .resets = s700_resets, 608 .num_resets = ARRAY_SIZE(s700_resets), 609}; 610 611static int s700_clk_probe(struct platform_device *pdev) 612{ 613 struct owl_clk_desc *desc; 614 struct owl_reset *reset; 615 int ret; 616 617 desc = &s700_clk_desc; 618 owl_clk_regmap_init(pdev, desc); 619 620 /* 621 * FIXME: Reset controller registration should be moved to 622 * common code, once all SoCs of Owl family supports it. 623 */ 624 reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); 625 if (!reset) 626 return -ENOMEM; 627 628 reset->rcdev.of_node = pdev->dev.of_node; 629 reset->rcdev.ops = &owl_reset_ops; 630 reset->rcdev.nr_resets = desc->num_resets; 631 reset->reset_map = desc->resets; 632 reset->regmap = desc->regmap; 633 634 ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev); 635 if (ret) 636 dev_err(&pdev->dev, "Failed to register reset controller\n"); 637 638 return owl_clk_probe(&pdev->dev, desc->hw_clks); 639} 640 641static const struct of_device_id s700_clk_of_match[] = { 642 { .compatible = "actions,s700-cmu", }, 643 { /* sentinel */ } 644}; 645 646static struct platform_driver s700_clk_driver = { 647 .probe = s700_clk_probe, 648 .driver = { 649 .name = "s700-cmu", 650 .of_match_table = s700_clk_of_match 651 }, 652}; 653 654static int __init s700_clk_init(void) 655{ 656 return platform_driver_register(&s700_clk_driver); 657} 658core_initcall(s700_clk_init); 659