1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2016 Google, Inc
4 *
5 * This device driver implements a TCG PTP FIFO interface over SPI for chips
6 * with Cr50 firmware.
7 * It is based on tpm_tis_spi driver by Peter Huewe and Christophe Ricard.
8 */
9
10#include <linux/completion.h>
11#include <linux/interrupt.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/pm.h>
15#include <linux/spi/spi.h>
16#include <linux/wait.h>
17
18#include "tpm_tis_core.h"
19#include "tpm_tis_spi.h"
20
21/*
22 * Cr50 timing constants:
23 * - can go to sleep not earlier than after CR50_SLEEP_DELAY_MSEC.
24 * - needs up to CR50_WAKE_START_DELAY_USEC to wake after sleep.
25 * - requires waiting for "ready" IRQ, if supported; or waiting for at least
26 *   CR50_NOIRQ_ACCESS_DELAY_MSEC between transactions, if IRQ is not supported.
27 * - waits for up to CR50_FLOW_CONTROL for flow control 'ready' indication.
28 */
29#define CR50_SLEEP_DELAY_MSEC			1000
30#define CR50_WAKE_START_DELAY_USEC		1000
31#define CR50_NOIRQ_ACCESS_DELAY			msecs_to_jiffies(2)
32#define CR50_READY_IRQ_TIMEOUT			msecs_to_jiffies(TPM2_TIMEOUT_A)
33#define CR50_FLOW_CONTROL			msecs_to_jiffies(TPM2_TIMEOUT_A)
34#define MAX_IRQ_CONFIRMATION_ATTEMPTS		3
35
36#define TPM_CR50_FW_VER(l)			(0x0f90 | ((l) << 12))
37#define TPM_CR50_MAX_FW_VER_LEN			64
38
39struct cr50_spi_phy {
40	struct tpm_tis_spi_phy spi_phy;
41
42	struct mutex time_track_mutex;
43	unsigned long last_access;
44
45	unsigned long access_delay;
46
47	unsigned int irq_confirmation_attempt;
48	bool irq_needs_confirmation;
49	bool irq_confirmed;
50};
51
52static inline struct cr50_spi_phy *to_cr50_spi_phy(struct tpm_tis_spi_phy *phy)
53{
54	return container_of(phy, struct cr50_spi_phy, spi_phy);
55}
56
57/*
58 * The cr50 interrupt handler just signals waiting threads that the
59 * interrupt was asserted.  It does not do any processing triggered
60 * by interrupts but is instead used to avoid fixed delays.
61 */
62static irqreturn_t cr50_spi_irq_handler(int dummy, void *dev_id)
63{
64	struct cr50_spi_phy *cr50_phy = dev_id;
65
66	cr50_phy->irq_confirmed = true;
67	complete(&cr50_phy->spi_phy.ready);
68
69	return IRQ_HANDLED;
70}
71
72/*
73 * Cr50 needs to have at least some delay between consecutive
74 * transactions. Make sure we wait.
75 */
76static void cr50_ensure_access_delay(struct cr50_spi_phy *phy)
77{
78	unsigned long allowed_access = phy->last_access + phy->access_delay;
79	unsigned long time_now = jiffies;
80	struct device *dev = &phy->spi_phy.spi_device->dev;
81
82	/*
83	 * Note: There is a small chance, if Cr50 is not accessed in a few days,
84	 * that time_in_range will not provide the correct result after the wrap
85	 * around for jiffies. In this case, we'll have an unneeded short delay,
86	 * which is fine.
87	 */
88	if (time_in_range_open(time_now, phy->last_access, allowed_access)) {
89		unsigned long remaining, timeout = allowed_access - time_now;
90
91		remaining = wait_for_completion_timeout(&phy->spi_phy.ready,
92							timeout);
93		if (!remaining && phy->irq_confirmed)
94			dev_warn(dev, "Timeout waiting for TPM ready IRQ\n");
95	}
96
97	if (phy->irq_needs_confirmation) {
98		unsigned int attempt = ++phy->irq_confirmation_attempt;
99
100		if (phy->irq_confirmed) {
101			phy->irq_needs_confirmation = false;
102			phy->access_delay = CR50_READY_IRQ_TIMEOUT;
103			dev_info(dev, "TPM ready IRQ confirmed on attempt %u\n",
104				 attempt);
105		} else if (attempt > MAX_IRQ_CONFIRMATION_ATTEMPTS) {
106			phy->irq_needs_confirmation = false;
107			dev_warn(dev, "IRQ not confirmed - will use delays\n");
108		}
109	}
110}
111
112/*
113 * Cr50 might go to sleep if there is no SPI activity for some time and
114 * miss the first few bits/bytes on the bus. In such case, wake it up
115 * by asserting CS and give it time to start up.
116 */
117static bool cr50_needs_waking(struct cr50_spi_phy *phy)
118{
119	/*
120	 * Note: There is a small chance, if Cr50 is not accessed in a few days,
121	 * that time_in_range will not provide the correct result after the wrap
122	 * around for jiffies. In this case, we'll probably timeout or read
123	 * incorrect value from TPM_STS and just retry the operation.
124	 */
125	return !time_in_range_open(jiffies, phy->last_access,
126				   phy->spi_phy.wake_after);
127}
128
129static void cr50_wake_if_needed(struct cr50_spi_phy *cr50_phy)
130{
131	struct tpm_tis_spi_phy *phy = &cr50_phy->spi_phy;
132
133	if (cr50_needs_waking(cr50_phy)) {
134		/* Assert CS, wait 1 msec, deassert CS */
135		struct spi_transfer spi_cs_wake = {
136			.delay = {
137				.value = 1000,
138				.unit = SPI_DELAY_UNIT_USECS
139			}
140		};
141
142		spi_sync_transfer(phy->spi_device, &spi_cs_wake, 1);
143		/* Wait for it to fully wake */
144		usleep_range(CR50_WAKE_START_DELAY_USEC,
145			     CR50_WAKE_START_DELAY_USEC * 2);
146	}
147
148	/* Reset the time when we need to wake Cr50 again */
149	phy->wake_after = jiffies + msecs_to_jiffies(CR50_SLEEP_DELAY_MSEC);
150}
151
152/*
153 * Flow control: clock the bus and wait for cr50 to set LSB before
154 * sending/receiving data. TCG PTP spec allows it to happen during
155 * the last byte of header, but cr50 never does that in practice,
156 * and earlier versions had a bug when it was set too early, so don't
157 * check for it during header transfer.
158 */
159static int cr50_spi_flow_control(struct tpm_tis_spi_phy *phy,
160				 struct spi_transfer *spi_xfer)
161{
162	struct device *dev = &phy->spi_device->dev;
163	unsigned long timeout = jiffies + CR50_FLOW_CONTROL;
164	struct spi_message m;
165	int ret;
166
167	spi_xfer->len = 1;
168
169	do {
170		spi_message_init(&m);
171		spi_message_add_tail(spi_xfer, &m);
172		ret = spi_sync_locked(phy->spi_device, &m);
173		if (ret < 0)
174			return ret;
175
176		if (time_after(jiffies, timeout)) {
177			dev_warn(dev, "Timeout during flow control\n");
178			return -EBUSY;
179		}
180	} while (!(phy->iobuf[0] & 0x01));
181
182	return 0;
183}
184
185static int tpm_tis_spi_cr50_transfer(struct tpm_tis_data *data, u32 addr, u16 len,
186				     u8 *in, const u8 *out)
187{
188	struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data);
189	struct cr50_spi_phy *cr50_phy = to_cr50_spi_phy(phy);
190	int ret;
191
192	mutex_lock(&cr50_phy->time_track_mutex);
193	/*
194	 * Do this outside of spi_bus_lock in case cr50 is not the
195	 * only device on that spi bus.
196	 */
197	cr50_ensure_access_delay(cr50_phy);
198	cr50_wake_if_needed(cr50_phy);
199
200	ret = tpm_tis_spi_transfer(data, addr, len, in, out);
201
202	cr50_phy->last_access = jiffies;
203	mutex_unlock(&cr50_phy->time_track_mutex);
204
205	return ret;
206}
207
208static int tpm_tis_spi_cr50_read_bytes(struct tpm_tis_data *data, u32 addr,
209				       u16 len, u8 *result)
210{
211	return tpm_tis_spi_cr50_transfer(data, addr, len, result, NULL);
212}
213
214static int tpm_tis_spi_cr50_write_bytes(struct tpm_tis_data *data, u32 addr,
215					u16 len, const u8 *value)
216{
217	return tpm_tis_spi_cr50_transfer(data, addr, len, NULL, value);
218}
219
220static const struct tpm_tis_phy_ops tpm_spi_cr50_phy_ops = {
221	.read_bytes = tpm_tis_spi_cr50_read_bytes,
222	.write_bytes = tpm_tis_spi_cr50_write_bytes,
223	.read16 = tpm_tis_spi_read16,
224	.read32 = tpm_tis_spi_read32,
225	.write32 = tpm_tis_spi_write32,
226};
227
228static void cr50_print_fw_version(struct tpm_tis_data *data)
229{
230	struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data);
231	int i, len = 0;
232	char fw_ver[TPM_CR50_MAX_FW_VER_LEN + 1];
233	char fw_ver_block[4];
234
235	/*
236	 * Write anything to TPM_CR50_FW_VER to start from the beginning
237	 * of the version string
238	 */
239	tpm_tis_write8(data, TPM_CR50_FW_VER(data->locality), 0);
240
241	/* Read the string, 4 bytes at a time, until we get '\0' */
242	do {
243		tpm_tis_read_bytes(data, TPM_CR50_FW_VER(data->locality), 4,
244				   fw_ver_block);
245		for (i = 0; i < 4 && fw_ver_block[i]; ++len, ++i)
246			fw_ver[len] = fw_ver_block[i];
247	} while (i == 4 && len < TPM_CR50_MAX_FW_VER_LEN);
248	fw_ver[len] = '\0';
249
250	dev_info(&phy->spi_device->dev, "Cr50 firmware version: %s\n", fw_ver);
251}
252
253int cr50_spi_probe(struct spi_device *spi)
254{
255	struct tpm_tis_spi_phy *phy;
256	struct cr50_spi_phy *cr50_phy;
257	int ret;
258	struct tpm_chip *chip;
259
260	cr50_phy = devm_kzalloc(&spi->dev, sizeof(*cr50_phy), GFP_KERNEL);
261	if (!cr50_phy)
262		return -ENOMEM;
263
264	phy = &cr50_phy->spi_phy;
265	phy->flow_control = cr50_spi_flow_control;
266	phy->wake_after = jiffies;
267	init_completion(&phy->ready);
268
269	cr50_phy->access_delay = CR50_NOIRQ_ACCESS_DELAY;
270	cr50_phy->last_access = jiffies;
271	mutex_init(&cr50_phy->time_track_mutex);
272
273	if (spi->irq > 0) {
274		ret = devm_request_irq(&spi->dev, spi->irq,
275				       cr50_spi_irq_handler,
276				       IRQF_TRIGGER_RISING | IRQF_ONESHOT,
277				       "cr50_spi", cr50_phy);
278		if (ret < 0) {
279			if (ret == -EPROBE_DEFER)
280				return ret;
281			dev_warn(&spi->dev, "Requesting IRQ %d failed: %d\n",
282				 spi->irq, ret);
283			/*
284			 * This is not fatal, the driver will fall back to
285			 * delays automatically, since ready will never
286			 * be completed without a registered irq handler.
287			 * So, just fall through.
288			 */
289		} else {
290			/*
291			 * IRQ requested, let's verify that it is actually
292			 * triggered, before relying on it.
293			 */
294			cr50_phy->irq_needs_confirmation = true;
295		}
296	} else {
297		dev_warn(&spi->dev,
298			 "No IRQ - will use delays between transactions.\n");
299	}
300
301	ret = tpm_tis_spi_init(spi, phy, -1, &tpm_spi_cr50_phy_ops);
302	if (ret)
303		return ret;
304
305	cr50_print_fw_version(&phy->priv);
306
307	chip = dev_get_drvdata(&spi->dev);
308	chip->flags |= TPM_CHIP_FLAG_FIRMWARE_POWER_MANAGED;
309
310	return 0;
311}
312
313#ifdef CONFIG_PM_SLEEP
314int tpm_tis_spi_resume(struct device *dev)
315{
316	struct tpm_chip *chip = dev_get_drvdata(dev);
317	struct tpm_tis_data *data = dev_get_drvdata(&chip->dev);
318	struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data);
319	/*
320	 * Jiffies not increased during suspend, so we need to reset
321	 * the time to wake Cr50 after resume.
322	 */
323	phy->wake_after = jiffies;
324
325	return tpm_tis_resume(dev);
326}
327#endif
328