1// SPDX-License-Identifier: GPL-2.0 2// 3// Register cache access API 4// 5// Copyright 2011 Wolfson Microelectronics plc 6// 7// Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> 8 9#include <linux/bsearch.h> 10#include <linux/device.h> 11#include <linux/export.h> 12#include <linux/slab.h> 13#include <linux/sort.h> 14 15#include "trace.h" 16#include "internal.h" 17 18static const struct regcache_ops *cache_types[] = { 19 ®cache_rbtree_ops, 20#if IS_ENABLED(CONFIG_REGCACHE_COMPRESSED) 21 ®cache_lzo_ops, 22#endif 23 ®cache_flat_ops, 24}; 25 26static int regcache_hw_init(struct regmap *map) 27{ 28 int i, j; 29 int ret; 30 int count; 31 unsigned int reg, val; 32 void *tmp_buf; 33 34 if (!map->num_reg_defaults_raw) 35 return -EINVAL; 36 37 /* calculate the size of reg_defaults */ 38 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++) 39 if (regmap_readable(map, i * map->reg_stride) && 40 !regmap_volatile(map, i * map->reg_stride)) 41 count++; 42 43 /* all registers are unreadable or volatile, so just bypass */ 44 if (!count) { 45 map->cache_bypass = true; 46 return 0; 47 } 48 49 map->num_reg_defaults = count; 50 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default), 51 GFP_KERNEL); 52 if (!map->reg_defaults) 53 return -ENOMEM; 54 55 if (!map->reg_defaults_raw) { 56 bool cache_bypass = map->cache_bypass; 57 dev_warn(map->dev, "No cache defaults, reading back from HW\n"); 58 59 /* Bypass the cache access till data read from HW */ 60 map->cache_bypass = true; 61 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL); 62 if (!tmp_buf) { 63 ret = -ENOMEM; 64 goto err_free; 65 } 66 ret = regmap_raw_read(map, 0, tmp_buf, 67 map->cache_size_raw); 68 map->cache_bypass = cache_bypass; 69 if (ret == 0) { 70 map->reg_defaults_raw = tmp_buf; 71 map->cache_free = 1; 72 } else { 73 kfree(tmp_buf); 74 } 75 } 76 77 /* fill the reg_defaults */ 78 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) { 79 reg = i * map->reg_stride; 80 81 if (!regmap_readable(map, reg)) 82 continue; 83 84 if (regmap_volatile(map, reg)) 85 continue; 86 87 if (map->reg_defaults_raw) { 88 val = regcache_get_val(map, map->reg_defaults_raw, i); 89 } else { 90 bool cache_bypass = map->cache_bypass; 91 92 map->cache_bypass = true; 93 ret = regmap_read(map, reg, &val); 94 map->cache_bypass = cache_bypass; 95 if (ret != 0) { 96 dev_err(map->dev, "Failed to read %d: %d\n", 97 reg, ret); 98 goto err_free; 99 } 100 } 101 102 map->reg_defaults[j].reg = reg; 103 map->reg_defaults[j].def = val; 104 j++; 105 } 106 107 return 0; 108 109err_free: 110 kfree(map->reg_defaults); 111 112 return ret; 113} 114 115int regcache_init(struct regmap *map, const struct regmap_config *config) 116{ 117 int ret; 118 int i; 119 void *tmp_buf; 120 121 if (map->cache_type == REGCACHE_NONE) { 122 if (config->reg_defaults || config->num_reg_defaults_raw) 123 dev_warn(map->dev, 124 "No cache used with register defaults set!\n"); 125 126 map->cache_bypass = true; 127 return 0; 128 } 129 130 if (config->reg_defaults && !config->num_reg_defaults) { 131 dev_err(map->dev, 132 "Register defaults are set without the number!\n"); 133 return -EINVAL; 134 } 135 136 for (i = 0; i < config->num_reg_defaults; i++) 137 if (config->reg_defaults[i].reg % map->reg_stride) 138 return -EINVAL; 139 140 for (i = 0; i < ARRAY_SIZE(cache_types); i++) 141 if (cache_types[i]->type == map->cache_type) 142 break; 143 144 if (i == ARRAY_SIZE(cache_types)) { 145 dev_err(map->dev, "Could not match compress type: %d\n", 146 map->cache_type); 147 return -EINVAL; 148 } 149 150 map->num_reg_defaults = config->num_reg_defaults; 151 map->num_reg_defaults_raw = config->num_reg_defaults_raw; 152 map->reg_defaults_raw = config->reg_defaults_raw; 153 map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8); 154 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw; 155 156 map->cache = NULL; 157 map->cache_ops = cache_types[i]; 158 159 if (!map->cache_ops->read || 160 !map->cache_ops->write || 161 !map->cache_ops->name) 162 return -EINVAL; 163 164 /* We still need to ensure that the reg_defaults 165 * won't vanish from under us. We'll need to make 166 * a copy of it. 167 */ 168 if (config->reg_defaults) { 169 tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults * 170 sizeof(struct reg_default), GFP_KERNEL); 171 if (!tmp_buf) 172 return -ENOMEM; 173 map->reg_defaults = tmp_buf; 174 } else if (map->num_reg_defaults_raw) { 175 /* Some devices such as PMICs don't have cache defaults, 176 * we cope with this by reading back the HW registers and 177 * crafting the cache defaults by hand. 178 */ 179 ret = regcache_hw_init(map); 180 if (ret < 0) 181 return ret; 182 if (map->cache_bypass) 183 return 0; 184 } 185 186 if (!map->max_register) 187 map->max_register = map->num_reg_defaults_raw; 188 189 if (map->cache_ops->init) { 190 dev_dbg(map->dev, "Initializing %s cache\n", 191 map->cache_ops->name); 192 ret = map->cache_ops->init(map); 193 if (ret) 194 goto err_free; 195 } 196 return 0; 197 198err_free: 199 kfree(map->reg_defaults); 200 if (map->cache_free) 201 kfree(map->reg_defaults_raw); 202 203 return ret; 204} 205 206void regcache_exit(struct regmap *map) 207{ 208 if (map->cache_type == REGCACHE_NONE) 209 return; 210 211 BUG_ON(!map->cache_ops); 212 213 kfree(map->reg_defaults); 214 if (map->cache_free) 215 kfree(map->reg_defaults_raw); 216 217 if (map->cache_ops->exit) { 218 dev_dbg(map->dev, "Destroying %s cache\n", 219 map->cache_ops->name); 220 map->cache_ops->exit(map); 221 } 222} 223 224/** 225 * regcache_read - Fetch the value of a given register from the cache. 226 * 227 * @map: map to configure. 228 * @reg: The register index. 229 * @value: The value to be returned. 230 * 231 * Return a negative value on failure, 0 on success. 232 */ 233int regcache_read(struct regmap *map, 234 unsigned int reg, unsigned int *value) 235{ 236 int ret; 237 238 if (map->cache_type == REGCACHE_NONE) 239 return -ENOSYS; 240 241 BUG_ON(!map->cache_ops); 242 243 if (!regmap_volatile(map, reg)) { 244 ret = map->cache_ops->read(map, reg, value); 245 246 if (ret == 0) 247 trace_regmap_reg_read_cache(map, reg, *value); 248 249 return ret; 250 } 251 252 return -EINVAL; 253} 254 255/** 256 * regcache_write - Set the value of a given register in the cache. 257 * 258 * @map: map to configure. 259 * @reg: The register index. 260 * @value: The new register value. 261 * 262 * Return a negative value on failure, 0 on success. 263 */ 264int regcache_write(struct regmap *map, 265 unsigned int reg, unsigned int value) 266{ 267 if (map->cache_type == REGCACHE_NONE) 268 return 0; 269 270 BUG_ON(!map->cache_ops); 271 272 if (!regmap_volatile(map, reg)) 273 return map->cache_ops->write(map, reg, value); 274 275 return 0; 276} 277 278static bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg, 279 unsigned int val) 280{ 281 int ret; 282 283 /* If we don't know the chip just got reset, then sync everything. */ 284 if (!map->no_sync_defaults) 285 return true; 286 287 /* Is this the hardware default? If so skip. */ 288 ret = regcache_lookup_reg(map, reg); 289 if (ret >= 0 && val == map->reg_defaults[ret].def) 290 return false; 291 return true; 292} 293 294static int regcache_default_sync(struct regmap *map, unsigned int min, 295 unsigned int max) 296{ 297 unsigned int reg; 298 299 for (reg = min; reg <= max; reg += map->reg_stride) { 300 unsigned int val; 301 int ret; 302 303 if (regmap_volatile(map, reg) || 304 !regmap_writeable(map, reg)) 305 continue; 306 307 ret = regcache_read(map, reg, &val); 308 if (ret) 309 return ret; 310 311 if (!regcache_reg_needs_sync(map, reg, val)) 312 continue; 313 314 map->cache_bypass = true; 315 ret = _regmap_write(map, reg, val); 316 map->cache_bypass = false; 317 if (ret) { 318 dev_err(map->dev, "Unable to sync register %#x. %d\n", 319 reg, ret); 320 return ret; 321 } 322 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val); 323 } 324 325 return 0; 326} 327 328/** 329 * regcache_sync - Sync the register cache with the hardware. 330 * 331 * @map: map to configure. 332 * 333 * Any registers that should not be synced should be marked as 334 * volatile. In general drivers can choose not to use the provided 335 * syncing functionality if they so require. 336 * 337 * Return a negative value on failure, 0 on success. 338 */ 339int regcache_sync(struct regmap *map) 340{ 341 int ret = 0; 342 unsigned int i; 343 const char *name; 344 bool bypass; 345 346 if (WARN_ON(map->cache_type == REGCACHE_NONE)) 347 return -EINVAL; 348 349 BUG_ON(!map->cache_ops); 350 351 map->lock(map->lock_arg); 352 /* Remember the initial bypass state */ 353 bypass = map->cache_bypass; 354 dev_dbg(map->dev, "Syncing %s cache\n", 355 map->cache_ops->name); 356 name = map->cache_ops->name; 357 trace_regcache_sync(map, name, "start"); 358 359 if (!map->cache_dirty) 360 goto out; 361 362 map->async = true; 363 364 /* Apply any patch first */ 365 map->cache_bypass = true; 366 for (i = 0; i < map->patch_regs; i++) { 367 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def); 368 if (ret != 0) { 369 dev_err(map->dev, "Failed to write %x = %x: %d\n", 370 map->patch[i].reg, map->patch[i].def, ret); 371 goto out; 372 } 373 } 374 map->cache_bypass = false; 375 376 if (map->cache_ops->sync) 377 ret = map->cache_ops->sync(map, 0, map->max_register); 378 else 379 ret = regcache_default_sync(map, 0, map->max_register); 380 381 if (ret == 0) 382 map->cache_dirty = false; 383 384out: 385 /* Restore the bypass state */ 386 map->async = false; 387 map->cache_bypass = bypass; 388 map->no_sync_defaults = false; 389 map->unlock(map->lock_arg); 390 391 regmap_async_complete(map); 392 393 trace_regcache_sync(map, name, "stop"); 394 395 return ret; 396} 397EXPORT_SYMBOL_GPL(regcache_sync); 398 399/** 400 * regcache_sync_region - Sync part of the register cache with the hardware. 401 * 402 * @map: map to sync. 403 * @min: first register to sync 404 * @max: last register to sync 405 * 406 * Write all non-default register values in the specified region to 407 * the hardware. 408 * 409 * Return a negative value on failure, 0 on success. 410 */ 411int regcache_sync_region(struct regmap *map, unsigned int min, 412 unsigned int max) 413{ 414 int ret = 0; 415 const char *name; 416 bool bypass; 417 418 if (WARN_ON(map->cache_type == REGCACHE_NONE)) 419 return -EINVAL; 420 421 BUG_ON(!map->cache_ops); 422 423 map->lock(map->lock_arg); 424 425 /* Remember the initial bypass state */ 426 bypass = map->cache_bypass; 427 428 name = map->cache_ops->name; 429 dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max); 430 431 trace_regcache_sync(map, name, "start region"); 432 433 if (!map->cache_dirty) 434 goto out; 435 436 map->async = true; 437 438 if (map->cache_ops->sync) 439 ret = map->cache_ops->sync(map, min, max); 440 else 441 ret = regcache_default_sync(map, min, max); 442 443out: 444 /* Restore the bypass state */ 445 map->cache_bypass = bypass; 446 map->async = false; 447 map->no_sync_defaults = false; 448 map->unlock(map->lock_arg); 449 450 regmap_async_complete(map); 451 452 trace_regcache_sync(map, name, "stop region"); 453 454 return ret; 455} 456EXPORT_SYMBOL_GPL(regcache_sync_region); 457 458/** 459 * regcache_drop_region - Discard part of the register cache 460 * 461 * @map: map to operate on 462 * @min: first register to discard 463 * @max: last register to discard 464 * 465 * Discard part of the register cache. 466 * 467 * Return a negative value on failure, 0 on success. 468 */ 469int regcache_drop_region(struct regmap *map, unsigned int min, 470 unsigned int max) 471{ 472 int ret = 0; 473 474 if (!map->cache_ops || !map->cache_ops->drop) 475 return -EINVAL; 476 477 map->lock(map->lock_arg); 478 479 trace_regcache_drop_region(map, min, max); 480 481 ret = map->cache_ops->drop(map, min, max); 482 483 map->unlock(map->lock_arg); 484 485 return ret; 486} 487EXPORT_SYMBOL_GPL(regcache_drop_region); 488 489/** 490 * regcache_cache_only - Put a register map into cache only mode 491 * 492 * @map: map to configure 493 * @enable: flag if changes should be written to the hardware 494 * 495 * When a register map is marked as cache only writes to the register 496 * map API will only update the register cache, they will not cause 497 * any hardware changes. This is useful for allowing portions of 498 * drivers to act as though the device were functioning as normal when 499 * it is disabled for power saving reasons. 500 */ 501void regcache_cache_only(struct regmap *map, bool enable) 502{ 503 map->lock(map->lock_arg); 504 WARN_ON(map->cache_bypass && enable); 505 map->cache_only = enable; 506 trace_regmap_cache_only(map, enable); 507 map->unlock(map->lock_arg); 508} 509EXPORT_SYMBOL_GPL(regcache_cache_only); 510 511/** 512 * regcache_mark_dirty - Indicate that HW registers were reset to default values 513 * 514 * @map: map to mark 515 * 516 * Inform regcache that the device has been powered down or reset, so that 517 * on resume, regcache_sync() knows to write out all non-default values 518 * stored in the cache. 519 * 520 * If this function is not called, regcache_sync() will assume that 521 * the hardware state still matches the cache state, modulo any writes that 522 * happened when cache_only was true. 523 */ 524void regcache_mark_dirty(struct regmap *map) 525{ 526 map->lock(map->lock_arg); 527 map->cache_dirty = true; 528 map->no_sync_defaults = true; 529 map->unlock(map->lock_arg); 530} 531EXPORT_SYMBOL_GPL(regcache_mark_dirty); 532 533/** 534 * regcache_cache_bypass - Put a register map into cache bypass mode 535 * 536 * @map: map to configure 537 * @enable: flag if changes should not be written to the cache 538 * 539 * When a register map is marked with the cache bypass option, writes 540 * to the register map API will only update the hardware and not the 541 * the cache directly. This is useful when syncing the cache back to 542 * the hardware. 543 */ 544void regcache_cache_bypass(struct regmap *map, bool enable) 545{ 546 map->lock(map->lock_arg); 547 WARN_ON(map->cache_only && enable); 548 map->cache_bypass = enable; 549 trace_regmap_cache_bypass(map, enable); 550 map->unlock(map->lock_arg); 551} 552EXPORT_SYMBOL_GPL(regcache_cache_bypass); 553 554bool regcache_set_val(struct regmap *map, void *base, unsigned int idx, 555 unsigned int val) 556{ 557 if (regcache_get_val(map, base, idx) == val) 558 return true; 559 560 /* Use device native format if possible */ 561 if (map->format.format_val) { 562 map->format.format_val(base + (map->cache_word_size * idx), 563 val, 0); 564 return false; 565 } 566 567 switch (map->cache_word_size) { 568 case 1: { 569 u8 *cache = base; 570 571 cache[idx] = val; 572 break; 573 } 574 case 2: { 575 u16 *cache = base; 576 577 cache[idx] = val; 578 break; 579 } 580 case 4: { 581 u32 *cache = base; 582 583 cache[idx] = val; 584 break; 585 } 586#ifdef CONFIG_64BIT 587 case 8: { 588 u64 *cache = base; 589 590 cache[idx] = val; 591 break; 592 } 593#endif 594 default: 595 BUG(); 596 } 597 return false; 598} 599 600unsigned int regcache_get_val(struct regmap *map, const void *base, 601 unsigned int idx) 602{ 603 if (!base) 604 return -EINVAL; 605 606 /* Use device native format if possible */ 607 if (map->format.parse_val) 608 return map->format.parse_val(regcache_get_val_addr(map, base, 609 idx)); 610 611 switch (map->cache_word_size) { 612 case 1: { 613 const u8 *cache = base; 614 615 return cache[idx]; 616 } 617 case 2: { 618 const u16 *cache = base; 619 620 return cache[idx]; 621 } 622 case 4: { 623 const u32 *cache = base; 624 625 return cache[idx]; 626 } 627#ifdef CONFIG_64BIT 628 case 8: { 629 const u64 *cache = base; 630 631 return cache[idx]; 632 } 633#endif 634 default: 635 BUG(); 636 } 637 /* unreachable */ 638 return -1; 639} 640 641static int regcache_default_cmp(const void *a, const void *b) 642{ 643 const struct reg_default *_a = a; 644 const struct reg_default *_b = b; 645 646 return _a->reg - _b->reg; 647} 648 649int regcache_lookup_reg(struct regmap *map, unsigned int reg) 650{ 651 struct reg_default key; 652 struct reg_default *r; 653 654 key.reg = reg; 655 key.def = 0; 656 657 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults, 658 sizeof(struct reg_default), regcache_default_cmp); 659 660 if (r) 661 return r - map->reg_defaults; 662 else 663 return -ENOENT; 664} 665 666static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx) 667{ 668 if (!cache_present) 669 return true; 670 671 return test_bit(idx, cache_present); 672} 673 674static int regcache_sync_block_single(struct regmap *map, void *block, 675 unsigned long *cache_present, 676 unsigned int block_base, 677 unsigned int start, unsigned int end) 678{ 679 unsigned int i, regtmp, val; 680 int ret; 681 682 for (i = start; i < end; i++) { 683 regtmp = block_base + (i * map->reg_stride); 684 685 if (!regcache_reg_present(cache_present, i) || 686 !regmap_writeable(map, regtmp)) 687 continue; 688 689 val = regcache_get_val(map, block, i); 690 if (!regcache_reg_needs_sync(map, regtmp, val)) 691 continue; 692 693 map->cache_bypass = true; 694 695 ret = _regmap_write(map, regtmp, val); 696 697 map->cache_bypass = false; 698 if (ret != 0) { 699 dev_err(map->dev, "Unable to sync register %#x. %d\n", 700 regtmp, ret); 701 return ret; 702 } 703 dev_dbg(map->dev, "Synced register %#x, value %#x\n", 704 regtmp, val); 705 } 706 707 return 0; 708} 709 710static int regcache_sync_block_raw_flush(struct regmap *map, const void **data, 711 unsigned int base, unsigned int cur) 712{ 713 size_t val_bytes = map->format.val_bytes; 714 int ret, count; 715 716 if (*data == NULL) 717 return 0; 718 719 count = (cur - base) / map->reg_stride; 720 721 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n", 722 count * val_bytes, count, base, cur - map->reg_stride); 723 724 map->cache_bypass = true; 725 726 ret = _regmap_raw_write(map, base, *data, count * val_bytes, false); 727 if (ret) 728 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n", 729 base, cur - map->reg_stride, ret); 730 731 map->cache_bypass = false; 732 733 *data = NULL; 734 735 return ret; 736} 737 738static int regcache_sync_block_raw(struct regmap *map, void *block, 739 unsigned long *cache_present, 740 unsigned int block_base, unsigned int start, 741 unsigned int end) 742{ 743 unsigned int i, val; 744 unsigned int regtmp = 0; 745 unsigned int base = 0; 746 const void *data = NULL; 747 int ret; 748 749 for (i = start; i < end; i++) { 750 regtmp = block_base + (i * map->reg_stride); 751 752 if (!regcache_reg_present(cache_present, i) || 753 !regmap_writeable(map, regtmp)) { 754 ret = regcache_sync_block_raw_flush(map, &data, 755 base, regtmp); 756 if (ret != 0) 757 return ret; 758 continue; 759 } 760 761 val = regcache_get_val(map, block, i); 762 if (!regcache_reg_needs_sync(map, regtmp, val)) { 763 ret = regcache_sync_block_raw_flush(map, &data, 764 base, regtmp); 765 if (ret != 0) 766 return ret; 767 continue; 768 } 769 770 if (!data) { 771 data = regcache_get_val_addr(map, block, i); 772 base = regtmp; 773 } 774 } 775 776 return regcache_sync_block_raw_flush(map, &data, base, regtmp + 777 map->reg_stride); 778} 779 780int regcache_sync_block(struct regmap *map, void *block, 781 unsigned long *cache_present, 782 unsigned int block_base, unsigned int start, 783 unsigned int end) 784{ 785 if (regmap_can_raw_write(map) && !map->use_single_write) 786 return regcache_sync_block_raw(map, block, cache_present, 787 block_base, start, end); 788 else 789 return regcache_sync_block_single(map, block, cache_present, 790 block_base, start, end); 791} 792