1/* SPDX-License-Identifier: GPL-2.0 */ 2/* drivers/atm/zatm.h - ZeitNet ZN122x device driver declarations */ 3 4/* Written 1995-1998 by Werner Almesberger, EPFL LRC/ICA */ 5 6 7#ifndef DRIVER_ATM_ZATM_H 8#define DRIVER_ATM_ZATM_H 9 10#include <linux/skbuff.h> 11#include <linux/atm.h> 12#include <linux/atmdev.h> 13#include <linux/sonet.h> 14#include <linux/pci.h> 15 16 17#define DEV_LABEL "zatm" 18 19#define MAX_AAL5_PDU 10240 /* allocate for AAL5 PDUs of this size */ 20#define MAX_RX_SIZE_LD 14 /* ceil(log2((MAX_AAL5_PDU+47)/48)) */ 21 22#define LOW_MARK 12 /* start adding new buffers if less than 12 */ 23#define HIGH_MARK 30 /* stop adding buffers after reaching 30 */ 24#define OFF_CNG_THRES 5 /* threshold for offset changes */ 25 26#define RX_SIZE 2 /* RX lookup entry size (in bytes) */ 27#define NR_POOLS 32 /* number of free buffer pointers */ 28#define POOL_SIZE 8 /* buffer entry size (in bytes) */ 29#define NR_SHAPERS 16 /* number of shapers */ 30#define SHAPER_SIZE 4 /* shaper entry size (in bytes) */ 31#define VC_SIZE 32 /* VC dsc (TX or RX) size (in bytes) */ 32 33#define RING_ENTRIES 32 /* ring entries (without back pointer) */ 34#define RING_WORDS 4 /* ring element size */ 35#define RING_SIZE (sizeof(unsigned long)*(RING_ENTRIES+1)*RING_WORDS) 36 37#define NR_MBX 4 /* four mailboxes */ 38#define MBX_RX_0 0 /* mailbox indices */ 39#define MBX_RX_1 1 40#define MBX_TX_0 2 41#define MBX_TX_1 3 42 43struct zatm_vcc { 44 /*-------------------------------- RX part */ 45 int rx_chan; /* RX channel, 0 if none */ 46 int pool; /* free buffer pool */ 47 /*-------------------------------- TX part */ 48 int tx_chan; /* TX channel, 0 if none */ 49 int shaper; /* shaper, <0 if none */ 50 struct sk_buff_head tx_queue; /* list of buffers in transit */ 51 wait_queue_head_t tx_wait; /* for close */ 52 u32 *ring; /* transmit ring */ 53 int ring_curr; /* current write position */ 54 int txing; /* number of transmits in progress */ 55 struct sk_buff_head backlog; /* list of buffers waiting for ring */ 56}; 57 58struct zatm_dev { 59 /*-------------------------------- TX part */ 60 int tx_bw; /* remaining bandwidth */ 61 u32 free_shapers; /* bit set */ 62 int ubr; /* UBR shaper; -1 if none */ 63 int ubr_ref_cnt; /* number of VCs using UBR shaper */ 64 /*-------------------------------- RX part */ 65 int pool_ref[NR_POOLS]; /* free buffer pool usage counters */ 66 volatile struct sk_buff *last_free[NR_POOLS]; 67 /* last entry in respective pool */ 68 struct sk_buff_head pool[NR_POOLS];/* free buffer pools */ 69 struct zatm_pool_info pool_info[NR_POOLS]; /* pool information */ 70 /*-------------------------------- maps */ 71 struct atm_vcc **tx_map; /* TX VCCs */ 72 struct atm_vcc **rx_map; /* RX VCCs */ 73 int chans; /* map size, must be 2^n */ 74 /*-------------------------------- mailboxes */ 75 unsigned long mbx_start[NR_MBX];/* start addresses */ 76 dma_addr_t mbx_dma[NR_MBX]; 77 u16 mbx_end[NR_MBX]; /* end offset (in bytes) */ 78 /*-------------------------------- other pointers */ 79 u32 pool_base; /* Free buffer pool dsc (word addr) */ 80 /*-------------------------------- ZATM links */ 81 struct atm_dev *more; /* other ZATM devices */ 82 /*-------------------------------- general information */ 83 int mem; /* RAM on board (in bytes) */ 84 int khz; /* timer clock */ 85 int copper; /* PHY type */ 86 unsigned char irq; /* IRQ */ 87 unsigned int base; /* IO base address */ 88 struct pci_dev *pci_dev; /* PCI stuff */ 89 spinlock_t lock; 90}; 91 92 93#define ZATM_DEV(d) ((struct zatm_dev *) (d)->dev_data) 94#define ZATM_VCC(d) ((struct zatm_vcc *) (d)->dev_data) 95 96 97struct zatm_skb_prv { 98 struct atm_skb_data _; /* reserved */ 99 u32 *dsc; /* pointer to skb's descriptor */ 100}; 101 102#define ZATM_PRV_DSC(skb) (((struct zatm_skb_prv *) (skb)->cb)->dsc) 103 104#endif 105