1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *	IDE tuning and bus mastering support for the CS5510/CS5520
4 *	chipsets
5 *
6 *	The CS5510/CS5520 are slightly unusual devices. Unlike the
7 *	typical IDE controllers they do bus mastering with the drive in
8 *	PIO mode and smarter silicon.
9 *
10 *	The practical upshot of this is that we must always tune the
11 *	drive for the right PIO mode. We must also ignore all the blacklists
12 *	and the drive bus mastering DMA information. Also to confuse matters
13 *	further we can do DMA on PIO only drives.
14 *
15 *	DMA on the 5510 also requires we disable_hlt() during DMA on early
16 *	revisions.
17 *
18 *	*** This driver is strictly experimental ***
19 *
20 *	(c) Copyright Red Hat Inc 2002
21 *
22 * Documentation:
23 *	Not publicly available.
24 */
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/blkdev.h>
29#include <linux/delay.h>
30#include <scsi/scsi_host.h>
31#include <linux/libata.h>
32
33#define DRV_NAME	"pata_cs5520"
34#define DRV_VERSION	"0.6.6"
35
36struct pio_clocks
37{
38	int address;
39	int assert;
40	int recovery;
41};
42
43static const struct pio_clocks cs5520_pio_clocks[]={
44	{3, 6, 11},
45	{2, 5, 6},
46	{1, 4, 3},
47	{1, 3, 2},
48	{1, 2, 1}
49};
50
51/**
52 *	cs5520_set_timings	-	program PIO timings
53 *	@ap: ATA port
54 *	@adev: ATA device
55 *
56 *	Program the PIO mode timings for the controller according to the pio
57 *	clocking table.
58 */
59
60static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int pio)
61{
62	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
63	int slave = adev->devno;
64
65	pio -= XFER_PIO_0;
66
67	/* Channel command timing */
68	pci_write_config_byte(pdev, 0x62 + ap->port_no,
69				(cs5520_pio_clocks[pio].recovery << 4) |
70				(cs5520_pio_clocks[pio].assert));
71	/* FIXME: should these use address ? */
72	/* Read command timing */
73	pci_write_config_byte(pdev, 0x64 +  4*ap->port_no + slave,
74				(cs5520_pio_clocks[pio].recovery << 4) |
75				(cs5520_pio_clocks[pio].assert));
76	/* Write command timing */
77	pci_write_config_byte(pdev, 0x66 +  4*ap->port_no + slave,
78				(cs5520_pio_clocks[pio].recovery << 4) |
79				(cs5520_pio_clocks[pio].assert));
80}
81
82/**
83 *	cs5520_set_piomode	-	program PIO timings
84 *	@ap: ATA port
85 *	@adev: ATA device
86 *
87 *	Program the PIO mode timings for the controller according to the pio
88 *	clocking table.
89 */
90
91static void cs5520_set_piomode(struct ata_port *ap, struct ata_device *adev)
92{
93	cs5520_set_timings(ap, adev, adev->pio_mode);
94}
95
96static struct scsi_host_template cs5520_sht = {
97	ATA_BMDMA_SHT(DRV_NAME),
98	.sg_tablesize		= LIBATA_DUMB_MAX_PRD,
99};
100
101static struct ata_port_operations cs5520_port_ops = {
102	.inherits		= &ata_bmdma_port_ops,
103	.qc_prep		= ata_bmdma_dumb_qc_prep,
104	.cable_detect		= ata_cable_40wire,
105	.set_piomode		= cs5520_set_piomode,
106};
107
108static int cs5520_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
109{
110	static const unsigned int cmd_port[] = { 0x1F0, 0x170 };
111	static const unsigned int ctl_port[] = { 0x3F6, 0x376 };
112	struct ata_port_info pi = {
113		.flags		= ATA_FLAG_SLAVE_POSS,
114		.pio_mask	= ATA_PIO4,
115		.port_ops	= &cs5520_port_ops,
116	};
117	const struct ata_port_info *ppi[2];
118	u8 pcicfg;
119	void __iomem *iomap[5];
120	struct ata_host *host;
121	struct ata_ioports *ioaddr;
122	int i, rc;
123
124	rc = pcim_enable_device(pdev);
125	if (rc)
126		return rc;
127
128	/* IDE port enable bits */
129	pci_read_config_byte(pdev, 0x60, &pcicfg);
130
131	/* Check if the ATA ports are enabled */
132	if ((pcicfg & 3) == 0)
133		return -ENODEV;
134
135	ppi[0] = ppi[1] = &ata_dummy_port_info;
136	if (pcicfg & 1)
137		ppi[0] = &pi;
138	if (pcicfg & 2)
139		ppi[1] = &pi;
140
141	if ((pcicfg & 0x40) == 0) {
142		dev_warn(&pdev->dev, "DMA mode disabled. Enabling.\n");
143		pci_write_config_byte(pdev, 0x60, pcicfg | 0x40);
144	}
145
146	pi.mwdma_mask = id->driver_data;
147
148	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
149	if (!host)
150		return -ENOMEM;
151
152	/* Perform set up for DMA */
153	if (pci_enable_device_io(pdev)) {
154		printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n");
155		return -ENODEV;
156	}
157
158	if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) {
159		printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n");
160		return -ENODEV;
161	}
162
163	/* Map IO ports and initialize host accordingly */
164	iomap[0] = devm_ioport_map(&pdev->dev, cmd_port[0], 8);
165	iomap[1] = devm_ioport_map(&pdev->dev, ctl_port[0], 1);
166	iomap[2] = devm_ioport_map(&pdev->dev, cmd_port[1], 8);
167	iomap[3] = devm_ioport_map(&pdev->dev, ctl_port[1], 1);
168	iomap[4] = pcim_iomap(pdev, 2, 0);
169
170	if (!iomap[0] || !iomap[1] || !iomap[2] || !iomap[3] || !iomap[4])
171		return -ENOMEM;
172
173	ioaddr = &host->ports[0]->ioaddr;
174	ioaddr->cmd_addr = iomap[0];
175	ioaddr->ctl_addr = iomap[1];
176	ioaddr->altstatus_addr = iomap[1];
177	ioaddr->bmdma_addr = iomap[4];
178	ata_sff_std_ports(ioaddr);
179
180	ata_port_desc(host->ports[0],
181		      "cmd 0x%x ctl 0x%x", cmd_port[0], ctl_port[0]);
182	ata_port_pbar_desc(host->ports[0], 4, 0, "bmdma");
183
184	ioaddr = &host->ports[1]->ioaddr;
185	ioaddr->cmd_addr = iomap[2];
186	ioaddr->ctl_addr = iomap[3];
187	ioaddr->altstatus_addr = iomap[3];
188	ioaddr->bmdma_addr = iomap[4] + 8;
189	ata_sff_std_ports(ioaddr);
190
191	ata_port_desc(host->ports[1],
192		      "cmd 0x%x ctl 0x%x", cmd_port[1], ctl_port[1]);
193	ata_port_pbar_desc(host->ports[1], 4, 8, "bmdma");
194
195	/* activate the host */
196	pci_set_master(pdev);
197	rc = ata_host_start(host);
198	if (rc)
199		return rc;
200
201	for (i = 0; i < 2; i++) {
202		static const int irq[] = { 14, 15 };
203		struct ata_port *ap = host->ports[i];
204
205		if (ata_port_is_dummy(ap))
206			continue;
207
208		rc = devm_request_irq(&pdev->dev, irq[ap->port_no],
209				      ata_bmdma_interrupt, 0, DRV_NAME, host);
210		if (rc)
211			return rc;
212
213		ata_port_desc(ap, "irq %d", irq[i]);
214	}
215
216	return ata_host_register(host, &cs5520_sht);
217}
218
219#ifdef CONFIG_PM_SLEEP
220/**
221 *	cs5520_reinit_one	-	device resume
222 *	@pdev: PCI device
223 *
224 *	Do any reconfiguration work needed by a resume from RAM. We need
225 *	to restore DMA mode support on BIOSen which disabled it
226 */
227
228static int cs5520_reinit_one(struct pci_dev *pdev)
229{
230	struct ata_host *host = pci_get_drvdata(pdev);
231	u8 pcicfg;
232	int rc;
233
234	rc = ata_pci_device_do_resume(pdev);
235	if (rc)
236		return rc;
237
238	pci_read_config_byte(pdev, 0x60, &pcicfg);
239	if ((pcicfg & 0x40) == 0)
240		pci_write_config_byte(pdev, 0x60, pcicfg | 0x40);
241
242	ata_host_resume(host);
243	return 0;
244}
245
246/**
247 *	cs5520_pci_device_suspend	-	device suspend
248 *	@pdev: PCI device
249 *
250 *	We have to cut and waste bits from the standard method because
251 *	the 5520 is a bit odd and not just a pure ATA device. As a result
252 *	we must not disable it. The needed code is short and this avoids
253 *	chip specific mess in the core code.
254 */
255
256static int cs5520_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
257{
258	struct ata_host *host = pci_get_drvdata(pdev);
259	int rc = 0;
260
261	rc = ata_host_suspend(host, mesg);
262	if (rc)
263		return rc;
264
265	pci_save_state(pdev);
266	return 0;
267}
268#endif /* CONFIG_PM_SLEEP */
269
270/* For now keep DMA off. We can set it for all but A rev CS5510 once the
271   core ATA code can handle it */
272
273static const struct pci_device_id pata_cs5520[] = {
274	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), },
275	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), },
276
277	{ },
278};
279
280static struct pci_driver cs5520_pci_driver = {
281	.name 		= DRV_NAME,
282	.id_table	= pata_cs5520,
283	.probe 		= cs5520_init_one,
284	.remove		= ata_pci_remove_one,
285#ifdef CONFIG_PM_SLEEP
286	.suspend	= cs5520_pci_device_suspend,
287	.resume		= cs5520_reinit_one,
288#endif
289};
290
291module_pci_driver(cs5520_pci_driver);
292
293MODULE_AUTHOR("Alan Cox");
294MODULE_DESCRIPTION("low-level driver for Cyrix CS5510/5520");
295MODULE_LICENSE("GPL");
296MODULE_DEVICE_TABLE(pci, pata_cs5520);
297MODULE_VERSION(DRV_VERSION);
298