18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-only 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * pata_cmd640.c - CMD640 PCI PATA for new ATA layer 48c2ecf20Sopenharmony_ci * (C) 2007 Red Hat Inc 58c2ecf20Sopenharmony_ci * 68c2ecf20Sopenharmony_ci * Based upon 78c2ecf20Sopenharmony_ci * linux/drivers/ide/pci/cmd640.c Version 1.02 Sep 01, 1996 88c2ecf20Sopenharmony_ci * 98c2ecf20Sopenharmony_ci * Copyright (C) 1995-1996 Linus Torvalds & authors (see driver) 108c2ecf20Sopenharmony_ci * 118c2ecf20Sopenharmony_ci * This drives only the PCI version of the controller. If you have a 128c2ecf20Sopenharmony_ci * VLB one then we have enough docs to support it but you can write 138c2ecf20Sopenharmony_ci * your own code. 148c2ecf20Sopenharmony_ci */ 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci#include <linux/kernel.h> 178c2ecf20Sopenharmony_ci#include <linux/module.h> 188c2ecf20Sopenharmony_ci#include <linux/pci.h> 198c2ecf20Sopenharmony_ci#include <linux/blkdev.h> 208c2ecf20Sopenharmony_ci#include <linux/delay.h> 218c2ecf20Sopenharmony_ci#include <linux/gfp.h> 228c2ecf20Sopenharmony_ci#include <scsi/scsi_host.h> 238c2ecf20Sopenharmony_ci#include <linux/libata.h> 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci#define DRV_NAME "pata_cmd640" 268c2ecf20Sopenharmony_ci#define DRV_VERSION "0.0.5" 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_cistruct cmd640_reg { 298c2ecf20Sopenharmony_ci int last; 308c2ecf20Sopenharmony_ci u8 reg58[ATA_MAX_DEVICES]; 318c2ecf20Sopenharmony_ci}; 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_cienum { 348c2ecf20Sopenharmony_ci CFR = 0x50, 358c2ecf20Sopenharmony_ci CNTRL = 0x51, 368c2ecf20Sopenharmony_ci CMDTIM = 0x52, 378c2ecf20Sopenharmony_ci ARTIM0 = 0x53, 388c2ecf20Sopenharmony_ci DRWTIM0 = 0x54, 398c2ecf20Sopenharmony_ci ARTIM23 = 0x57, 408c2ecf20Sopenharmony_ci DRWTIM23 = 0x58, 418c2ecf20Sopenharmony_ci BRST = 0x59 428c2ecf20Sopenharmony_ci}; 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ci/** 458c2ecf20Sopenharmony_ci * cmd640_set_piomode - set initial PIO mode data 468c2ecf20Sopenharmony_ci * @ap: ATA port 478c2ecf20Sopenharmony_ci * @adev: ATA device 488c2ecf20Sopenharmony_ci * 498c2ecf20Sopenharmony_ci * Called to do the PIO mode setup. 508c2ecf20Sopenharmony_ci */ 518c2ecf20Sopenharmony_ci 528c2ecf20Sopenharmony_cistatic void cmd640_set_piomode(struct ata_port *ap, struct ata_device *adev) 538c2ecf20Sopenharmony_ci{ 548c2ecf20Sopenharmony_ci struct cmd640_reg *timing = ap->private_data; 558c2ecf20Sopenharmony_ci struct pci_dev *pdev = to_pci_dev(ap->host->dev); 568c2ecf20Sopenharmony_ci struct ata_timing t; 578c2ecf20Sopenharmony_ci const unsigned long T = 1000000 / 33; 588c2ecf20Sopenharmony_ci const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 }; 598c2ecf20Sopenharmony_ci u8 reg; 608c2ecf20Sopenharmony_ci int arttim = ARTIM0 + 2 * adev->devno; 618c2ecf20Sopenharmony_ci struct ata_device *pair = ata_dev_pair(adev); 628c2ecf20Sopenharmony_ci 638c2ecf20Sopenharmony_ci if (ata_timing_compute(adev, adev->pio_mode, &t, T, 0) < 0) { 648c2ecf20Sopenharmony_ci printk(KERN_ERR DRV_NAME ": mode computation failed.\n"); 658c2ecf20Sopenharmony_ci return; 668c2ecf20Sopenharmony_ci } 678c2ecf20Sopenharmony_ci 688c2ecf20Sopenharmony_ci /* The second channel has shared timings and the setup timing is 698c2ecf20Sopenharmony_ci messy to switch to merge it for worst case */ 708c2ecf20Sopenharmony_ci if (ap->port_no && pair) { 718c2ecf20Sopenharmony_ci struct ata_timing p; 728c2ecf20Sopenharmony_ci ata_timing_compute(pair, pair->pio_mode, &p, T, 1); 738c2ecf20Sopenharmony_ci ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP); 748c2ecf20Sopenharmony_ci } 758c2ecf20Sopenharmony_ci 768c2ecf20Sopenharmony_ci /* Make the timings fit */ 778c2ecf20Sopenharmony_ci if (t.recover > 16) { 788c2ecf20Sopenharmony_ci t.active += t.recover - 16; 798c2ecf20Sopenharmony_ci t.recover = 16; 808c2ecf20Sopenharmony_ci } 818c2ecf20Sopenharmony_ci if (t.active > 16) 828c2ecf20Sopenharmony_ci t.active = 16; 838c2ecf20Sopenharmony_ci 848c2ecf20Sopenharmony_ci /* Now convert the clocks into values we can actually stuff into 858c2ecf20Sopenharmony_ci the chip */ 868c2ecf20Sopenharmony_ci 878c2ecf20Sopenharmony_ci if (t.recover > 1) 888c2ecf20Sopenharmony_ci t.recover--; /* 640B only */ 898c2ecf20Sopenharmony_ci else 908c2ecf20Sopenharmony_ci t.recover = 15; 918c2ecf20Sopenharmony_ci 928c2ecf20Sopenharmony_ci if (t.setup > 4) 938c2ecf20Sopenharmony_ci t.setup = 0xC0; 948c2ecf20Sopenharmony_ci else 958c2ecf20Sopenharmony_ci t.setup = setup_data[t.setup]; 968c2ecf20Sopenharmony_ci 978c2ecf20Sopenharmony_ci if (ap->port_no == 0) { 988c2ecf20Sopenharmony_ci t.active &= 0x0F; /* 0 = 16 */ 998c2ecf20Sopenharmony_ci 1008c2ecf20Sopenharmony_ci /* Load setup timing */ 1018c2ecf20Sopenharmony_ci pci_read_config_byte(pdev, arttim, ®); 1028c2ecf20Sopenharmony_ci reg &= 0x3F; 1038c2ecf20Sopenharmony_ci reg |= t.setup; 1048c2ecf20Sopenharmony_ci pci_write_config_byte(pdev, arttim, reg); 1058c2ecf20Sopenharmony_ci 1068c2ecf20Sopenharmony_ci /* Load active/recovery */ 1078c2ecf20Sopenharmony_ci pci_write_config_byte(pdev, arttim + 1, (t.active << 4) | t.recover); 1088c2ecf20Sopenharmony_ci } else { 1098c2ecf20Sopenharmony_ci /* Save the shared timings for channel, they will be loaded 1108c2ecf20Sopenharmony_ci by qc_issue. Reloading the setup time is expensive so we 1118c2ecf20Sopenharmony_ci keep a merged one loaded */ 1128c2ecf20Sopenharmony_ci pci_read_config_byte(pdev, ARTIM23, ®); 1138c2ecf20Sopenharmony_ci reg &= 0x3F; 1148c2ecf20Sopenharmony_ci reg |= t.setup; 1158c2ecf20Sopenharmony_ci pci_write_config_byte(pdev, ARTIM23, reg); 1168c2ecf20Sopenharmony_ci timing->reg58[adev->devno] = (t.active << 4) | t.recover; 1178c2ecf20Sopenharmony_ci } 1188c2ecf20Sopenharmony_ci} 1198c2ecf20Sopenharmony_ci 1208c2ecf20Sopenharmony_ci 1218c2ecf20Sopenharmony_ci/** 1228c2ecf20Sopenharmony_ci * cmd640_qc_issue - command preparation hook 1238c2ecf20Sopenharmony_ci * @qc: Command to be issued 1248c2ecf20Sopenharmony_ci * 1258c2ecf20Sopenharmony_ci * Channel 1 has shared timings. We must reprogram the 1268c2ecf20Sopenharmony_ci * clock each drive 2/3 switch we do. 1278c2ecf20Sopenharmony_ci */ 1288c2ecf20Sopenharmony_ci 1298c2ecf20Sopenharmony_cistatic unsigned int cmd640_qc_issue(struct ata_queued_cmd *qc) 1308c2ecf20Sopenharmony_ci{ 1318c2ecf20Sopenharmony_ci struct ata_port *ap = qc->ap; 1328c2ecf20Sopenharmony_ci struct ata_device *adev = qc->dev; 1338c2ecf20Sopenharmony_ci struct pci_dev *pdev = to_pci_dev(ap->host->dev); 1348c2ecf20Sopenharmony_ci struct cmd640_reg *timing = ap->private_data; 1358c2ecf20Sopenharmony_ci 1368c2ecf20Sopenharmony_ci if (ap->port_no != 0 && adev->devno != timing->last) { 1378c2ecf20Sopenharmony_ci pci_write_config_byte(pdev, DRWTIM23, timing->reg58[adev->devno]); 1388c2ecf20Sopenharmony_ci timing->last = adev->devno; 1398c2ecf20Sopenharmony_ci } 1408c2ecf20Sopenharmony_ci return ata_sff_qc_issue(qc); 1418c2ecf20Sopenharmony_ci} 1428c2ecf20Sopenharmony_ci 1438c2ecf20Sopenharmony_ci/** 1448c2ecf20Sopenharmony_ci * cmd640_port_start - port setup 1458c2ecf20Sopenharmony_ci * @ap: ATA port being set up 1468c2ecf20Sopenharmony_ci * 1478c2ecf20Sopenharmony_ci * The CMD640 needs to maintain private data structures so we 1488c2ecf20Sopenharmony_ci * allocate space here. 1498c2ecf20Sopenharmony_ci */ 1508c2ecf20Sopenharmony_ci 1518c2ecf20Sopenharmony_cistatic int cmd640_port_start(struct ata_port *ap) 1528c2ecf20Sopenharmony_ci{ 1538c2ecf20Sopenharmony_ci struct pci_dev *pdev = to_pci_dev(ap->host->dev); 1548c2ecf20Sopenharmony_ci struct cmd640_reg *timing; 1558c2ecf20Sopenharmony_ci 1568c2ecf20Sopenharmony_ci timing = devm_kzalloc(&pdev->dev, sizeof(struct cmd640_reg), GFP_KERNEL); 1578c2ecf20Sopenharmony_ci if (timing == NULL) 1588c2ecf20Sopenharmony_ci return -ENOMEM; 1598c2ecf20Sopenharmony_ci timing->last = -1; /* Force a load */ 1608c2ecf20Sopenharmony_ci ap->private_data = timing; 1618c2ecf20Sopenharmony_ci return 0; 1628c2ecf20Sopenharmony_ci} 1638c2ecf20Sopenharmony_ci 1648c2ecf20Sopenharmony_cistatic bool cmd640_sff_irq_check(struct ata_port *ap) 1658c2ecf20Sopenharmony_ci{ 1668c2ecf20Sopenharmony_ci struct pci_dev *pdev = to_pci_dev(ap->host->dev); 1678c2ecf20Sopenharmony_ci int irq_reg = ap->port_no ? ARTIM23 : CFR; 1688c2ecf20Sopenharmony_ci u8 irq_stat, irq_mask = ap->port_no ? 0x10 : 0x04; 1698c2ecf20Sopenharmony_ci 1708c2ecf20Sopenharmony_ci pci_read_config_byte(pdev, irq_reg, &irq_stat); 1718c2ecf20Sopenharmony_ci 1728c2ecf20Sopenharmony_ci return irq_stat & irq_mask; 1738c2ecf20Sopenharmony_ci} 1748c2ecf20Sopenharmony_ci 1758c2ecf20Sopenharmony_cistatic struct scsi_host_template cmd640_sht = { 1768c2ecf20Sopenharmony_ci ATA_PIO_SHT(DRV_NAME), 1778c2ecf20Sopenharmony_ci}; 1788c2ecf20Sopenharmony_ci 1798c2ecf20Sopenharmony_cistatic struct ata_port_operations cmd640_port_ops = { 1808c2ecf20Sopenharmony_ci .inherits = &ata_sff_port_ops, 1818c2ecf20Sopenharmony_ci /* In theory xfer_noirq is not needed once we kill the prefetcher */ 1828c2ecf20Sopenharmony_ci .sff_data_xfer = ata_sff_data_xfer32, 1838c2ecf20Sopenharmony_ci .sff_irq_check = cmd640_sff_irq_check, 1848c2ecf20Sopenharmony_ci .qc_issue = cmd640_qc_issue, 1858c2ecf20Sopenharmony_ci .cable_detect = ata_cable_40wire, 1868c2ecf20Sopenharmony_ci .set_piomode = cmd640_set_piomode, 1878c2ecf20Sopenharmony_ci .port_start = cmd640_port_start, 1888c2ecf20Sopenharmony_ci}; 1898c2ecf20Sopenharmony_ci 1908c2ecf20Sopenharmony_cistatic void cmd640_hardware_init(struct pci_dev *pdev) 1918c2ecf20Sopenharmony_ci{ 1928c2ecf20Sopenharmony_ci u8 ctrl; 1938c2ecf20Sopenharmony_ci 1948c2ecf20Sopenharmony_ci /* CMD640 detected, commiserations */ 1958c2ecf20Sopenharmony_ci pci_write_config_byte(pdev, 0x5B, 0x00); 1968c2ecf20Sopenharmony_ci /* PIO0 command cycles */ 1978c2ecf20Sopenharmony_ci pci_write_config_byte(pdev, CMDTIM, 0); 1988c2ecf20Sopenharmony_ci /* 512 byte bursts (sector) */ 1998c2ecf20Sopenharmony_ci pci_write_config_byte(pdev, BRST, 0x40); 2008c2ecf20Sopenharmony_ci /* 2018c2ecf20Sopenharmony_ci * A reporter a long time ago 2028c2ecf20Sopenharmony_ci * Had problems with the data fifo 2038c2ecf20Sopenharmony_ci * So don't run the risk 2048c2ecf20Sopenharmony_ci * Of putting crap on the disk 2058c2ecf20Sopenharmony_ci * For its better just to go slow 2068c2ecf20Sopenharmony_ci */ 2078c2ecf20Sopenharmony_ci /* Do channel 0 */ 2088c2ecf20Sopenharmony_ci pci_read_config_byte(pdev, CNTRL, &ctrl); 2098c2ecf20Sopenharmony_ci pci_write_config_byte(pdev, CNTRL, ctrl | 0xC0); 2108c2ecf20Sopenharmony_ci /* Ditto for channel 1 */ 2118c2ecf20Sopenharmony_ci pci_read_config_byte(pdev, ARTIM23, &ctrl); 2128c2ecf20Sopenharmony_ci ctrl |= 0x0C; 2138c2ecf20Sopenharmony_ci pci_write_config_byte(pdev, ARTIM23, ctrl); 2148c2ecf20Sopenharmony_ci} 2158c2ecf20Sopenharmony_ci 2168c2ecf20Sopenharmony_cistatic int cmd640_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 2178c2ecf20Sopenharmony_ci{ 2188c2ecf20Sopenharmony_ci static const struct ata_port_info info = { 2198c2ecf20Sopenharmony_ci .flags = ATA_FLAG_SLAVE_POSS, 2208c2ecf20Sopenharmony_ci .pio_mask = ATA_PIO4, 2218c2ecf20Sopenharmony_ci .port_ops = &cmd640_port_ops 2228c2ecf20Sopenharmony_ci }; 2238c2ecf20Sopenharmony_ci const struct ata_port_info *ppi[] = { &info, NULL }; 2248c2ecf20Sopenharmony_ci int rc; 2258c2ecf20Sopenharmony_ci 2268c2ecf20Sopenharmony_ci rc = pcim_enable_device(pdev); 2278c2ecf20Sopenharmony_ci if (rc) 2288c2ecf20Sopenharmony_ci return rc; 2298c2ecf20Sopenharmony_ci 2308c2ecf20Sopenharmony_ci cmd640_hardware_init(pdev); 2318c2ecf20Sopenharmony_ci 2328c2ecf20Sopenharmony_ci return ata_pci_sff_init_one(pdev, ppi, &cmd640_sht, NULL, 0); 2338c2ecf20Sopenharmony_ci} 2348c2ecf20Sopenharmony_ci 2358c2ecf20Sopenharmony_ci#ifdef CONFIG_PM_SLEEP 2368c2ecf20Sopenharmony_cistatic int cmd640_reinit_one(struct pci_dev *pdev) 2378c2ecf20Sopenharmony_ci{ 2388c2ecf20Sopenharmony_ci struct ata_host *host = pci_get_drvdata(pdev); 2398c2ecf20Sopenharmony_ci int rc; 2408c2ecf20Sopenharmony_ci 2418c2ecf20Sopenharmony_ci rc = ata_pci_device_do_resume(pdev); 2428c2ecf20Sopenharmony_ci if (rc) 2438c2ecf20Sopenharmony_ci return rc; 2448c2ecf20Sopenharmony_ci cmd640_hardware_init(pdev); 2458c2ecf20Sopenharmony_ci ata_host_resume(host); 2468c2ecf20Sopenharmony_ci return 0; 2478c2ecf20Sopenharmony_ci} 2488c2ecf20Sopenharmony_ci#endif 2498c2ecf20Sopenharmony_ci 2508c2ecf20Sopenharmony_cistatic const struct pci_device_id cmd640[] = { 2518c2ecf20Sopenharmony_ci { PCI_VDEVICE(CMD, 0x640), 0 }, 2528c2ecf20Sopenharmony_ci { }, 2538c2ecf20Sopenharmony_ci}; 2548c2ecf20Sopenharmony_ci 2558c2ecf20Sopenharmony_cistatic struct pci_driver cmd640_pci_driver = { 2568c2ecf20Sopenharmony_ci .name = DRV_NAME, 2578c2ecf20Sopenharmony_ci .id_table = cmd640, 2588c2ecf20Sopenharmony_ci .probe = cmd640_init_one, 2598c2ecf20Sopenharmony_ci .remove = ata_pci_remove_one, 2608c2ecf20Sopenharmony_ci#ifdef CONFIG_PM_SLEEP 2618c2ecf20Sopenharmony_ci .suspend = ata_pci_device_suspend, 2628c2ecf20Sopenharmony_ci .resume = cmd640_reinit_one, 2638c2ecf20Sopenharmony_ci#endif 2648c2ecf20Sopenharmony_ci}; 2658c2ecf20Sopenharmony_ci 2668c2ecf20Sopenharmony_cimodule_pci_driver(cmd640_pci_driver); 2678c2ecf20Sopenharmony_ci 2688c2ecf20Sopenharmony_ciMODULE_AUTHOR("Alan Cox"); 2698c2ecf20Sopenharmony_ciMODULE_DESCRIPTION("low-level driver for CMD640 PATA controllers"); 2708c2ecf20Sopenharmony_ciMODULE_LICENSE("GPL"); 2718c2ecf20Sopenharmony_ciMODULE_DEVICE_TABLE(pci, cmd640); 2728c2ecf20Sopenharmony_ciMODULE_VERSION(DRV_VERSION); 273