1/* 2 * drivers/ata/pata_arasan_cf.c 3 * 4 * Arasan Compact Flash host controller source file 5 * 6 * Copyright (C) 2011 ST Microelectronics 7 * Viresh Kumar <vireshk@kernel.org> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14/* 15 * The Arasan CompactFlash Device Controller IP core has three basic modes of 16 * operation: PC card ATA using I/O mode, PC card ATA using memory mode, PC card 17 * ATA using true IDE modes. This driver supports only True IDE mode currently. 18 * 19 * Arasan CF Controller shares global irq register with Arasan XD Controller. 20 * 21 * Tested on arch/arm/mach-spear13xx 22 */ 23 24#include <linux/ata.h> 25#include <linux/clk.h> 26#include <linux/completion.h> 27#include <linux/delay.h> 28#include <linux/dmaengine.h> 29#include <linux/io.h> 30#include <linux/irq.h> 31#include <linux/kernel.h> 32#include <linux/libata.h> 33#include <linux/module.h> 34#include <linux/of.h> 35#include <linux/pata_arasan_cf_data.h> 36#include <linux/platform_device.h> 37#include <linux/pm.h> 38#include <linux/slab.h> 39#include <linux/spinlock.h> 40#include <linux/types.h> 41#include <linux/workqueue.h> 42 43#define DRIVER_NAME "arasan_cf" 44#define TIMEOUT msecs_to_jiffies(3000) 45 46/* Registers */ 47/* CompactFlash Interface Status */ 48#define CFI_STS 0x000 49 #define STS_CHG (1) 50 #define BIN_AUDIO_OUT (1 << 1) 51 #define CARD_DETECT1 (1 << 2) 52 #define CARD_DETECT2 (1 << 3) 53 #define INP_ACK (1 << 4) 54 #define CARD_READY (1 << 5) 55 #define IO_READY (1 << 6) 56 #define B16_IO_PORT_SEL (1 << 7) 57/* IRQ */ 58#define IRQ_STS 0x004 59/* Interrupt Enable */ 60#define IRQ_EN 0x008 61 #define CARD_DETECT_IRQ (1) 62 #define STATUS_CHNG_IRQ (1 << 1) 63 #define MEM_MODE_IRQ (1 << 2) 64 #define IO_MODE_IRQ (1 << 3) 65 #define TRUE_IDE_MODE_IRQ (1 << 8) 66 #define PIO_XFER_ERR_IRQ (1 << 9) 67 #define BUF_AVAIL_IRQ (1 << 10) 68 #define XFER_DONE_IRQ (1 << 11) 69 #define IGNORED_IRQS (STATUS_CHNG_IRQ | MEM_MODE_IRQ | IO_MODE_IRQ |\ 70 TRUE_IDE_MODE_IRQ) 71 #define TRUE_IDE_IRQS (CARD_DETECT_IRQ | PIO_XFER_ERR_IRQ |\ 72 BUF_AVAIL_IRQ | XFER_DONE_IRQ) 73/* Operation Mode */ 74#define OP_MODE 0x00C 75 #define CARD_MODE_MASK (0x3) 76 #define MEM_MODE (0x0) 77 #define IO_MODE (0x1) 78 #define TRUE_IDE_MODE (0x2) 79 80 #define CARD_TYPE_MASK (1 << 2) 81 #define CF_CARD (0) 82 #define CF_PLUS_CARD (1 << 2) 83 84 #define CARD_RESET (1 << 3) 85 #define CFHOST_ENB (1 << 4) 86 #define OUTPUTS_TRISTATE (1 << 5) 87 #define ULTRA_DMA_ENB (1 << 8) 88 #define MULTI_WORD_DMA_ENB (1 << 9) 89 #define DRQ_BLOCK_SIZE_MASK (0x3 << 11) 90 #define DRQ_BLOCK_SIZE_512 (0) 91 #define DRQ_BLOCK_SIZE_1024 (1 << 11) 92 #define DRQ_BLOCK_SIZE_2048 (2 << 11) 93 #define DRQ_BLOCK_SIZE_4096 (3 << 11) 94/* CF Interface Clock Configuration */ 95#define CLK_CFG 0x010 96 #define CF_IF_CLK_MASK (0XF) 97/* CF Timing Mode Configuration */ 98#define TM_CFG 0x014 99 #define MEM_MODE_TIMING_MASK (0x3) 100 #define MEM_MODE_TIMING_250NS (0x0) 101 #define MEM_MODE_TIMING_120NS (0x1) 102 #define MEM_MODE_TIMING_100NS (0x2) 103 #define MEM_MODE_TIMING_80NS (0x3) 104 105 #define IO_MODE_TIMING_MASK (0x3 << 2) 106 #define IO_MODE_TIMING_250NS (0x0 << 2) 107 #define IO_MODE_TIMING_120NS (0x1 << 2) 108 #define IO_MODE_TIMING_100NS (0x2 << 2) 109 #define IO_MODE_TIMING_80NS (0x3 << 2) 110 111 #define TRUEIDE_PIO_TIMING_MASK (0x7 << 4) 112 #define TRUEIDE_PIO_TIMING_SHIFT 4 113 114 #define TRUEIDE_MWORD_DMA_TIMING_MASK (0x7 << 7) 115 #define TRUEIDE_MWORD_DMA_TIMING_SHIFT 7 116 117 #define ULTRA_DMA_TIMING_MASK (0x7 << 10) 118 #define ULTRA_DMA_TIMING_SHIFT 10 119/* CF Transfer Address */ 120#define XFER_ADDR 0x014 121 #define XFER_ADDR_MASK (0x7FF) 122 #define MAX_XFER_COUNT 0x20000u 123/* Transfer Control */ 124#define XFER_CTR 0x01C 125 #define XFER_COUNT_MASK (0x3FFFF) 126 #define ADDR_INC_DISABLE (1 << 24) 127 #define XFER_WIDTH_MASK (1 << 25) 128 #define XFER_WIDTH_8B (0) 129 #define XFER_WIDTH_16B (1 << 25) 130 131 #define MEM_TYPE_MASK (1 << 26) 132 #define MEM_TYPE_COMMON (0) 133 #define MEM_TYPE_ATTRIBUTE (1 << 26) 134 135 #define MEM_IO_XFER_MASK (1 << 27) 136 #define MEM_XFER (0) 137 #define IO_XFER (1 << 27) 138 139 #define DMA_XFER_MODE (1 << 28) 140 141 #define AHB_BUS_NORMAL_PIO_OPRTN (~(1 << 29)) 142 #define XFER_DIR_MASK (1 << 30) 143 #define XFER_READ (0) 144 #define XFER_WRITE (1 << 30) 145 146 #define XFER_START (1 << 31) 147/* Write Data Port */ 148#define WRITE_PORT 0x024 149/* Read Data Port */ 150#define READ_PORT 0x028 151/* ATA Data Port */ 152#define ATA_DATA_PORT 0x030 153 #define ATA_DATA_PORT_MASK (0xFFFF) 154/* ATA Error/Features */ 155#define ATA_ERR_FTR 0x034 156/* ATA Sector Count */ 157#define ATA_SC 0x038 158/* ATA Sector Number */ 159#define ATA_SN 0x03C 160/* ATA Cylinder Low */ 161#define ATA_CL 0x040 162/* ATA Cylinder High */ 163#define ATA_CH 0x044 164/* ATA Select Card/Head */ 165#define ATA_SH 0x048 166/* ATA Status-Command */ 167#define ATA_STS_CMD 0x04C 168/* ATA Alternate Status/Device Control */ 169#define ATA_ASTS_DCTR 0x050 170/* Extended Write Data Port 0x200-0x3FC */ 171#define EXT_WRITE_PORT 0x200 172/* Extended Read Data Port 0x400-0x5FC */ 173#define EXT_READ_PORT 0x400 174 #define FIFO_SIZE 0x200u 175/* Global Interrupt Status */ 176#define GIRQ_STS 0x800 177/* Global Interrupt Status enable */ 178#define GIRQ_STS_EN 0x804 179/* Global Interrupt Signal enable */ 180#define GIRQ_SGN_EN 0x808 181 #define GIRQ_CF (1) 182 #define GIRQ_XD (1 << 1) 183 184/* Compact Flash Controller Dev Structure */ 185struct arasan_cf_dev { 186 /* pointer to ata_host structure */ 187 struct ata_host *host; 188 /* clk structure */ 189 struct clk *clk; 190 191 /* physical base address of controller */ 192 dma_addr_t pbase; 193 /* virtual base address of controller */ 194 void __iomem *vbase; 195 /* irq number*/ 196 int irq; 197 198 /* status to be updated to framework regarding DMA transfer */ 199 u8 dma_status; 200 /* Card is present or Not */ 201 u8 card_present; 202 203 /* dma specific */ 204 /* Completion for transfer complete interrupt from controller */ 205 struct completion cf_completion; 206 /* Completion for DMA transfer complete. */ 207 struct completion dma_completion; 208 /* Dma channel allocated */ 209 struct dma_chan *dma_chan; 210 /* Mask for DMA transfers */ 211 dma_cap_mask_t mask; 212 /* DMA transfer work */ 213 struct work_struct work; 214 /* DMA delayed finish work */ 215 struct delayed_work dwork; 216 /* qc to be transferred using DMA */ 217 struct ata_queued_cmd *qc; 218}; 219 220static struct scsi_host_template arasan_cf_sht = { 221 ATA_BASE_SHT(DRIVER_NAME), 222 .dma_boundary = 0xFFFFFFFFUL, 223}; 224 225static void cf_dumpregs(struct arasan_cf_dev *acdev) 226{ 227 struct device *dev = acdev->host->dev; 228 229 dev_dbg(dev, ": =========== REGISTER DUMP ==========="); 230 dev_dbg(dev, ": CFI_STS: %x", readl(acdev->vbase + CFI_STS)); 231 dev_dbg(dev, ": IRQ_STS: %x", readl(acdev->vbase + IRQ_STS)); 232 dev_dbg(dev, ": IRQ_EN: %x", readl(acdev->vbase + IRQ_EN)); 233 dev_dbg(dev, ": OP_MODE: %x", readl(acdev->vbase + OP_MODE)); 234 dev_dbg(dev, ": CLK_CFG: %x", readl(acdev->vbase + CLK_CFG)); 235 dev_dbg(dev, ": TM_CFG: %x", readl(acdev->vbase + TM_CFG)); 236 dev_dbg(dev, ": XFER_CTR: %x", readl(acdev->vbase + XFER_CTR)); 237 dev_dbg(dev, ": GIRQ_STS: %x", readl(acdev->vbase + GIRQ_STS)); 238 dev_dbg(dev, ": GIRQ_STS_EN: %x", readl(acdev->vbase + GIRQ_STS_EN)); 239 dev_dbg(dev, ": GIRQ_SGN_EN: %x", readl(acdev->vbase + GIRQ_SGN_EN)); 240 dev_dbg(dev, ": ====================================="); 241} 242 243/* Enable/Disable global interrupts shared between CF and XD ctrlr. */ 244static void cf_ginterrupt_enable(struct arasan_cf_dev *acdev, bool enable) 245{ 246 /* enable should be 0 or 1 */ 247 writel(enable, acdev->vbase + GIRQ_STS_EN); 248 writel(enable, acdev->vbase + GIRQ_SGN_EN); 249} 250 251/* Enable/Disable CF interrupts */ 252static inline void 253cf_interrupt_enable(struct arasan_cf_dev *acdev, u32 mask, bool enable) 254{ 255 u32 val = readl(acdev->vbase + IRQ_EN); 256 /* clear & enable/disable irqs */ 257 if (enable) { 258 writel(mask, acdev->vbase + IRQ_STS); 259 writel(val | mask, acdev->vbase + IRQ_EN); 260 } else 261 writel(val & ~mask, acdev->vbase + IRQ_EN); 262} 263 264static inline void cf_card_reset(struct arasan_cf_dev *acdev) 265{ 266 u32 val = readl(acdev->vbase + OP_MODE); 267 268 writel(val | CARD_RESET, acdev->vbase + OP_MODE); 269 udelay(200); 270 writel(val & ~CARD_RESET, acdev->vbase + OP_MODE); 271} 272 273static inline void cf_ctrl_reset(struct arasan_cf_dev *acdev) 274{ 275 writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB, 276 acdev->vbase + OP_MODE); 277 writel(readl(acdev->vbase + OP_MODE) | CFHOST_ENB, 278 acdev->vbase + OP_MODE); 279} 280 281static void cf_card_detect(struct arasan_cf_dev *acdev, bool hotplugged) 282{ 283 struct ata_port *ap = acdev->host->ports[0]; 284 struct ata_eh_info *ehi = &ap->link.eh_info; 285 u32 val = readl(acdev->vbase + CFI_STS); 286 287 /* Both CD1 & CD2 should be low if card inserted completely */ 288 if (!(val & (CARD_DETECT1 | CARD_DETECT2))) { 289 if (acdev->card_present) 290 return; 291 acdev->card_present = 1; 292 cf_card_reset(acdev); 293 } else { 294 if (!acdev->card_present) 295 return; 296 acdev->card_present = 0; 297 } 298 299 if (hotplugged) { 300 ata_ehi_hotplugged(ehi); 301 ata_port_freeze(ap); 302 } 303} 304 305static int cf_init(struct arasan_cf_dev *acdev) 306{ 307 struct arasan_cf_pdata *pdata = dev_get_platdata(acdev->host->dev); 308 unsigned int if_clk; 309 unsigned long flags; 310 int ret = 0; 311 312 ret = clk_prepare_enable(acdev->clk); 313 if (ret) { 314 dev_dbg(acdev->host->dev, "clock enable failed"); 315 return ret; 316 } 317 318 ret = clk_set_rate(acdev->clk, 166000000); 319 if (ret) { 320 dev_warn(acdev->host->dev, "clock set rate failed"); 321 clk_disable_unprepare(acdev->clk); 322 return ret; 323 } 324 325 spin_lock_irqsave(&acdev->host->lock, flags); 326 /* configure CF interface clock */ 327 /* TODO: read from device tree */ 328 if_clk = CF_IF_CLK_166M; 329 if (pdata && pdata->cf_if_clk <= CF_IF_CLK_200M) 330 if_clk = pdata->cf_if_clk; 331 332 writel(if_clk, acdev->vbase + CLK_CFG); 333 334 writel(TRUE_IDE_MODE | CFHOST_ENB, acdev->vbase + OP_MODE); 335 cf_interrupt_enable(acdev, CARD_DETECT_IRQ, 1); 336 cf_ginterrupt_enable(acdev, 1); 337 spin_unlock_irqrestore(&acdev->host->lock, flags); 338 339 return ret; 340} 341 342static void cf_exit(struct arasan_cf_dev *acdev) 343{ 344 unsigned long flags; 345 346 spin_lock_irqsave(&acdev->host->lock, flags); 347 cf_ginterrupt_enable(acdev, 0); 348 cf_interrupt_enable(acdev, TRUE_IDE_IRQS, 0); 349 cf_card_reset(acdev); 350 writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB, 351 acdev->vbase + OP_MODE); 352 spin_unlock_irqrestore(&acdev->host->lock, flags); 353 clk_disable_unprepare(acdev->clk); 354} 355 356static void dma_callback(void *dev) 357{ 358 struct arasan_cf_dev *acdev = dev; 359 360 complete(&acdev->dma_completion); 361} 362 363static inline void dma_complete(struct arasan_cf_dev *acdev) 364{ 365 struct ata_queued_cmd *qc = acdev->qc; 366 unsigned long flags; 367 368 acdev->qc = NULL; 369 ata_sff_interrupt(acdev->irq, acdev->host); 370 371 spin_lock_irqsave(&acdev->host->lock, flags); 372 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol)) 373 ata_ehi_push_desc(&qc->ap->link.eh_info, "DMA Failed: Timeout"); 374 spin_unlock_irqrestore(&acdev->host->lock, flags); 375} 376 377static inline int wait4buf(struct arasan_cf_dev *acdev) 378{ 379 if (!wait_for_completion_timeout(&acdev->cf_completion, TIMEOUT)) { 380 u32 rw = acdev->qc->tf.flags & ATA_TFLAG_WRITE; 381 382 dev_err(acdev->host->dev, "%s TimeOut", rw ? "write" : "read"); 383 return -ETIMEDOUT; 384 } 385 386 /* Check if PIO Error interrupt has occurred */ 387 if (acdev->dma_status & ATA_DMA_ERR) 388 return -EAGAIN; 389 390 return 0; 391} 392 393static int 394dma_xfer(struct arasan_cf_dev *acdev, dma_addr_t src, dma_addr_t dest, u32 len) 395{ 396 struct dma_async_tx_descriptor *tx; 397 struct dma_chan *chan = acdev->dma_chan; 398 dma_cookie_t cookie; 399 unsigned long flags = DMA_PREP_INTERRUPT; 400 int ret = 0; 401 402 tx = chan->device->device_prep_dma_memcpy(chan, dest, src, len, flags); 403 if (!tx) { 404 dev_err(acdev->host->dev, "device_prep_dma_memcpy failed\n"); 405 return -EAGAIN; 406 } 407 408 tx->callback = dma_callback; 409 tx->callback_param = acdev; 410 cookie = tx->tx_submit(tx); 411 412 ret = dma_submit_error(cookie); 413 if (ret) { 414 dev_err(acdev->host->dev, "dma_submit_error\n"); 415 return ret; 416 } 417 418 chan->device->device_issue_pending(chan); 419 420 /* Wait for DMA to complete */ 421 if (!wait_for_completion_timeout(&acdev->dma_completion, TIMEOUT)) { 422 dmaengine_terminate_all(chan); 423 dev_err(acdev->host->dev, "wait_for_completion_timeout\n"); 424 return -ETIMEDOUT; 425 } 426 427 return ret; 428} 429 430static int sg_xfer(struct arasan_cf_dev *acdev, struct scatterlist *sg) 431{ 432 dma_addr_t dest = 0, src = 0; 433 u32 xfer_cnt, sglen, dma_len, xfer_ctr; 434 u32 write = acdev->qc->tf.flags & ATA_TFLAG_WRITE; 435 unsigned long flags; 436 int ret = 0; 437 438 sglen = sg_dma_len(sg); 439 if (write) { 440 src = sg_dma_address(sg); 441 dest = acdev->pbase + EXT_WRITE_PORT; 442 } else { 443 dest = sg_dma_address(sg); 444 src = acdev->pbase + EXT_READ_PORT; 445 } 446 447 /* 448 * For each sg: 449 * MAX_XFER_COUNT data will be transferred before we get transfer 450 * complete interrupt. Between after FIFO_SIZE data 451 * buffer available interrupt will be generated. At this time we will 452 * fill FIFO again: max FIFO_SIZE data. 453 */ 454 while (sglen) { 455 xfer_cnt = min(sglen, MAX_XFER_COUNT); 456 spin_lock_irqsave(&acdev->host->lock, flags); 457 xfer_ctr = readl(acdev->vbase + XFER_CTR) & 458 ~XFER_COUNT_MASK; 459 writel(xfer_ctr | xfer_cnt | XFER_START, 460 acdev->vbase + XFER_CTR); 461 spin_unlock_irqrestore(&acdev->host->lock, flags); 462 463 /* continue dma xfers until current sg is completed */ 464 while (xfer_cnt) { 465 /* wait for read to complete */ 466 if (!write) { 467 ret = wait4buf(acdev); 468 if (ret) 469 goto fail; 470 } 471 472 /* read/write FIFO in chunk of FIFO_SIZE */ 473 dma_len = min(xfer_cnt, FIFO_SIZE); 474 ret = dma_xfer(acdev, src, dest, dma_len); 475 if (ret) { 476 dev_err(acdev->host->dev, "dma failed"); 477 goto fail; 478 } 479 480 if (write) 481 src += dma_len; 482 else 483 dest += dma_len; 484 485 sglen -= dma_len; 486 xfer_cnt -= dma_len; 487 488 /* wait for write to complete */ 489 if (write) { 490 ret = wait4buf(acdev); 491 if (ret) 492 goto fail; 493 } 494 } 495 } 496 497fail: 498 spin_lock_irqsave(&acdev->host->lock, flags); 499 writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START, 500 acdev->vbase + XFER_CTR); 501 spin_unlock_irqrestore(&acdev->host->lock, flags); 502 503 return ret; 504} 505 506/* 507 * This routine uses External DMA controller to read/write data to FIFO of CF 508 * controller. There are two xfer related interrupt supported by CF controller: 509 * - buf_avail: This interrupt is generated as soon as we have buffer of 512 510 * bytes available for reading or empty buffer available for writing. 511 * - xfer_done: This interrupt is generated on transfer of "xfer_size" amount of 512 * data to/from FIFO. xfer_size is programmed in XFER_CTR register. 513 * 514 * Max buffer size = FIFO_SIZE = 512 Bytes. 515 * Max xfer_size = MAX_XFER_COUNT = 256 KB. 516 */ 517static void data_xfer(struct work_struct *work) 518{ 519 struct arasan_cf_dev *acdev = container_of(work, struct arasan_cf_dev, 520 work); 521 struct ata_queued_cmd *qc = acdev->qc; 522 struct scatterlist *sg; 523 unsigned long flags; 524 u32 temp; 525 int ret = 0; 526 527 /* request dma channels */ 528 /* dma_request_channel may sleep, so calling from process context */ 529 acdev->dma_chan = dma_request_chan(acdev->host->dev, "data"); 530 if (IS_ERR(acdev->dma_chan)) { 531 dev_err_probe(acdev->host->dev, PTR_ERR(acdev->dma_chan), 532 "Unable to get dma_chan\n"); 533 acdev->dma_chan = NULL; 534 goto chan_request_fail; 535 } 536 537 for_each_sg(qc->sg, sg, qc->n_elem, temp) { 538 ret = sg_xfer(acdev, sg); 539 if (ret) 540 break; 541 } 542 543 dma_release_channel(acdev->dma_chan); 544 acdev->dma_chan = NULL; 545 546 /* data xferred successfully */ 547 if (!ret) { 548 u32 status; 549 550 spin_lock_irqsave(&acdev->host->lock, flags); 551 status = ioread8(qc->ap->ioaddr.altstatus_addr); 552 spin_unlock_irqrestore(&acdev->host->lock, flags); 553 if (status & (ATA_BUSY | ATA_DRQ)) { 554 ata_sff_queue_delayed_work(&acdev->dwork, 1); 555 return; 556 } 557 558 goto sff_intr; 559 } 560 561 cf_dumpregs(acdev); 562 563chan_request_fail: 564 spin_lock_irqsave(&acdev->host->lock, flags); 565 /* error when transferring data to/from memory */ 566 qc->err_mask |= AC_ERR_HOST_BUS; 567 qc->ap->hsm_task_state = HSM_ST_ERR; 568 569 cf_ctrl_reset(acdev); 570 spin_unlock_irqrestore(&acdev->host->lock, flags); 571sff_intr: 572 dma_complete(acdev); 573} 574 575static void delayed_finish(struct work_struct *work) 576{ 577 struct arasan_cf_dev *acdev = container_of(work, struct arasan_cf_dev, 578 dwork.work); 579 struct ata_queued_cmd *qc = acdev->qc; 580 unsigned long flags; 581 u8 status; 582 583 spin_lock_irqsave(&acdev->host->lock, flags); 584 status = ioread8(qc->ap->ioaddr.altstatus_addr); 585 spin_unlock_irqrestore(&acdev->host->lock, flags); 586 587 if (status & (ATA_BUSY | ATA_DRQ)) 588 ata_sff_queue_delayed_work(&acdev->dwork, 1); 589 else 590 dma_complete(acdev); 591} 592 593static irqreturn_t arasan_cf_interrupt(int irq, void *dev) 594{ 595 struct arasan_cf_dev *acdev = ((struct ata_host *)dev)->private_data; 596 unsigned long flags; 597 u32 irqsts; 598 599 irqsts = readl(acdev->vbase + GIRQ_STS); 600 if (!(irqsts & GIRQ_CF)) 601 return IRQ_NONE; 602 603 spin_lock_irqsave(&acdev->host->lock, flags); 604 irqsts = readl(acdev->vbase + IRQ_STS); 605 writel(irqsts, acdev->vbase + IRQ_STS); /* clear irqs */ 606 writel(GIRQ_CF, acdev->vbase + GIRQ_STS); /* clear girqs */ 607 608 /* handle only relevant interrupts */ 609 irqsts &= ~IGNORED_IRQS; 610 611 if (irqsts & CARD_DETECT_IRQ) { 612 cf_card_detect(acdev, 1); 613 spin_unlock_irqrestore(&acdev->host->lock, flags); 614 return IRQ_HANDLED; 615 } 616 617 if (irqsts & PIO_XFER_ERR_IRQ) { 618 acdev->dma_status = ATA_DMA_ERR; 619 writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START, 620 acdev->vbase + XFER_CTR); 621 spin_unlock_irqrestore(&acdev->host->lock, flags); 622 complete(&acdev->cf_completion); 623 dev_err(acdev->host->dev, "pio xfer err irq\n"); 624 return IRQ_HANDLED; 625 } 626 627 spin_unlock_irqrestore(&acdev->host->lock, flags); 628 629 if (irqsts & BUF_AVAIL_IRQ) { 630 complete(&acdev->cf_completion); 631 return IRQ_HANDLED; 632 } 633 634 if (irqsts & XFER_DONE_IRQ) { 635 struct ata_queued_cmd *qc = acdev->qc; 636 637 /* Send Complete only for write */ 638 if (qc->tf.flags & ATA_TFLAG_WRITE) 639 complete(&acdev->cf_completion); 640 } 641 642 return IRQ_HANDLED; 643} 644 645static void arasan_cf_freeze(struct ata_port *ap) 646{ 647 struct arasan_cf_dev *acdev = ap->host->private_data; 648 649 /* stop transfer and reset controller */ 650 writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START, 651 acdev->vbase + XFER_CTR); 652 cf_ctrl_reset(acdev); 653 acdev->dma_status = ATA_DMA_ERR; 654 655 ata_sff_dma_pause(ap); 656 ata_sff_freeze(ap); 657} 658 659static void arasan_cf_error_handler(struct ata_port *ap) 660{ 661 struct arasan_cf_dev *acdev = ap->host->private_data; 662 663 /* 664 * DMA transfers using an external DMA controller may be scheduled. 665 * Abort them before handling error. Refer data_xfer() for further 666 * details. 667 */ 668 cancel_work_sync(&acdev->work); 669 cancel_delayed_work_sync(&acdev->dwork); 670 return ata_sff_error_handler(ap); 671} 672 673static void arasan_cf_dma_start(struct arasan_cf_dev *acdev) 674{ 675 struct ata_queued_cmd *qc = acdev->qc; 676 struct ata_port *ap = qc->ap; 677 struct ata_taskfile *tf = &qc->tf; 678 u32 xfer_ctr = readl(acdev->vbase + XFER_CTR) & ~XFER_DIR_MASK; 679 u32 write = tf->flags & ATA_TFLAG_WRITE; 680 681 xfer_ctr |= write ? XFER_WRITE : XFER_READ; 682 writel(xfer_ctr, acdev->vbase + XFER_CTR); 683 684 ap->ops->sff_exec_command(ap, tf); 685 ata_sff_queue_work(&acdev->work); 686} 687 688static unsigned int arasan_cf_qc_issue(struct ata_queued_cmd *qc) 689{ 690 struct ata_port *ap = qc->ap; 691 struct arasan_cf_dev *acdev = ap->host->private_data; 692 693 /* defer PIO handling to sff_qc_issue */ 694 if (!ata_is_dma(qc->tf.protocol)) 695 return ata_sff_qc_issue(qc); 696 697 /* select the device */ 698 ata_wait_idle(ap); 699 ata_sff_dev_select(ap, qc->dev->devno); 700 ata_wait_idle(ap); 701 702 /* start the command */ 703 switch (qc->tf.protocol) { 704 case ATA_PROT_DMA: 705 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); 706 707 ap->ops->sff_tf_load(ap, &qc->tf); 708 acdev->dma_status = 0; 709 acdev->qc = qc; 710 arasan_cf_dma_start(acdev); 711 ap->hsm_task_state = HSM_ST_LAST; 712 break; 713 714 default: 715 WARN_ON(1); 716 return AC_ERR_SYSTEM; 717 } 718 719 return 0; 720} 721 722static void arasan_cf_set_piomode(struct ata_port *ap, struct ata_device *adev) 723{ 724 struct arasan_cf_dev *acdev = ap->host->private_data; 725 u8 pio = adev->pio_mode - XFER_PIO_0; 726 unsigned long flags; 727 u32 val; 728 729 /* Arasan ctrl supports Mode0 -> Mode6 */ 730 if (pio > 6) { 731 dev_err(ap->dev, "Unknown PIO mode\n"); 732 return; 733 } 734 735 spin_lock_irqsave(&acdev->host->lock, flags); 736 val = readl(acdev->vbase + OP_MODE) & 737 ~(ULTRA_DMA_ENB | MULTI_WORD_DMA_ENB | DRQ_BLOCK_SIZE_MASK); 738 writel(val, acdev->vbase + OP_MODE); 739 val = readl(acdev->vbase + TM_CFG) & ~TRUEIDE_PIO_TIMING_MASK; 740 val |= pio << TRUEIDE_PIO_TIMING_SHIFT; 741 writel(val, acdev->vbase + TM_CFG); 742 743 cf_interrupt_enable(acdev, BUF_AVAIL_IRQ | XFER_DONE_IRQ, 0); 744 cf_interrupt_enable(acdev, PIO_XFER_ERR_IRQ, 1); 745 spin_unlock_irqrestore(&acdev->host->lock, flags); 746} 747 748static void arasan_cf_set_dmamode(struct ata_port *ap, struct ata_device *adev) 749{ 750 struct arasan_cf_dev *acdev = ap->host->private_data; 751 u32 opmode, tmcfg, dma_mode = adev->dma_mode; 752 unsigned long flags; 753 754 spin_lock_irqsave(&acdev->host->lock, flags); 755 opmode = readl(acdev->vbase + OP_MODE) & 756 ~(MULTI_WORD_DMA_ENB | ULTRA_DMA_ENB); 757 tmcfg = readl(acdev->vbase + TM_CFG); 758 759 if ((dma_mode >= XFER_UDMA_0) && (dma_mode <= XFER_UDMA_6)) { 760 opmode |= ULTRA_DMA_ENB; 761 tmcfg &= ~ULTRA_DMA_TIMING_MASK; 762 tmcfg |= (dma_mode - XFER_UDMA_0) << ULTRA_DMA_TIMING_SHIFT; 763 } else if ((dma_mode >= XFER_MW_DMA_0) && (dma_mode <= XFER_MW_DMA_4)) { 764 opmode |= MULTI_WORD_DMA_ENB; 765 tmcfg &= ~TRUEIDE_MWORD_DMA_TIMING_MASK; 766 tmcfg |= (dma_mode - XFER_MW_DMA_0) << 767 TRUEIDE_MWORD_DMA_TIMING_SHIFT; 768 } else { 769 dev_err(ap->dev, "Unknown DMA mode\n"); 770 spin_unlock_irqrestore(&acdev->host->lock, flags); 771 return; 772 } 773 774 writel(opmode, acdev->vbase + OP_MODE); 775 writel(tmcfg, acdev->vbase + TM_CFG); 776 writel(DMA_XFER_MODE, acdev->vbase + XFER_CTR); 777 778 cf_interrupt_enable(acdev, PIO_XFER_ERR_IRQ, 0); 779 cf_interrupt_enable(acdev, BUF_AVAIL_IRQ | XFER_DONE_IRQ, 1); 780 spin_unlock_irqrestore(&acdev->host->lock, flags); 781} 782 783static struct ata_port_operations arasan_cf_ops = { 784 .inherits = &ata_sff_port_ops, 785 .freeze = arasan_cf_freeze, 786 .error_handler = arasan_cf_error_handler, 787 .qc_issue = arasan_cf_qc_issue, 788 .set_piomode = arasan_cf_set_piomode, 789 .set_dmamode = arasan_cf_set_dmamode, 790}; 791 792static int arasan_cf_probe(struct platform_device *pdev) 793{ 794 struct arasan_cf_dev *acdev; 795 struct arasan_cf_pdata *pdata = dev_get_platdata(&pdev->dev); 796 struct ata_host *host; 797 struct ata_port *ap; 798 struct resource *res; 799 u32 quirk; 800 irq_handler_t irq_handler = NULL; 801 int ret; 802 803 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 804 if (!res) 805 return -EINVAL; 806 807 if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res), 808 DRIVER_NAME)) { 809 dev_warn(&pdev->dev, "Failed to get memory region resource\n"); 810 return -ENOENT; 811 } 812 813 acdev = devm_kzalloc(&pdev->dev, sizeof(*acdev), GFP_KERNEL); 814 if (!acdev) 815 return -ENOMEM; 816 817 if (pdata) 818 quirk = pdata->quirk; 819 else 820 quirk = CF_BROKEN_UDMA; /* as it is on spear1340 */ 821 822 /* 823 * If there's an error getting IRQ (or we do get IRQ0), 824 * support only PIO 825 */ 826 ret = platform_get_irq(pdev, 0); 827 if (ret > 0) { 828 acdev->irq = ret; 829 irq_handler = arasan_cf_interrupt; 830 } else if (ret == -EPROBE_DEFER) { 831 return ret; 832 } else { 833 quirk |= CF_BROKEN_MWDMA | CF_BROKEN_UDMA; 834 } 835 836 acdev->pbase = res->start; 837 acdev->vbase = devm_ioremap(&pdev->dev, res->start, 838 resource_size(res)); 839 if (!acdev->vbase) { 840 dev_warn(&pdev->dev, "ioremap fail\n"); 841 return -ENOMEM; 842 } 843 844 acdev->clk = devm_clk_get(&pdev->dev, NULL); 845 if (IS_ERR(acdev->clk)) { 846 dev_warn(&pdev->dev, "Clock not found\n"); 847 return PTR_ERR(acdev->clk); 848 } 849 850 /* allocate host */ 851 host = ata_host_alloc(&pdev->dev, 1); 852 if (!host) { 853 dev_warn(&pdev->dev, "alloc host fail\n"); 854 return -ENOMEM; 855 } 856 857 ap = host->ports[0]; 858 host->private_data = acdev; 859 acdev->host = host; 860 ap->ops = &arasan_cf_ops; 861 ap->pio_mask = ATA_PIO6; 862 ap->mwdma_mask = ATA_MWDMA4; 863 ap->udma_mask = ATA_UDMA6; 864 865 init_completion(&acdev->cf_completion); 866 init_completion(&acdev->dma_completion); 867 INIT_WORK(&acdev->work, data_xfer); 868 INIT_DELAYED_WORK(&acdev->dwork, delayed_finish); 869 dma_cap_set(DMA_MEMCPY, acdev->mask); 870 871 /* Handle platform specific quirks */ 872 if (quirk) { 873 if (quirk & CF_BROKEN_PIO) { 874 ap->ops->set_piomode = NULL; 875 ap->pio_mask = 0; 876 } 877 if (quirk & CF_BROKEN_MWDMA) 878 ap->mwdma_mask = 0; 879 if (quirk & CF_BROKEN_UDMA) 880 ap->udma_mask = 0; 881 } 882 ap->flags |= ATA_FLAG_PIO_POLLING | ATA_FLAG_NO_ATAPI; 883 884 ap->ioaddr.cmd_addr = acdev->vbase + ATA_DATA_PORT; 885 ap->ioaddr.data_addr = acdev->vbase + ATA_DATA_PORT; 886 ap->ioaddr.error_addr = acdev->vbase + ATA_ERR_FTR; 887 ap->ioaddr.feature_addr = acdev->vbase + ATA_ERR_FTR; 888 ap->ioaddr.nsect_addr = acdev->vbase + ATA_SC; 889 ap->ioaddr.lbal_addr = acdev->vbase + ATA_SN; 890 ap->ioaddr.lbam_addr = acdev->vbase + ATA_CL; 891 ap->ioaddr.lbah_addr = acdev->vbase + ATA_CH; 892 ap->ioaddr.device_addr = acdev->vbase + ATA_SH; 893 ap->ioaddr.status_addr = acdev->vbase + ATA_STS_CMD; 894 ap->ioaddr.command_addr = acdev->vbase + ATA_STS_CMD; 895 ap->ioaddr.altstatus_addr = acdev->vbase + ATA_ASTS_DCTR; 896 ap->ioaddr.ctl_addr = acdev->vbase + ATA_ASTS_DCTR; 897 898 ata_port_desc(ap, "phy_addr %llx virt_addr %p", 899 (unsigned long long) res->start, acdev->vbase); 900 901 ret = cf_init(acdev); 902 if (ret) 903 return ret; 904 905 cf_card_detect(acdev, 0); 906 907 ret = ata_host_activate(host, acdev->irq, irq_handler, 0, 908 &arasan_cf_sht); 909 if (!ret) 910 return 0; 911 912 cf_exit(acdev); 913 914 return ret; 915} 916 917static int arasan_cf_remove(struct platform_device *pdev) 918{ 919 struct ata_host *host = platform_get_drvdata(pdev); 920 struct arasan_cf_dev *acdev = host->ports[0]->private_data; 921 922 ata_host_detach(host); 923 cf_exit(acdev); 924 925 return 0; 926} 927 928#ifdef CONFIG_PM_SLEEP 929static int arasan_cf_suspend(struct device *dev) 930{ 931 struct ata_host *host = dev_get_drvdata(dev); 932 struct arasan_cf_dev *acdev = host->ports[0]->private_data; 933 934 if (acdev->dma_chan) 935 dmaengine_terminate_all(acdev->dma_chan); 936 937 cf_exit(acdev); 938 return ata_host_suspend(host, PMSG_SUSPEND); 939} 940 941static int arasan_cf_resume(struct device *dev) 942{ 943 struct ata_host *host = dev_get_drvdata(dev); 944 struct arasan_cf_dev *acdev = host->ports[0]->private_data; 945 946 cf_init(acdev); 947 ata_host_resume(host); 948 949 return 0; 950} 951#endif 952 953static SIMPLE_DEV_PM_OPS(arasan_cf_pm_ops, arasan_cf_suspend, arasan_cf_resume); 954 955#ifdef CONFIG_OF 956static const struct of_device_id arasan_cf_id_table[] = { 957 { .compatible = "arasan,cf-spear1340" }, 958 {} 959}; 960MODULE_DEVICE_TABLE(of, arasan_cf_id_table); 961#endif 962 963static struct platform_driver arasan_cf_driver = { 964 .probe = arasan_cf_probe, 965 .remove = arasan_cf_remove, 966 .driver = { 967 .name = DRIVER_NAME, 968 .pm = &arasan_cf_pm_ops, 969 .of_match_table = of_match_ptr(arasan_cf_id_table), 970 }, 971}; 972 973module_platform_driver(arasan_cf_driver); 974 975MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>"); 976MODULE_DESCRIPTION("Arasan ATA Compact Flash driver"); 977MODULE_LICENSE("GPL"); 978MODULE_ALIAS("platform:" DRIVER_NAME); 979