1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * ahci.c - AHCI SATA support 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004-2005 Red Hat, Inc. 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * AHCI hardware documentation: 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 17 */ 18 19#include <linux/kernel.h> 20#include <linux/module.h> 21#include <linux/pci.h> 22#include <linux/blkdev.h> 23#include <linux/delay.h> 24#include <linux/interrupt.h> 25#include <linux/dma-mapping.h> 26#include <linux/device.h> 27#include <linux/dmi.h> 28#include <linux/gfp.h> 29#include <linux/msi.h> 30#include <scsi/scsi_host.h> 31#include <scsi/scsi_cmnd.h> 32#include <linux/libata.h> 33#include <linux/ahci-remap.h> 34#include <linux/io-64-nonatomic-lo-hi.h> 35#include "ahci.h" 36 37#define DRV_NAME "ahci" 38#define DRV_VERSION "3.0" 39 40enum { 41 AHCI_PCI_BAR_STA2X11 = 0, 42 AHCI_PCI_BAR_CAVIUM = 0, 43 AHCI_PCI_BAR_LOONGSON = 0, 44 AHCI_PCI_BAR_ENMOTUS = 2, 45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4, 46 AHCI_PCI_BAR_STANDARD = 5, 47}; 48 49enum board_ids { 50 /* board IDs by feature in alphabetical order */ 51 board_ahci, 52 board_ahci_ign_iferr, 53 board_ahci_low_power, 54 board_ahci_no_debounce_delay, 55 board_ahci_nomsi, 56 board_ahci_noncq, 57 board_ahci_nosntf, 58 board_ahci_yes_fbs, 59 60 /* board IDs for specific chipsets in alphabetical order */ 61 board_ahci_al, 62 board_ahci_avn, 63 board_ahci_mcp65, 64 board_ahci_mcp77, 65 board_ahci_mcp89, 66 board_ahci_mv, 67 board_ahci_sb600, 68 board_ahci_sb700, /* for SB700 and SB800 */ 69 board_ahci_vt8251, 70 71 /* 72 * board IDs for Intel chipsets that support more than 6 ports 73 * *and* end up needing the PCS quirk. 74 */ 75 board_ahci_pcs7, 76 77 /* aliases */ 78 board_ahci_mcp_linux = board_ahci_mcp65, 79 board_ahci_mcp67 = board_ahci_mcp65, 80 board_ahci_mcp73 = board_ahci_mcp65, 81 board_ahci_mcp79 = board_ahci_mcp77, 82}; 83 84static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 85static void ahci_remove_one(struct pci_dev *dev); 86static void ahci_shutdown_one(struct pci_dev *dev); 87static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv); 88static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 89 unsigned long deadline); 90static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 91 unsigned long deadline); 92static void ahci_mcp89_apple_enable(struct pci_dev *pdev); 93static bool is_mcp89_apple(struct pci_dev *pdev); 94static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 95 unsigned long deadline); 96#ifdef CONFIG_PM 97static int ahci_pci_device_runtime_suspend(struct device *dev); 98static int ahci_pci_device_runtime_resume(struct device *dev); 99#ifdef CONFIG_PM_SLEEP 100static int ahci_pci_device_suspend(struct device *dev); 101static int ahci_pci_device_resume(struct device *dev); 102#endif 103#endif /* CONFIG_PM */ 104 105static struct scsi_host_template ahci_sht = { 106 AHCI_SHT("ahci"), 107}; 108 109static struct ata_port_operations ahci_vt8251_ops = { 110 .inherits = &ahci_ops, 111 .hardreset = ahci_vt8251_hardreset, 112}; 113 114static struct ata_port_operations ahci_p5wdh_ops = { 115 .inherits = &ahci_ops, 116 .hardreset = ahci_p5wdh_hardreset, 117}; 118 119static struct ata_port_operations ahci_avn_ops = { 120 .inherits = &ahci_ops, 121 .hardreset = ahci_avn_hardreset, 122}; 123 124static const struct ata_port_info ahci_port_info[] = { 125 /* by features */ 126 [board_ahci] = { 127 .flags = AHCI_FLAG_COMMON, 128 .pio_mask = ATA_PIO4, 129 .udma_mask = ATA_UDMA6, 130 .port_ops = &ahci_ops, 131 }, 132 [board_ahci_ign_iferr] = { 133 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 134 .flags = AHCI_FLAG_COMMON, 135 .pio_mask = ATA_PIO4, 136 .udma_mask = ATA_UDMA6, 137 .port_ops = &ahci_ops, 138 }, 139 [board_ahci_low_power] = { 140 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE), 141 .flags = AHCI_FLAG_COMMON, 142 .pio_mask = ATA_PIO4, 143 .udma_mask = ATA_UDMA6, 144 .port_ops = &ahci_ops, 145 }, 146 [board_ahci_no_debounce_delay] = { 147 .flags = AHCI_FLAG_COMMON, 148 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY, 149 .pio_mask = ATA_PIO4, 150 .udma_mask = ATA_UDMA6, 151 .port_ops = &ahci_ops, 152 }, 153 [board_ahci_nomsi] = { 154 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), 155 .flags = AHCI_FLAG_COMMON, 156 .pio_mask = ATA_PIO4, 157 .udma_mask = ATA_UDMA6, 158 .port_ops = &ahci_ops, 159 }, 160 [board_ahci_noncq] = { 161 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), 162 .flags = AHCI_FLAG_COMMON, 163 .pio_mask = ATA_PIO4, 164 .udma_mask = ATA_UDMA6, 165 .port_ops = &ahci_ops, 166 }, 167 [board_ahci_nosntf] = { 168 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), 169 .flags = AHCI_FLAG_COMMON, 170 .pio_mask = ATA_PIO4, 171 .udma_mask = ATA_UDMA6, 172 .port_ops = &ahci_ops, 173 }, 174 [board_ahci_yes_fbs] = { 175 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), 176 .flags = AHCI_FLAG_COMMON, 177 .pio_mask = ATA_PIO4, 178 .udma_mask = ATA_UDMA6, 179 .port_ops = &ahci_ops, 180 }, 181 /* by chipsets */ 182 [board_ahci_al] = { 183 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI), 184 .flags = AHCI_FLAG_COMMON, 185 .pio_mask = ATA_PIO4, 186 .udma_mask = ATA_UDMA6, 187 .port_ops = &ahci_ops, 188 }, 189 [board_ahci_avn] = { 190 .flags = AHCI_FLAG_COMMON, 191 .pio_mask = ATA_PIO4, 192 .udma_mask = ATA_UDMA6, 193 .port_ops = &ahci_avn_ops, 194 }, 195 [board_ahci_mcp65] = { 196 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 197 AHCI_HFLAG_YES_NCQ), 198 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 199 .pio_mask = ATA_PIO4, 200 .udma_mask = ATA_UDMA6, 201 .port_ops = &ahci_ops, 202 }, 203 [board_ahci_mcp77] = { 204 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), 205 .flags = AHCI_FLAG_COMMON, 206 .pio_mask = ATA_PIO4, 207 .udma_mask = ATA_UDMA6, 208 .port_ops = &ahci_ops, 209 }, 210 [board_ahci_mcp89] = { 211 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), 212 .flags = AHCI_FLAG_COMMON, 213 .pio_mask = ATA_PIO4, 214 .udma_mask = ATA_UDMA6, 215 .port_ops = &ahci_ops, 216 }, 217 [board_ahci_mv] = { 218 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 219 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 220 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 221 .pio_mask = ATA_PIO4, 222 .udma_mask = ATA_UDMA6, 223 .port_ops = &ahci_ops, 224 }, 225 [board_ahci_sb600] = { 226 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 227 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | 228 AHCI_HFLAG_32BIT_ONLY), 229 .flags = AHCI_FLAG_COMMON, 230 .pio_mask = ATA_PIO4, 231 .udma_mask = ATA_UDMA6, 232 .port_ops = &ahci_pmp_retry_srst_ops, 233 }, 234 [board_ahci_sb700] = { /* for SB700 and SB800 */ 235 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 236 .flags = AHCI_FLAG_COMMON, 237 .pio_mask = ATA_PIO4, 238 .udma_mask = ATA_UDMA6, 239 .port_ops = &ahci_pmp_retry_srst_ops, 240 }, 241 [board_ahci_vt8251] = { 242 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 243 .flags = AHCI_FLAG_COMMON, 244 .pio_mask = ATA_PIO4, 245 .udma_mask = ATA_UDMA6, 246 .port_ops = &ahci_vt8251_ops, 247 }, 248 [board_ahci_pcs7] = { 249 .flags = AHCI_FLAG_COMMON, 250 .pio_mask = ATA_PIO4, 251 .udma_mask = ATA_UDMA6, 252 .port_ops = &ahci_ops, 253 }, 254}; 255 256static const struct pci_device_id ahci_pci_tbl[] = { 257 /* Intel */ 258 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */ 259 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 260 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 261 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 262 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 263 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 264 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 265 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 266 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 267 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 268 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 269 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ 270 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */ 271 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 272 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 273 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 274 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ 275 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ 276 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ 277 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ 278 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ 279 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */ 280 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */ 281 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */ 282 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */ 283 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */ 284 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ 285 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */ 286 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ 287 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ 288 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ 289 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ 290 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ 291 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ 292 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ 293 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ 294 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ 295 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */ 296 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ 297 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */ 298 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ 299 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */ 300 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */ 301 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */ 302 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */ 303 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */ 304 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */ 305 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */ 306 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */ 307 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */ 308 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */ 309 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */ 310 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */ 311 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */ 312 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */ 313 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */ 314 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */ 315 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */ 316 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */ 317 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */ 318 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */ 319 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ 320 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */ 321 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ 322 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */ 323 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ 324 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ 325 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ 326 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ 327 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ 328 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */ 329 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ 330 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ 331 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */ 332 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ 333 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ 334 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ 335 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */ 336 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ 337 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ 338 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */ 339 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ 340 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */ 341 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ 342 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */ 343 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ 344 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */ 345 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */ 346 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */ 347 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */ 348 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */ 349 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */ 350 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */ 351 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */ 352 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */ 353 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */ 354 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ 355 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ 356 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ 357 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ 358 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ 359 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ 360 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ 361 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ 362 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ 363 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ 364 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ 365 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ 366 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ 367 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ 368 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ 369 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ 370 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */ 371 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */ 372 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */ 373 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */ 374 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */ 375 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */ 376 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ 377 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ 378 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ 379 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ 380 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ 381 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ 382 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ 383 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ 384 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ 385 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */ 386 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */ 387 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */ 388 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */ 389 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ 390 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */ 391 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ 392 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */ 393 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ 394 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */ 395 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ 396 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */ 397 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */ 398 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */ 399 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */ 400 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */ 401 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */ 402 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ 403 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */ 404 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */ 405 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ 406 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/ 407 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/ 408 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/ 409 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/ 410 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/ 411 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/ 412 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/ 413 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/ 414 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/ 415 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/ 416 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/ 417 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/ 418 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */ 419 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */ 420 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */ 421 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */ 422 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */ 423 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */ 424 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */ 425 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */ 426 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */ 427 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */ 428 /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */ 429 { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_low_power }, /* Elkhart Lake AHCI */ 430 431 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 432 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 433 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 434 /* JMicron 362B and 362C have an AHCI function with IDE class code */ 435 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, 436 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, 437 /* May need to update quirk_jmicron_async_suspend() for additions */ 438 439 /* ATI */ 440 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 441 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 442 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 443 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 444 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 445 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 446 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 447 448 /* Amazon's Annapurna Labs support */ 449 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031), 450 .class = PCI_CLASS_STORAGE_SATA_AHCI, 451 .class_mask = 0xffffff, 452 board_ahci_al }, 453 /* AMD */ 454 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ 455 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */ 456 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ 457 { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */ 458 /* AMD is using RAID class only for ahci controllers */ 459 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 460 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 461 462 /* VIA */ 463 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 464 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 465 466 /* NVIDIA */ 467 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 468 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 469 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 470 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 471 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 472 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 473 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 474 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 475 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ 476 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ 477 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ 478 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ 479 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ 480 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ 481 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ 482 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ 483 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ 484 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ 485 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ 486 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ 487 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ 488 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ 489 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ 490 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ 491 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ 492 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ 493 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ 494 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ 495 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ 496 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ 497 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ 498 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ 499 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ 500 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ 501 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ 502 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ 503 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ 504 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ 505 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ 506 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ 507 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ 508 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ 509 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ 510 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ 511 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ 512 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ 513 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ 514 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ 515 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ 516 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ 517 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ 518 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ 519 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ 520 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ 521 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ 522 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ 523 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ 524 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ 525 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ 526 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ 527 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ 528 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ 529 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ 530 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ 531 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ 532 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ 533 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ 534 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ 535 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ 536 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ 537 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ 538 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ 539 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ 540 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ 541 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ 542 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ 543 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ 544 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ 545 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ 546 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ 547 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ 548 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ 549 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ 550 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ 551 552 /* SiS */ 553 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 554 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 555 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 556 557 /* ST Microelectronics */ 558 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ 559 560 /* Marvell */ 561 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 562 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 563 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), 564 .class = PCI_CLASS_STORAGE_SATA_AHCI, 565 .class_mask = 0xffffff, 566 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ 567 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), 568 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ 569 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, 570 PCI_VENDOR_ID_MARVELL_EXT, 0x9170), 571 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ 572 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), 573 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 574 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), 575 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ 576 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), 577 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 578 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), 579 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ 580 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), 581 .driver_data = board_ahci_yes_fbs }, 582 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */ 583 .driver_data = board_ahci_yes_fbs }, 584 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), 585 .driver_data = board_ahci_yes_fbs }, 586 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), 587 .driver_data = board_ahci_yes_fbs }, 588 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */ 589 .driver_data = board_ahci_yes_fbs }, 590 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */ 591 .driver_data = board_ahci_yes_fbs }, 592 593 /* Promise */ 594 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 595 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ 596 597 /* Asmedia */ 598 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ 599 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ 600 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ 601 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ 602 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */ 603 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */ 604 605 /* 606 * Samsung SSDs found on some macbooks. NCQ times out if MSI is 607 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 608 */ 609 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi }, 610 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi }, 611 612 /* Enmotus */ 613 { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, 614 615 /* Loongson */ 616 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci }, 617 618 /* Generic, PCI class code for AHCI */ 619 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 620 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 621 622 { } /* terminate list */ 623}; 624 625static const struct dev_pm_ops ahci_pci_pm_ops = { 626 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume) 627 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend, 628 ahci_pci_device_runtime_resume, NULL) 629}; 630 631static struct pci_driver ahci_pci_driver = { 632 .name = DRV_NAME, 633 .id_table = ahci_pci_tbl, 634 .probe = ahci_init_one, 635 .remove = ahci_remove_one, 636 .shutdown = ahci_shutdown_one, 637 .driver = { 638 .pm = &ahci_pci_pm_ops, 639 }, 640}; 641 642#if IS_ENABLED(CONFIG_PATA_MARVELL) 643static int marvell_enable; 644#else 645static int marvell_enable = 1; 646#endif 647module_param(marvell_enable, int, 0644); 648MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 649 650static int mobile_lpm_policy = -1; 651module_param(mobile_lpm_policy, int, 0644); 652MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets"); 653 654static void ahci_pci_save_initial_config(struct pci_dev *pdev, 655 struct ahci_host_priv *hpriv) 656{ 657 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { 658 dev_info(&pdev->dev, "JMB361 has only one port\n"); 659 hpriv->force_port_map = 1; 660 } 661 662 /* 663 * Temporary Marvell 6145 hack: PATA port presence 664 * is asserted through the standard AHCI port 665 * presence register, as bit 4 (counting from 0) 666 */ 667 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 668 if (pdev->device == 0x6121) 669 hpriv->mask_port_map = 0x3; 670 else 671 hpriv->mask_port_map = 0xf; 672 dev_info(&pdev->dev, 673 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 674 } 675 676 ahci_save_initial_config(&pdev->dev, hpriv); 677} 678 679static int ahci_pci_reset_controller(struct ata_host *host) 680{ 681 struct pci_dev *pdev = to_pci_dev(host->dev); 682 struct ahci_host_priv *hpriv = host->private_data; 683 int rc; 684 685 rc = ahci_reset_controller(host); 686 if (rc) 687 return rc; 688 689 /* 690 * If platform firmware failed to enable ports, try to enable 691 * them here. 692 */ 693 ahci_intel_pcs_quirk(pdev, hpriv); 694 695 return 0; 696} 697 698static void ahci_pci_init_controller(struct ata_host *host) 699{ 700 struct ahci_host_priv *hpriv = host->private_data; 701 struct pci_dev *pdev = to_pci_dev(host->dev); 702 void __iomem *port_mmio; 703 u32 tmp; 704 int mv; 705 706 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 707 if (pdev->device == 0x6121) 708 mv = 2; 709 else 710 mv = 4; 711 port_mmio = __ahci_port_base(host, mv); 712 713 writel(0, port_mmio + PORT_IRQ_MASK); 714 715 /* clear port IRQ */ 716 tmp = readl(port_mmio + PORT_IRQ_STAT); 717 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp); 718 if (tmp) 719 writel(tmp, port_mmio + PORT_IRQ_STAT); 720 } 721 722 ahci_init_controller(host); 723} 724 725static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 726 unsigned long deadline) 727{ 728 struct ata_port *ap = link->ap; 729 struct ahci_host_priv *hpriv = ap->host->private_data; 730 bool online; 731 int rc; 732 733 DPRINTK("ENTER\n"); 734 735 hpriv->stop_engine(ap); 736 737 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 738 deadline, &online, NULL); 739 740 hpriv->start_engine(ap); 741 742 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 743 744 /* vt8251 doesn't clear BSY on signature FIS reception, 745 * request follow-up softreset. 746 */ 747 return online ? -EAGAIN : rc; 748} 749 750static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 751 unsigned long deadline) 752{ 753 struct ata_port *ap = link->ap; 754 struct ahci_port_priv *pp = ap->private_data; 755 struct ahci_host_priv *hpriv = ap->host->private_data; 756 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 757 struct ata_taskfile tf; 758 bool online; 759 int rc; 760 761 hpriv->stop_engine(ap); 762 763 /* clear D2H reception area to properly wait for D2H FIS */ 764 ata_tf_init(link->device, &tf); 765 tf.command = ATA_BUSY; 766 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 767 768 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 769 deadline, &online, NULL); 770 771 hpriv->start_engine(ap); 772 773 /* The pseudo configuration device on SIMG4726 attached to 774 * ASUS P5W-DH Deluxe doesn't send signature FIS after 775 * hardreset if no device is attached to the first downstream 776 * port && the pseudo device locks up on SRST w/ PMP==0. To 777 * work around this, wait for !BSY only briefly. If BSY isn't 778 * cleared, perform CLO and proceed to IDENTIFY (achieved by 779 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 780 * 781 * Wait for two seconds. Devices attached to downstream port 782 * which can't process the following IDENTIFY after this will 783 * have to be reset again. For most cases, this should 784 * suffice while making probing snappish enough. 785 */ 786 if (online) { 787 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 788 ahci_check_ready); 789 if (rc) 790 ahci_kick_engine(ap); 791 } 792 return rc; 793} 794 795/* 796 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. 797 * 798 * It has been observed with some SSDs that the timing of events in the 799 * link synchronization phase can leave the port in a state that can not 800 * be recovered by a SATA-hard-reset alone. The failing signature is 801 * SStatus.DET stuck at 1 ("Device presence detected but Phy 802 * communication not established"). It was found that unloading and 803 * reloading the driver when this problem occurs allows the drive 804 * connection to be recovered (DET advanced to 0x3). The critical 805 * component of reloading the driver is that the port state machines are 806 * reset by bouncing "port enable" in the AHCI PCS configuration 807 * register. So, reproduce that effect by bouncing a port whenever we 808 * see DET==1 after a reset. 809 */ 810static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 811 unsigned long deadline) 812{ 813 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 814 struct ata_port *ap = link->ap; 815 struct ahci_port_priv *pp = ap->private_data; 816 struct ahci_host_priv *hpriv = ap->host->private_data; 817 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 818 unsigned long tmo = deadline - jiffies; 819 struct ata_taskfile tf; 820 bool online; 821 int rc, i; 822 823 DPRINTK("ENTER\n"); 824 825 hpriv->stop_engine(ap); 826 827 for (i = 0; i < 2; i++) { 828 u16 val; 829 u32 sstatus; 830 int port = ap->port_no; 831 struct ata_host *host = ap->host; 832 struct pci_dev *pdev = to_pci_dev(host->dev); 833 834 /* clear D2H reception area to properly wait for D2H FIS */ 835 ata_tf_init(link->device, &tf); 836 tf.command = ATA_BUSY; 837 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 838 839 rc = sata_link_hardreset(link, timing, deadline, &online, 840 ahci_check_ready); 841 842 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || 843 (sstatus & 0xf) != 1) 844 break; 845 846 ata_link_info(link, "avn bounce port%d\n", port); 847 848 pci_read_config_word(pdev, 0x92, &val); 849 val &= ~(1 << port); 850 pci_write_config_word(pdev, 0x92, val); 851 ata_msleep(ap, 1000); 852 val |= 1 << port; 853 pci_write_config_word(pdev, 0x92, val); 854 deadline += tmo; 855 } 856 857 hpriv->start_engine(ap); 858 859 if (online) 860 *class = ahci_dev_classify(ap); 861 862 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 863 return rc; 864} 865 866 867#ifdef CONFIG_PM 868static void ahci_pci_disable_interrupts(struct ata_host *host) 869{ 870 struct ahci_host_priv *hpriv = host->private_data; 871 void __iomem *mmio = hpriv->mmio; 872 u32 ctl; 873 874 /* AHCI spec rev1.1 section 8.3.3: 875 * Software must disable interrupts prior to requesting a 876 * transition of the HBA to D3 state. 877 */ 878 ctl = readl(mmio + HOST_CTL); 879 ctl &= ~HOST_IRQ_EN; 880 writel(ctl, mmio + HOST_CTL); 881 readl(mmio + HOST_CTL); /* flush */ 882} 883 884static int ahci_pci_device_runtime_suspend(struct device *dev) 885{ 886 struct pci_dev *pdev = to_pci_dev(dev); 887 struct ata_host *host = pci_get_drvdata(pdev); 888 889 ahci_pci_disable_interrupts(host); 890 return 0; 891} 892 893static int ahci_pci_device_runtime_resume(struct device *dev) 894{ 895 struct pci_dev *pdev = to_pci_dev(dev); 896 struct ata_host *host = pci_get_drvdata(pdev); 897 int rc; 898 899 rc = ahci_pci_reset_controller(host); 900 if (rc) 901 return rc; 902 ahci_pci_init_controller(host); 903 return 0; 904} 905 906#ifdef CONFIG_PM_SLEEP 907static int ahci_pci_device_suspend(struct device *dev) 908{ 909 struct pci_dev *pdev = to_pci_dev(dev); 910 struct ata_host *host = pci_get_drvdata(pdev); 911 struct ahci_host_priv *hpriv = host->private_data; 912 913 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 914 dev_err(&pdev->dev, 915 "BIOS update required for suspend/resume\n"); 916 return -EIO; 917 } 918 919 ahci_pci_disable_interrupts(host); 920 return ata_host_suspend(host, PMSG_SUSPEND); 921} 922 923static int ahci_pci_device_resume(struct device *dev) 924{ 925 struct pci_dev *pdev = to_pci_dev(dev); 926 struct ata_host *host = pci_get_drvdata(pdev); 927 int rc; 928 929 /* Apple BIOS helpfully mangles the registers on resume */ 930 if (is_mcp89_apple(pdev)) 931 ahci_mcp89_apple_enable(pdev); 932 933 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 934 rc = ahci_pci_reset_controller(host); 935 if (rc) 936 return rc; 937 938 ahci_pci_init_controller(host); 939 } 940 941 ata_host_resume(host); 942 943 return 0; 944} 945#endif 946 947#endif /* CONFIG_PM */ 948 949static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) 950{ 951 const int dma_bits = using_dac ? 64 : 32; 952 int rc; 953 954 /* 955 * If the device fixup already set the dma_mask to some non-standard 956 * value, don't extend it here. This happens on STA2X11, for example. 957 * 958 * XXX: manipulating the DMA mask from platform code is completely 959 * bogus, platform code should use dev->bus_dma_limit instead.. 960 */ 961 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) 962 return 0; 963 964 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits)); 965 if (rc) 966 dev_err(&pdev->dev, "DMA enable failed\n"); 967 return rc; 968} 969 970static void ahci_pci_print_info(struct ata_host *host) 971{ 972 struct pci_dev *pdev = to_pci_dev(host->dev); 973 u16 cc; 974 const char *scc_s; 975 976 pci_read_config_word(pdev, 0x0a, &cc); 977 if (cc == PCI_CLASS_STORAGE_IDE) 978 scc_s = "IDE"; 979 else if (cc == PCI_CLASS_STORAGE_SATA) 980 scc_s = "SATA"; 981 else if (cc == PCI_CLASS_STORAGE_RAID) 982 scc_s = "RAID"; 983 else 984 scc_s = "unknown"; 985 986 ahci_print_info(host, scc_s); 987} 988 989/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 990 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 991 * support PMP and the 4726 either directly exports the device 992 * attached to the first downstream port or acts as a hardware storage 993 * controller and emulate a single ATA device (can be RAID 0/1 or some 994 * other configuration). 995 * 996 * When there's no device attached to the first downstream port of the 997 * 4726, "Config Disk" appears, which is a pseudo ATA device to 998 * configure the 4726. However, ATA emulation of the device is very 999 * lame. It doesn't send signature D2H Reg FIS after the initial 1000 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 1001 * 1002 * The following function works around the problem by always using 1003 * hardreset on the port and not depending on receiving signature FIS 1004 * afterward. If signature FIS isn't received soon, ATA class is 1005 * assumed without follow-up softreset. 1006 */ 1007static void ahci_p5wdh_workaround(struct ata_host *host) 1008{ 1009 static const struct dmi_system_id sysids[] = { 1010 { 1011 .ident = "P5W DH Deluxe", 1012 .matches = { 1013 DMI_MATCH(DMI_SYS_VENDOR, 1014 "ASUSTEK COMPUTER INC"), 1015 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 1016 }, 1017 }, 1018 { } 1019 }; 1020 struct pci_dev *pdev = to_pci_dev(host->dev); 1021 1022 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 1023 dmi_check_system(sysids)) { 1024 struct ata_port *ap = host->ports[1]; 1025 1026 dev_info(&pdev->dev, 1027 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); 1028 1029 ap->ops = &ahci_p5wdh_ops; 1030 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 1031 } 1032} 1033 1034/* 1035 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when 1036 * booting in BIOS compatibility mode. We restore the registers but not ID. 1037 */ 1038static void ahci_mcp89_apple_enable(struct pci_dev *pdev) 1039{ 1040 u32 val; 1041 1042 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); 1043 1044 pci_read_config_dword(pdev, 0xf8, &val); 1045 val |= 1 << 0x1b; 1046 /* the following changes the device ID, but appears not to affect function */ 1047 /* val = (val & ~0xf0000000) | 0x80000000; */ 1048 pci_write_config_dword(pdev, 0xf8, val); 1049 1050 pci_read_config_dword(pdev, 0x54c, &val); 1051 val |= 1 << 0xc; 1052 pci_write_config_dword(pdev, 0x54c, val); 1053 1054 pci_read_config_dword(pdev, 0x4a4, &val); 1055 val &= 0xff; 1056 val |= 0x01060100; 1057 pci_write_config_dword(pdev, 0x4a4, val); 1058 1059 pci_read_config_dword(pdev, 0x54c, &val); 1060 val &= ~(1 << 0xc); 1061 pci_write_config_dword(pdev, 0x54c, val); 1062 1063 pci_read_config_dword(pdev, 0xf8, &val); 1064 val &= ~(1 << 0x1b); 1065 pci_write_config_dword(pdev, 0xf8, val); 1066} 1067 1068static bool is_mcp89_apple(struct pci_dev *pdev) 1069{ 1070 return pdev->vendor == PCI_VENDOR_ID_NVIDIA && 1071 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && 1072 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1073 pdev->subsystem_device == 0xcb89; 1074} 1075 1076/* only some SB600 ahci controllers can do 64bit DMA */ 1077static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 1078{ 1079 static const struct dmi_system_id sysids[] = { 1080 /* 1081 * The oldest version known to be broken is 0901 and 1082 * working is 1501 which was released on 2007-10-26. 1083 * Enable 64bit DMA on 1501 and anything newer. 1084 * 1085 * Please read bko#9412 for more info. 1086 */ 1087 { 1088 .ident = "ASUS M2A-VM", 1089 .matches = { 1090 DMI_MATCH(DMI_BOARD_VENDOR, 1091 "ASUSTeK Computer INC."), 1092 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 1093 }, 1094 .driver_data = "20071026", /* yyyymmdd */ 1095 }, 1096 /* 1097 * All BIOS versions for the MSI K9A2 Platinum (MS-7376) 1098 * support 64bit DMA. 1099 * 1100 * BIOS versions earlier than 1.5 had the Manufacturer DMI 1101 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". 1102 * This spelling mistake was fixed in BIOS version 1.5, so 1103 * 1.5 and later have the Manufacturer as 1104 * "MICRO-STAR INTERNATIONAL CO.,LTD". 1105 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". 1106 * 1107 * BIOS versions earlier than 1.9 had a Board Product Name 1108 * DMI field of "MS-7376". This was changed to be 1109 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still 1110 * match on DMI_BOARD_NAME of "MS-7376". 1111 */ 1112 { 1113 .ident = "MSI K9A2 Platinum", 1114 .matches = { 1115 DMI_MATCH(DMI_BOARD_VENDOR, 1116 "MICRO-STAR INTER"), 1117 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), 1118 }, 1119 }, 1120 /* 1121 * All BIOS versions for the MSI K9AGM2 (MS-7327) support 1122 * 64bit DMA. 1123 * 1124 * This board also had the typo mentioned above in the 1125 * Manufacturer DMI field (fixed in BIOS version 1.5), so 1126 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. 1127 */ 1128 { 1129 .ident = "MSI K9AGM2", 1130 .matches = { 1131 DMI_MATCH(DMI_BOARD_VENDOR, 1132 "MICRO-STAR INTER"), 1133 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), 1134 }, 1135 }, 1136 /* 1137 * All BIOS versions for the Asus M3A support 64bit DMA. 1138 * (all release versions from 0301 to 1206 were tested) 1139 */ 1140 { 1141 .ident = "ASUS M3A", 1142 .matches = { 1143 DMI_MATCH(DMI_BOARD_VENDOR, 1144 "ASUSTeK Computer INC."), 1145 DMI_MATCH(DMI_BOARD_NAME, "M3A"), 1146 }, 1147 }, 1148 { } 1149 }; 1150 const struct dmi_system_id *match; 1151 int year, month, date; 1152 char buf[9]; 1153 1154 match = dmi_first_match(sysids); 1155 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 1156 !match) 1157 return false; 1158 1159 if (!match->driver_data) 1160 goto enable_64bit; 1161 1162 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1163 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1164 1165 if (strcmp(buf, match->driver_data) >= 0) 1166 goto enable_64bit; 1167 else { 1168 dev_warn(&pdev->dev, 1169 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", 1170 match->ident); 1171 return false; 1172 } 1173 1174enable_64bit: 1175 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); 1176 return true; 1177} 1178 1179static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 1180{ 1181 static const struct dmi_system_id broken_systems[] = { 1182 { 1183 .ident = "HP Compaq nx6310", 1184 .matches = { 1185 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1186 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 1187 }, 1188 /* PCI slot number of the controller */ 1189 .driver_data = (void *)0x1FUL, 1190 }, 1191 { 1192 .ident = "HP Compaq 6720s", 1193 .matches = { 1194 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1195 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 1196 }, 1197 /* PCI slot number of the controller */ 1198 .driver_data = (void *)0x1FUL, 1199 }, 1200 1201 { } /* terminate list */ 1202 }; 1203 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1204 1205 if (dmi) { 1206 unsigned long slot = (unsigned long)dmi->driver_data; 1207 /* apply the quirk only to on-board controllers */ 1208 return slot == PCI_SLOT(pdev->devfn); 1209 } 1210 1211 return false; 1212} 1213 1214static bool ahci_broken_suspend(struct pci_dev *pdev) 1215{ 1216 static const struct dmi_system_id sysids[] = { 1217 /* 1218 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 1219 * to the harddisk doesn't become online after 1220 * resuming from STR. Warn and fail suspend. 1221 * 1222 * http://bugzilla.kernel.org/show_bug.cgi?id=12276 1223 * 1224 * Use dates instead of versions to match as HP is 1225 * apparently recycling both product and version 1226 * strings. 1227 * 1228 * http://bugzilla.kernel.org/show_bug.cgi?id=15462 1229 */ 1230 { 1231 .ident = "dv4", 1232 .matches = { 1233 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1234 DMI_MATCH(DMI_PRODUCT_NAME, 1235 "HP Pavilion dv4 Notebook PC"), 1236 }, 1237 .driver_data = "20090105", /* F.30 */ 1238 }, 1239 { 1240 .ident = "dv5", 1241 .matches = { 1242 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1243 DMI_MATCH(DMI_PRODUCT_NAME, 1244 "HP Pavilion dv5 Notebook PC"), 1245 }, 1246 .driver_data = "20090506", /* F.16 */ 1247 }, 1248 { 1249 .ident = "dv6", 1250 .matches = { 1251 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1252 DMI_MATCH(DMI_PRODUCT_NAME, 1253 "HP Pavilion dv6 Notebook PC"), 1254 }, 1255 .driver_data = "20090423", /* F.21 */ 1256 }, 1257 { 1258 .ident = "HDX18", 1259 .matches = { 1260 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1261 DMI_MATCH(DMI_PRODUCT_NAME, 1262 "HP HDX18 Notebook PC"), 1263 }, 1264 .driver_data = "20090430", /* F.23 */ 1265 }, 1266 /* 1267 * Acer eMachines G725 has the same problem. BIOS 1268 * V1.03 is known to be broken. V3.04 is known to 1269 * work. Between, there are V1.06, V2.06 and V3.03 1270 * that we don't have much idea about. For now, 1271 * blacklist anything older than V3.04. 1272 * 1273 * http://bugzilla.kernel.org/show_bug.cgi?id=15104 1274 */ 1275 { 1276 .ident = "G725", 1277 .matches = { 1278 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), 1279 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), 1280 }, 1281 .driver_data = "20091216", /* V3.04 */ 1282 }, 1283 { } /* terminate list */ 1284 }; 1285 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1286 int year, month, date; 1287 char buf[9]; 1288 1289 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 1290 return false; 1291 1292 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1293 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1294 1295 return strcmp(buf, dmi->driver_data) < 0; 1296} 1297 1298static bool ahci_broken_lpm(struct pci_dev *pdev) 1299{ 1300 static const struct dmi_system_id sysids[] = { 1301 /* Various Lenovo 50 series have LPM issues with older BIOSen */ 1302 { 1303 .matches = { 1304 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1305 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"), 1306 }, 1307 .driver_data = "20180406", /* 1.31 */ 1308 }, 1309 { 1310 .matches = { 1311 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1312 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"), 1313 }, 1314 .driver_data = "20180420", /* 1.28 */ 1315 }, 1316 { 1317 .matches = { 1318 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1319 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"), 1320 }, 1321 .driver_data = "20180315", /* 1.33 */ 1322 }, 1323 { 1324 .matches = { 1325 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1326 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"), 1327 }, 1328 /* 1329 * Note date based on release notes, 2.35 has been 1330 * reported to be good, but I've been unable to get 1331 * a hold of the reporter to get the DMI BIOS date. 1332 * TODO: fix this. 1333 */ 1334 .driver_data = "20180310", /* 2.35 */ 1335 }, 1336 { } /* terminate list */ 1337 }; 1338 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1339 int year, month, date; 1340 char buf[9]; 1341 1342 if (!dmi) 1343 return false; 1344 1345 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1346 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1347 1348 return strcmp(buf, dmi->driver_data) < 0; 1349} 1350 1351static bool ahci_broken_online(struct pci_dev *pdev) 1352{ 1353#define ENCODE_BUSDEVFN(bus, slot, func) \ 1354 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) 1355 static const struct dmi_system_id sysids[] = { 1356 /* 1357 * There are several gigabyte boards which use 1358 * SIMG5723s configured as hardware RAID. Certain 1359 * 5723 firmware revisions shipped there keep the link 1360 * online but fail to answer properly to SRST or 1361 * IDENTIFY when no device is attached downstream 1362 * causing libata to retry quite a few times leading 1363 * to excessive detection delay. 1364 * 1365 * As these firmwares respond to the second reset try 1366 * with invalid device signature, considering unknown 1367 * sig as offline works around the problem acceptably. 1368 */ 1369 { 1370 .ident = "EP45-DQ6", 1371 .matches = { 1372 DMI_MATCH(DMI_BOARD_VENDOR, 1373 "Gigabyte Technology Co., Ltd."), 1374 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), 1375 }, 1376 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), 1377 }, 1378 { 1379 .ident = "EP45-DS5", 1380 .matches = { 1381 DMI_MATCH(DMI_BOARD_VENDOR, 1382 "Gigabyte Technology Co., Ltd."), 1383 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), 1384 }, 1385 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), 1386 }, 1387 { } /* terminate list */ 1388 }; 1389#undef ENCODE_BUSDEVFN 1390 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1391 unsigned int val; 1392 1393 if (!dmi) 1394 return false; 1395 1396 val = (unsigned long)dmi->driver_data; 1397 1398 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); 1399} 1400 1401static bool ahci_broken_devslp(struct pci_dev *pdev) 1402{ 1403 /* device with broken DEVSLP but still showing SDS capability */ 1404 static const struct pci_device_id ids[] = { 1405 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */ 1406 {} 1407 }; 1408 1409 return pci_match_id(ids, pdev); 1410} 1411 1412#ifdef CONFIG_ATA_ACPI 1413static void ahci_gtf_filter_workaround(struct ata_host *host) 1414{ 1415 static const struct dmi_system_id sysids[] = { 1416 /* 1417 * Aspire 3810T issues a bunch of SATA enable commands 1418 * via _GTF including an invalid one and one which is 1419 * rejected by the device. Among the successful ones 1420 * is FPDMA non-zero offset enable which when enabled 1421 * only on the drive side leads to NCQ command 1422 * failures. Filter it out. 1423 */ 1424 { 1425 .ident = "Aspire 3810T", 1426 .matches = { 1427 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1428 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), 1429 }, 1430 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, 1431 }, 1432 { } 1433 }; 1434 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1435 unsigned int filter; 1436 int i; 1437 1438 if (!dmi) 1439 return; 1440 1441 filter = (unsigned long)dmi->driver_data; 1442 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", 1443 filter, dmi->ident); 1444 1445 for (i = 0; i < host->n_ports; i++) { 1446 struct ata_port *ap = host->ports[i]; 1447 struct ata_link *link; 1448 struct ata_device *dev; 1449 1450 ata_for_each_link(link, ap, EDGE) 1451 ata_for_each_dev(dev, link, ALL) 1452 dev->gtf_filter |= filter; 1453 } 1454} 1455#else 1456static inline void ahci_gtf_filter_workaround(struct ata_host *host) 1457{} 1458#endif 1459 1460/* 1461 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected 1462 * as DUMMY, or detected but eventually get a "link down" and never get up 1463 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the 1464 * port_map may hold a value of 0x00. 1465 * 1466 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports 1467 * and can significantly reduce the occurrence of the problem. 1468 * 1469 * https://bugzilla.kernel.org/show_bug.cgi?id=189471 1470 */ 1471static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv, 1472 struct pci_dev *pdev) 1473{ 1474 static const struct dmi_system_id sysids[] = { 1475 { 1476 .ident = "Acer Switch Alpha 12", 1477 .matches = { 1478 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1479 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271") 1480 }, 1481 }, 1482 { } 1483 }; 1484 1485 if (dmi_check_system(sysids)) { 1486 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n"); 1487 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) { 1488 hpriv->port_map = 0x7; 1489 hpriv->cap = 0xC734FF02; 1490 } 1491 } 1492} 1493 1494#ifdef CONFIG_ARM64 1495/* 1496 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently. 1497 * Workaround is to make sure all pending IRQs are served before leaving 1498 * handler. 1499 */ 1500static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) 1501{ 1502 struct ata_host *host = dev_instance; 1503 struct ahci_host_priv *hpriv; 1504 unsigned int rc = 0; 1505 void __iomem *mmio; 1506 u32 irq_stat, irq_masked; 1507 unsigned int handled = 1; 1508 1509 hpriv = host->private_data; 1510 mmio = hpriv->mmio; 1511 irq_stat = readl(mmio + HOST_IRQ_STAT); 1512 if (!irq_stat) 1513 return IRQ_NONE; 1514 1515 do { 1516 irq_masked = irq_stat & hpriv->port_map; 1517 spin_lock(&host->lock); 1518 rc = ahci_handle_port_intr(host, irq_masked); 1519 if (!rc) 1520 handled = 0; 1521 writel(irq_stat, mmio + HOST_IRQ_STAT); 1522 irq_stat = readl(mmio + HOST_IRQ_STAT); 1523 spin_unlock(&host->lock); 1524 } while (irq_stat); 1525 1526 return IRQ_RETVAL(handled); 1527} 1528#endif 1529 1530static void ahci_remap_check(struct pci_dev *pdev, int bar, 1531 struct ahci_host_priv *hpriv) 1532{ 1533 int i; 1534 u32 cap; 1535 1536 /* 1537 * Check if this device might have remapped nvme devices. 1538 */ 1539 if (pdev->vendor != PCI_VENDOR_ID_INTEL || 1540 pci_resource_len(pdev, bar) < SZ_512K || 1541 bar != AHCI_PCI_BAR_STANDARD || 1542 !(readl(hpriv->mmio + AHCI_VSCAP) & 1)) 1543 return; 1544 1545 cap = readq(hpriv->mmio + AHCI_REMAP_CAP); 1546 for (i = 0; i < AHCI_MAX_REMAP; i++) { 1547 if ((cap & (1 << i)) == 0) 1548 continue; 1549 if (readl(hpriv->mmio + ahci_remap_dcc(i)) 1550 != PCI_CLASS_STORAGE_EXPRESS) 1551 continue; 1552 1553 /* We've found a remapped device */ 1554 hpriv->remapped_nvme++; 1555 } 1556 1557 if (!hpriv->remapped_nvme) 1558 return; 1559 1560 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n", 1561 hpriv->remapped_nvme); 1562 dev_warn(&pdev->dev, 1563 "Switch your BIOS from RAID to AHCI mode to use them.\n"); 1564 1565 /* 1566 * Don't rely on the msi-x capability in the remap case, 1567 * share the legacy interrupt across ahci and remapped devices. 1568 */ 1569 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1570} 1571 1572static int ahci_get_irq_vector(struct ata_host *host, int port) 1573{ 1574 return pci_irq_vector(to_pci_dev(host->dev), port); 1575} 1576 1577static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, 1578 struct ahci_host_priv *hpriv) 1579{ 1580 int nvec; 1581 1582 if (hpriv->flags & AHCI_HFLAG_NO_MSI) 1583 return -ENODEV; 1584 1585 /* 1586 * If number of MSIs is less than number of ports then Sharing Last 1587 * Message mode could be enforced. In this case assume that advantage 1588 * of multipe MSIs is negated and use single MSI mode instead. 1589 */ 1590 if (n_ports > 1) { 1591 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX, 1592 PCI_IRQ_MSIX | PCI_IRQ_MSI); 1593 if (nvec > 0) { 1594 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) { 1595 hpriv->get_irq_vector = ahci_get_irq_vector; 1596 hpriv->flags |= AHCI_HFLAG_MULTI_MSI; 1597 return nvec; 1598 } 1599 1600 /* 1601 * Fallback to single MSI mode if the controller 1602 * enforced MRSM mode. 1603 */ 1604 printk(KERN_INFO 1605 "ahci: MRSM is on, fallback to single MSI\n"); 1606 pci_free_irq_vectors(pdev); 1607 } 1608 } 1609 1610 /* 1611 * If the host is not capable of supporting per-port vectors, fall 1612 * back to single MSI before finally attempting single MSI-X. 1613 */ 1614 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1615 if (nvec == 1) 1616 return nvec; 1617 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX); 1618} 1619 1620static void ahci_update_initial_lpm_policy(struct ata_port *ap, 1621 struct ahci_host_priv *hpriv) 1622{ 1623 int policy = CONFIG_SATA_MOBILE_LPM_POLICY; 1624 1625 1626 /* Ignore processing for non mobile platforms */ 1627 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE)) 1628 return; 1629 1630 /* user modified policy via module param */ 1631 if (mobile_lpm_policy != -1) { 1632 policy = mobile_lpm_policy; 1633 goto update_policy; 1634 } 1635 1636#ifdef CONFIG_ACPI 1637 if (policy > ATA_LPM_MED_POWER && 1638 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) { 1639 if (hpriv->cap & HOST_CAP_PART) 1640 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL; 1641 else if (hpriv->cap & HOST_CAP_SSC) 1642 policy = ATA_LPM_MIN_POWER; 1643 } 1644#endif 1645 1646update_policy: 1647 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER) 1648 ap->target_lpm_policy = policy; 1649} 1650 1651static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv) 1652{ 1653 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev); 1654 u16 tmp16; 1655 1656 /* 1657 * Only apply the 6-port PCS quirk for known legacy platforms. 1658 */ 1659 if (!id || id->vendor != PCI_VENDOR_ID_INTEL) 1660 return; 1661 1662 /* Skip applying the quirk on Denverton and beyond */ 1663 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7) 1664 return; 1665 1666 /* 1667 * port_map is determined from PORTS_IMPL PCI register which is 1668 * implemented as write or write-once register. If the register 1669 * isn't programmed, ahci automatically generates it from number 1670 * of ports, which is good enough for PCS programming. It is 1671 * otherwise expected that platform firmware enables the ports 1672 * before the OS boots. 1673 */ 1674 pci_read_config_word(pdev, PCS_6, &tmp16); 1675 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 1676 tmp16 |= hpriv->port_map; 1677 pci_write_config_word(pdev, PCS_6, tmp16); 1678 } 1679} 1680 1681static ssize_t remapped_nvme_show(struct device *dev, 1682 struct device_attribute *attr, 1683 char *buf) 1684{ 1685 struct ata_host *host = dev_get_drvdata(dev); 1686 struct ahci_host_priv *hpriv = host->private_data; 1687 1688 return sprintf(buf, "%u\n", hpriv->remapped_nvme); 1689} 1690 1691static DEVICE_ATTR_RO(remapped_nvme); 1692 1693static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1694{ 1695 unsigned int board_id = ent->driver_data; 1696 struct ata_port_info pi = ahci_port_info[board_id]; 1697 const struct ata_port_info *ppi[] = { &pi, NULL }; 1698 struct device *dev = &pdev->dev; 1699 struct ahci_host_priv *hpriv; 1700 struct ata_host *host; 1701 int n_ports, i, rc; 1702 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; 1703 1704 VPRINTK("ENTER\n"); 1705 1706 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1707 1708 ata_print_version_once(&pdev->dev, DRV_VERSION); 1709 1710 /* The AHCI driver can only drive the SATA ports, the PATA driver 1711 can drive them all so if both drivers are selected make sure 1712 AHCI stays out of the way */ 1713 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1714 return -ENODEV; 1715 1716 /* Apple BIOS on MCP89 prevents us using AHCI */ 1717 if (is_mcp89_apple(pdev)) 1718 ahci_mcp89_apple_enable(pdev); 1719 1720 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1721 * At the moment, we can only use the AHCI mode. Let the users know 1722 * that for SAS drives they're out of luck. 1723 */ 1724 if (pdev->vendor == PCI_VENDOR_ID_PROMISE) 1725 dev_info(&pdev->dev, 1726 "PDC42819 can only drive SATA devices with this driver\n"); 1727 1728 /* Some devices use non-standard BARs */ 1729 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) 1730 ahci_pci_bar = AHCI_PCI_BAR_STA2X11; 1731 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) 1732 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; 1733 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) { 1734 if (pdev->device == 0xa01c) 1735 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; 1736 if (pdev->device == 0xa084) 1737 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5; 1738 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) { 1739 if (pdev->device == 0x7a08) 1740 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON; 1741 } 1742 1743 /* acquire resources */ 1744 rc = pcim_enable_device(pdev); 1745 if (rc) 1746 return rc; 1747 1748 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 1749 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 1750 u8 map; 1751 1752 /* ICH6s share the same PCI ID for both piix and ahci 1753 * modes. Enabling ahci mode while MAP indicates 1754 * combined mode is a bad idea. Yield to ata_piix. 1755 */ 1756 pci_read_config_byte(pdev, ICH_MAP, &map); 1757 if (map & 0x3) { 1758 dev_info(&pdev->dev, 1759 "controller is in combined mode, can't enable AHCI mode\n"); 1760 return -ENODEV; 1761 } 1762 } 1763 1764 /* AHCI controllers often implement SFF compatible interface. 1765 * Grab all PCI BARs just in case. 1766 */ 1767 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); 1768 if (rc == -EBUSY) 1769 pcim_pin_device(pdev); 1770 if (rc) 1771 return rc; 1772 1773 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1774 if (!hpriv) 1775 return -ENOMEM; 1776 hpriv->flags |= (unsigned long)pi.private_data; 1777 1778 /* MCP65 revision A1 and A2 can't do MSI */ 1779 if (board_id == board_ahci_mcp65 && 1780 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 1781 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1782 1783 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 1784 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 1785 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 1786 1787 /* only some SB600s can do 64bit DMA */ 1788 if (ahci_sb600_enable_64bit(pdev)) 1789 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; 1790 1791 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; 1792 1793 /* detect remapped nvme devices */ 1794 ahci_remap_check(pdev, ahci_pci_bar, hpriv); 1795 1796 sysfs_add_file_to_group(&pdev->dev.kobj, 1797 &dev_attr_remapped_nvme.attr, 1798 NULL); 1799 1800 /* must set flag prior to save config in order to take effect */ 1801 if (ahci_broken_devslp(pdev)) 1802 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP; 1803 1804#ifdef CONFIG_ARM64 1805 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI && 1806 pdev->device == 0xa235 && 1807 pdev->revision < 0x30) 1808 hpriv->flags |= AHCI_HFLAG_NO_SXS; 1809 1810 if (pdev->vendor == 0x177d && pdev->device == 0xa01c) 1811 hpriv->irq_handler = ahci_thunderx_irq_handler; 1812#endif 1813 1814 /* save initial config */ 1815 ahci_pci_save_initial_config(pdev, hpriv); 1816 1817 /* prepare host */ 1818 if (hpriv->cap & HOST_CAP_NCQ) { 1819 pi.flags |= ATA_FLAG_NCQ; 1820 /* 1821 * Auto-activate optimization is supposed to be 1822 * supported on all AHCI controllers indicating NCQ 1823 * capability, but it seems to be broken on some 1824 * chipsets including NVIDIAs. 1825 */ 1826 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) 1827 pi.flags |= ATA_FLAG_FPDMA_AA; 1828 1829 /* 1830 * All AHCI controllers should be forward-compatible 1831 * with the new auxiliary field. This code should be 1832 * conditionalized if any buggy AHCI controllers are 1833 * encountered. 1834 */ 1835 pi.flags |= ATA_FLAG_FPDMA_AUX; 1836 } 1837 1838 if (hpriv->cap & HOST_CAP_PMP) 1839 pi.flags |= ATA_FLAG_PMP; 1840 1841 ahci_set_em_messages(hpriv, &pi); 1842 1843 if (ahci_broken_system_poweroff(pdev)) { 1844 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 1845 dev_info(&pdev->dev, 1846 "quirky BIOS, skipping spindown on poweroff\n"); 1847 } 1848 1849 if (ahci_broken_lpm(pdev)) { 1850 pi.flags |= ATA_FLAG_NO_LPM; 1851 dev_warn(&pdev->dev, 1852 "BIOS update required for Link Power Management support\n"); 1853 } 1854 1855 if (ahci_broken_suspend(pdev)) { 1856 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 1857 dev_warn(&pdev->dev, 1858 "BIOS update required for suspend/resume\n"); 1859 } 1860 1861 if (ahci_broken_online(pdev)) { 1862 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; 1863 dev_info(&pdev->dev, 1864 "online status unreliable, applying workaround\n"); 1865 } 1866 1867 1868 /* Acer SA5-271 workaround modifies private_data */ 1869 acer_sa5_271_workaround(hpriv, pdev); 1870 1871 /* CAP.NP sometimes indicate the index of the last enabled 1872 * port, at other times, that of the last possible port, so 1873 * determining the maximum port number requires looking at 1874 * both CAP.NP and port_map. 1875 */ 1876 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 1877 1878 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1879 if (!host) 1880 return -ENOMEM; 1881 host->private_data = hpriv; 1882 1883 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) { 1884 /* legacy intx interrupts */ 1885 pci_intx(pdev, 1); 1886 } 1887 hpriv->irq = pci_irq_vector(pdev, 0); 1888 1889 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 1890 host->flags |= ATA_HOST_PARALLEL_SCAN; 1891 else 1892 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); 1893 1894 if (!(hpriv->cap & HOST_CAP_PART)) 1895 host->flags |= ATA_HOST_NO_PART; 1896 1897 if (!(hpriv->cap & HOST_CAP_SSC)) 1898 host->flags |= ATA_HOST_NO_SSC; 1899 1900 if (!(hpriv->cap2 & HOST_CAP2_SDS)) 1901 host->flags |= ATA_HOST_NO_DEVSLP; 1902 1903 if (pi.flags & ATA_FLAG_EM) 1904 ahci_reset_em(host); 1905 1906 for (i = 0; i < host->n_ports; i++) { 1907 struct ata_port *ap = host->ports[i]; 1908 1909 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); 1910 ata_port_pbar_desc(ap, ahci_pci_bar, 1911 0x100 + ap->port_no * 0x80, "port"); 1912 1913 /* set enclosure management message type */ 1914 if (ap->flags & ATA_FLAG_EM) 1915 ap->em_message_type = hpriv->em_msg_type; 1916 1917 ahci_update_initial_lpm_policy(ap, hpriv); 1918 1919 /* disabled/not-implemented port */ 1920 if (!(hpriv->port_map & (1 << i))) 1921 ap->ops = &ata_dummy_port_ops; 1922 } 1923 1924 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 1925 ahci_p5wdh_workaround(host); 1926 1927 /* apply gtf filter quirk */ 1928 ahci_gtf_filter_workaround(host); 1929 1930 /* initialize adapter */ 1931 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); 1932 if (rc) 1933 return rc; 1934 1935 rc = ahci_pci_reset_controller(host); 1936 if (rc) 1937 return rc; 1938 1939 ahci_pci_init_controller(host); 1940 ahci_pci_print_info(host); 1941 1942 pci_set_master(pdev); 1943 1944 rc = ahci_host_activate(host, &ahci_sht); 1945 if (rc) 1946 return rc; 1947 1948 pm_runtime_put_noidle(&pdev->dev); 1949 return 0; 1950} 1951 1952static void ahci_shutdown_one(struct pci_dev *pdev) 1953{ 1954 ata_pci_shutdown_one(pdev); 1955} 1956 1957static void ahci_remove_one(struct pci_dev *pdev) 1958{ 1959 sysfs_remove_file_from_group(&pdev->dev.kobj, 1960 &dev_attr_remapped_nvme.attr, 1961 NULL); 1962 pm_runtime_get_noresume(&pdev->dev); 1963 ata_pci_remove_one(pdev); 1964} 1965 1966module_pci_driver(ahci_pci_driver); 1967 1968MODULE_AUTHOR("Jeff Garzik"); 1969MODULE_DESCRIPTION("AHCI SATA low-level driver"); 1970MODULE_LICENSE("GPL"); 1971MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 1972MODULE_VERSION(DRV_VERSION); 1973