1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers. 4 * 5 * (C) Copyright 2014, 2015 Linaro Ltd. 6 * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org> 7 * 8 * CPPC describes a few methods for controlling CPU performance using 9 * information from a per CPU table called CPC. This table is described in 10 * the ACPI v5.0+ specification. The table consists of a list of 11 * registers which may be memory mapped or hardware registers and also may 12 * include some static integer values. 13 * 14 * CPU performance is on an abstract continuous scale as against a discretized 15 * P-state scale which is tied to CPU frequency only. In brief, the basic 16 * operation involves: 17 * 18 * - OS makes a CPU performance request. (Can provide min and max bounds) 19 * 20 * - Platform (such as BMC) is free to optimize request within requested bounds 21 * depending on power/thermal budgets etc. 22 * 23 * - Platform conveys its decision back to OS 24 * 25 * The communication between OS and platform occurs through another medium 26 * called (PCC) Platform Communication Channel. This is a generic mailbox like 27 * mechanism which includes doorbell semantics to indicate register updates. 28 * See drivers/mailbox/pcc.c for details on PCC. 29 * 30 * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and 31 * above specifications. 32 */ 33 34#define pr_fmt(fmt) "ACPI CPPC: " fmt 35 36#include <linux/cpufreq.h> 37#include <linux/delay.h> 38#include <linux/iopoll.h> 39#include <linux/ktime.h> 40#include <linux/rwsem.h> 41#include <linux/wait.h> 42 43#include <acpi/cppc_acpi.h> 44 45struct cppc_pcc_data { 46 struct mbox_chan *pcc_channel; 47 void __iomem *pcc_comm_addr; 48 bool pcc_channel_acquired; 49 unsigned int deadline_us; 50 unsigned int pcc_mpar, pcc_mrtt, pcc_nominal; 51 52 bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */ 53 bool platform_owns_pcc; /* Ownership of PCC subspace */ 54 unsigned int pcc_write_cnt; /* Running count of PCC write commands */ 55 56 /* 57 * Lock to provide controlled access to the PCC channel. 58 * 59 * For performance critical usecases(currently cppc_set_perf) 60 * We need to take read_lock and check if channel belongs to OSPM 61 * before reading or writing to PCC subspace 62 * We need to take write_lock before transferring the channel 63 * ownership to the platform via a Doorbell 64 * This allows us to batch a number of CPPC requests if they happen 65 * to originate in about the same time 66 * 67 * For non-performance critical usecases(init) 68 * Take write_lock for all purposes which gives exclusive access 69 */ 70 struct rw_semaphore pcc_lock; 71 72 /* Wait queue for CPUs whose requests were batched */ 73 wait_queue_head_t pcc_write_wait_q; 74 ktime_t last_cmd_cmpl_time; 75 ktime_t last_mpar_reset; 76 int mpar_count; 77 int refcount; 78}; 79 80/* Array to represent the PCC channel per subspace ID */ 81static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES]; 82/* The cpu_pcc_subspace_idx contains per CPU subspace ID */ 83static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx); 84 85/* 86 * The cpc_desc structure contains the ACPI register details 87 * as described in the per CPU _CPC tables. The details 88 * include the type of register (e.g. PCC, System IO, FFH etc.) 89 * and destination addresses which lets us READ/WRITE CPU performance 90 * information using the appropriate I/O methods. 91 */ 92static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr); 93 94/* pcc mapped address + header size + offset within PCC subspace */ 95#define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \ 96 0x8 + (offs)) 97 98/* Check if a CPC register is in PCC */ 99#define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \ 100 (cpc)->cpc_entry.reg.space_id == \ 101 ACPI_ADR_SPACE_PLATFORM_COMM) 102 103/* Evalutes to True if reg is a NULL register descriptor */ 104#define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \ 105 (reg)->address == 0 && \ 106 (reg)->bit_width == 0 && \ 107 (reg)->bit_offset == 0 && \ 108 (reg)->access_width == 0) 109 110/* Evalutes to True if an optional cpc field is supported */ 111#define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \ 112 !!(cpc)->cpc_entry.int_value : \ 113 !IS_NULL_REG(&(cpc)->cpc_entry.reg)) 114/* 115 * Arbitrary Retries in case the remote processor is slow to respond 116 * to PCC commands. Keeping it high enough to cover emulators where 117 * the processors run painfully slow. 118 */ 119#define NUM_RETRIES 500ULL 120 121#define define_one_cppc_ro(_name) \ 122static struct kobj_attribute _name = \ 123__ATTR(_name, 0444, show_##_name, NULL) 124 125#define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj) 126 127#define show_cppc_data(access_fn, struct_name, member_name) \ 128 static ssize_t show_##member_name(struct kobject *kobj, \ 129 struct kobj_attribute *attr, char *buf) \ 130 { \ 131 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \ 132 struct struct_name st_name = {0}; \ 133 int ret; \ 134 \ 135 ret = access_fn(cpc_ptr->cpu_id, &st_name); \ 136 if (ret) \ 137 return ret; \ 138 \ 139 return scnprintf(buf, PAGE_SIZE, "%llu\n", \ 140 (u64)st_name.member_name); \ 141 } \ 142 define_one_cppc_ro(member_name) 143 144show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf); 145show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf); 146show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf); 147show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf); 148show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq); 149show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq); 150 151show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf); 152show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time); 153 154static ssize_t show_feedback_ctrs(struct kobject *kobj, 155 struct kobj_attribute *attr, char *buf) 156{ 157 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); 158 struct cppc_perf_fb_ctrs fb_ctrs = {0}; 159 int ret; 160 161 ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs); 162 if (ret) 163 return ret; 164 165 return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n", 166 fb_ctrs.reference, fb_ctrs.delivered); 167} 168define_one_cppc_ro(feedback_ctrs); 169 170static struct attribute *cppc_attrs[] = { 171 &feedback_ctrs.attr, 172 &reference_perf.attr, 173 &wraparound_time.attr, 174 &highest_perf.attr, 175 &lowest_perf.attr, 176 &lowest_nonlinear_perf.attr, 177 &nominal_perf.attr, 178 &nominal_freq.attr, 179 &lowest_freq.attr, 180 NULL 181}; 182 183static struct kobj_type cppc_ktype = { 184 .sysfs_ops = &kobj_sysfs_ops, 185 .default_attrs = cppc_attrs, 186}; 187 188static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit) 189{ 190 int ret, status; 191 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; 192 struct acpi_pcct_shared_memory __iomem *generic_comm_base = 193 pcc_ss_data->pcc_comm_addr; 194 195 if (!pcc_ss_data->platform_owns_pcc) 196 return 0; 197 198 /* 199 * Poll PCC status register every 3us(delay_us) for maximum of 200 * deadline_us(timeout_us) until PCC command complete bit is set(cond) 201 */ 202 ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status, 203 status & PCC_CMD_COMPLETE_MASK, 3, 204 pcc_ss_data->deadline_us); 205 206 if (likely(!ret)) { 207 pcc_ss_data->platform_owns_pcc = false; 208 if (chk_err_bit && (status & PCC_ERROR_MASK)) 209 ret = -EIO; 210 } 211 212 if (unlikely(ret)) 213 pr_err("PCC check channel failed for ss: %d. ret=%d\n", 214 pcc_ss_id, ret); 215 216 return ret; 217} 218 219/* 220 * This function transfers the ownership of the PCC to the platform 221 * So it must be called while holding write_lock(pcc_lock) 222 */ 223static int send_pcc_cmd(int pcc_ss_id, u16 cmd) 224{ 225 int ret = -EIO, i; 226 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; 227 struct acpi_pcct_shared_memory *generic_comm_base = 228 (struct acpi_pcct_shared_memory *)pcc_ss_data->pcc_comm_addr; 229 unsigned int time_delta; 230 231 /* 232 * For CMD_WRITE we know for a fact the caller should have checked 233 * the channel before writing to PCC space 234 */ 235 if (cmd == CMD_READ) { 236 /* 237 * If there are pending cpc_writes, then we stole the channel 238 * before write completion, so first send a WRITE command to 239 * platform 240 */ 241 if (pcc_ss_data->pending_pcc_write_cmd) 242 send_pcc_cmd(pcc_ss_id, CMD_WRITE); 243 244 ret = check_pcc_chan(pcc_ss_id, false); 245 if (ret) 246 goto end; 247 } else /* CMD_WRITE */ 248 pcc_ss_data->pending_pcc_write_cmd = FALSE; 249 250 /* 251 * Handle the Minimum Request Turnaround Time(MRTT) 252 * "The minimum amount of time that OSPM must wait after the completion 253 * of a command before issuing the next command, in microseconds" 254 */ 255 if (pcc_ss_data->pcc_mrtt) { 256 time_delta = ktime_us_delta(ktime_get(), 257 pcc_ss_data->last_cmd_cmpl_time); 258 if (pcc_ss_data->pcc_mrtt > time_delta) 259 udelay(pcc_ss_data->pcc_mrtt - time_delta); 260 } 261 262 /* 263 * Handle the non-zero Maximum Periodic Access Rate(MPAR) 264 * "The maximum number of periodic requests that the subspace channel can 265 * support, reported in commands per minute. 0 indicates no limitation." 266 * 267 * This parameter should be ideally zero or large enough so that it can 268 * handle maximum number of requests that all the cores in the system can 269 * collectively generate. If it is not, we will follow the spec and just 270 * not send the request to the platform after hitting the MPAR limit in 271 * any 60s window 272 */ 273 if (pcc_ss_data->pcc_mpar) { 274 if (pcc_ss_data->mpar_count == 0) { 275 time_delta = ktime_ms_delta(ktime_get(), 276 pcc_ss_data->last_mpar_reset); 277 if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) { 278 pr_debug("PCC cmd for subspace %d not sent due to MPAR limit", 279 pcc_ss_id); 280 ret = -EIO; 281 goto end; 282 } 283 pcc_ss_data->last_mpar_reset = ktime_get(); 284 pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar; 285 } 286 pcc_ss_data->mpar_count--; 287 } 288 289 /* Write to the shared comm region. */ 290 writew_relaxed(cmd, &generic_comm_base->command); 291 292 /* Flip CMD COMPLETE bit */ 293 writew_relaxed(0, &generic_comm_base->status); 294 295 pcc_ss_data->platform_owns_pcc = true; 296 297 /* Ring doorbell */ 298 ret = mbox_send_message(pcc_ss_data->pcc_channel, &cmd); 299 if (ret < 0) { 300 pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n", 301 pcc_ss_id, cmd, ret); 302 goto end; 303 } 304 305 /* wait for completion and check for PCC errro bit */ 306 ret = check_pcc_chan(pcc_ss_id, true); 307 308 if (pcc_ss_data->pcc_mrtt) 309 pcc_ss_data->last_cmd_cmpl_time = ktime_get(); 310 311 if (pcc_ss_data->pcc_channel->mbox->txdone_irq) 312 mbox_chan_txdone(pcc_ss_data->pcc_channel, ret); 313 else 314 mbox_client_txdone(pcc_ss_data->pcc_channel, ret); 315 316end: 317 if (cmd == CMD_WRITE) { 318 if (unlikely(ret)) { 319 for_each_possible_cpu(i) { 320 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i); 321 if (!desc) 322 continue; 323 324 if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt) 325 desc->write_cmd_status = ret; 326 } 327 } 328 pcc_ss_data->pcc_write_cnt++; 329 wake_up_all(&pcc_ss_data->pcc_write_wait_q); 330 } 331 332 return ret; 333} 334 335static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret) 336{ 337 if (ret < 0) 338 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n", 339 *(u16 *)msg, ret); 340 else 341 pr_debug("TX completed. CMD sent:%x, ret:%d\n", 342 *(u16 *)msg, ret); 343} 344 345static struct mbox_client cppc_mbox_cl = { 346 .tx_done = cppc_chan_tx_done, 347 .knows_txdone = true, 348}; 349 350static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle) 351{ 352 int result = -EFAULT; 353 acpi_status status = AE_OK; 354 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL}; 355 struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"}; 356 struct acpi_buffer state = {0, NULL}; 357 union acpi_object *psd = NULL; 358 struct acpi_psd_package *pdomain; 359 360 status = acpi_evaluate_object_typed(handle, "_PSD", NULL, 361 &buffer, ACPI_TYPE_PACKAGE); 362 if (status == AE_NOT_FOUND) /* _PSD is optional */ 363 return 0; 364 if (ACPI_FAILURE(status)) 365 return -ENODEV; 366 367 psd = buffer.pointer; 368 if (!psd || psd->package.count != 1) { 369 pr_debug("Invalid _PSD data\n"); 370 goto end; 371 } 372 373 pdomain = &(cpc_ptr->domain_info); 374 375 state.length = sizeof(struct acpi_psd_package); 376 state.pointer = pdomain; 377 378 status = acpi_extract_package(&(psd->package.elements[0]), 379 &format, &state); 380 if (ACPI_FAILURE(status)) { 381 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id); 382 goto end; 383 } 384 385 if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) { 386 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id); 387 goto end; 388 } 389 390 if (pdomain->revision != ACPI_PSD_REV0_REVISION) { 391 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id); 392 goto end; 393 } 394 395 if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL && 396 pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY && 397 pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) { 398 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id); 399 goto end; 400 } 401 402 result = 0; 403end: 404 kfree(buffer.pointer); 405 return result; 406} 407 408/** 409 * acpi_get_psd_map - Map the CPUs in a common freq domain. 410 * @all_cpu_data: Ptrs to CPU specific CPPC data including PSD info. 411 * 412 * Return: 0 for success or negative value for err. 413 */ 414int acpi_get_psd_map(struct cppc_cpudata **all_cpu_data) 415{ 416 int count_target; 417 int retval = 0; 418 unsigned int i, j; 419 cpumask_var_t covered_cpus; 420 struct cppc_cpudata *pr, *match_pr; 421 struct acpi_psd_package *pdomain; 422 struct acpi_psd_package *match_pdomain; 423 struct cpc_desc *cpc_ptr, *match_cpc_ptr; 424 425 if (!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL)) 426 return -ENOMEM; 427 428 /* 429 * Now that we have _PSD data from all CPUs, let's setup P-state 430 * domain info. 431 */ 432 for_each_possible_cpu(i) { 433 if (cpumask_test_cpu(i, covered_cpus)) 434 continue; 435 436 pr = all_cpu_data[i]; 437 cpc_ptr = per_cpu(cpc_desc_ptr, i); 438 if (!cpc_ptr) { 439 retval = -EFAULT; 440 goto err_ret; 441 } 442 443 pdomain = &(cpc_ptr->domain_info); 444 cpumask_set_cpu(i, pr->shared_cpu_map); 445 cpumask_set_cpu(i, covered_cpus); 446 if (pdomain->num_processors <= 1) 447 continue; 448 449 /* Validate the Domain info */ 450 count_target = pdomain->num_processors; 451 if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL) 452 pr->shared_type = CPUFREQ_SHARED_TYPE_ALL; 453 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL) 454 pr->shared_type = CPUFREQ_SHARED_TYPE_HW; 455 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY) 456 pr->shared_type = CPUFREQ_SHARED_TYPE_ANY; 457 458 for_each_possible_cpu(j) { 459 if (i == j) 460 continue; 461 462 match_cpc_ptr = per_cpu(cpc_desc_ptr, j); 463 if (!match_cpc_ptr) { 464 retval = -EFAULT; 465 goto err_ret; 466 } 467 468 match_pdomain = &(match_cpc_ptr->domain_info); 469 if (match_pdomain->domain != pdomain->domain) 470 continue; 471 472 /* Here i and j are in the same domain */ 473 if (match_pdomain->num_processors != count_target) { 474 retval = -EFAULT; 475 goto err_ret; 476 } 477 478 if (pdomain->coord_type != match_pdomain->coord_type) { 479 retval = -EFAULT; 480 goto err_ret; 481 } 482 483 cpumask_set_cpu(j, covered_cpus); 484 cpumask_set_cpu(j, pr->shared_cpu_map); 485 } 486 487 for_each_cpu(j, pr->shared_cpu_map) { 488 if (i == j) 489 continue; 490 491 match_pr = all_cpu_data[j]; 492 match_pr->shared_type = pr->shared_type; 493 cpumask_copy(match_pr->shared_cpu_map, 494 pr->shared_cpu_map); 495 } 496 } 497 goto out; 498 499err_ret: 500 for_each_possible_cpu(i) { 501 pr = all_cpu_data[i]; 502 503 /* Assume no coordination on any error parsing domain info */ 504 cpumask_clear(pr->shared_cpu_map); 505 cpumask_set_cpu(i, pr->shared_cpu_map); 506 pr->shared_type = CPUFREQ_SHARED_TYPE_ALL; 507 } 508out: 509 free_cpumask_var(covered_cpus); 510 return retval; 511} 512EXPORT_SYMBOL_GPL(acpi_get_psd_map); 513 514static int register_pcc_channel(int pcc_ss_idx) 515{ 516 struct acpi_pcct_hw_reduced *cppc_ss; 517 u64 usecs_lat; 518 519 if (pcc_ss_idx >= 0) { 520 pcc_data[pcc_ss_idx]->pcc_channel = 521 pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx); 522 523 if (IS_ERR(pcc_data[pcc_ss_idx]->pcc_channel)) { 524 pr_err("Failed to find PCC channel for subspace %d\n", 525 pcc_ss_idx); 526 return -ENODEV; 527 } 528 529 /* 530 * The PCC mailbox controller driver should 531 * have parsed the PCCT (global table of all 532 * PCC channels) and stored pointers to the 533 * subspace communication region in con_priv. 534 */ 535 cppc_ss = (pcc_data[pcc_ss_idx]->pcc_channel)->con_priv; 536 537 if (!cppc_ss) { 538 pr_err("No PCC subspace found for %d CPPC\n", 539 pcc_ss_idx); 540 return -ENODEV; 541 } 542 543 /* 544 * cppc_ss->latency is just a Nominal value. In reality 545 * the remote processor could be much slower to reply. 546 * So add an arbitrary amount of wait on top of Nominal. 547 */ 548 usecs_lat = NUM_RETRIES * cppc_ss->latency; 549 pcc_data[pcc_ss_idx]->deadline_us = usecs_lat; 550 pcc_data[pcc_ss_idx]->pcc_mrtt = cppc_ss->min_turnaround_time; 551 pcc_data[pcc_ss_idx]->pcc_mpar = cppc_ss->max_access_rate; 552 pcc_data[pcc_ss_idx]->pcc_nominal = cppc_ss->latency; 553 554 pcc_data[pcc_ss_idx]->pcc_comm_addr = 555 acpi_os_ioremap(cppc_ss->base_address, cppc_ss->length); 556 if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) { 557 pr_err("Failed to ioremap PCC comm region mem for %d\n", 558 pcc_ss_idx); 559 return -ENOMEM; 560 } 561 562 /* Set flag so that we don't come here for each CPU. */ 563 pcc_data[pcc_ss_idx]->pcc_channel_acquired = true; 564 } 565 566 return 0; 567} 568 569/** 570 * cpc_ffh_supported() - check if FFH reading supported 571 * 572 * Check if the architecture has support for functional fixed hardware 573 * read/write capability. 574 * 575 * Return: true for supported, false for not supported 576 */ 577bool __weak cpc_ffh_supported(void) 578{ 579 return false; 580} 581 582/** 583 * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace 584 * 585 * Check and allocate the cppc_pcc_data memory. 586 * In some processor configurations it is possible that same subspace 587 * is shared between multiple CPUs. This is seen especially in CPUs 588 * with hardware multi-threading support. 589 * 590 * Return: 0 for success, errno for failure 591 */ 592static int pcc_data_alloc(int pcc_ss_id) 593{ 594 if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES) 595 return -EINVAL; 596 597 if (pcc_data[pcc_ss_id]) { 598 pcc_data[pcc_ss_id]->refcount++; 599 } else { 600 pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data), 601 GFP_KERNEL); 602 if (!pcc_data[pcc_ss_id]) 603 return -ENOMEM; 604 pcc_data[pcc_ss_id]->refcount++; 605 } 606 607 return 0; 608} 609 610/* 611 * An example CPC table looks like the following. 612 * 613 * Name(_CPC, Package() 614 * { 615 * 17, 616 * NumEntries 617 * 1, 618 * // Revision 619 * ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)}, 620 * // Highest Performance 621 * ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)}, 622 * // Nominal Performance 623 * ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)}, 624 * // Lowest Nonlinear Performance 625 * ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)}, 626 * // Lowest Performance 627 * ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)}, 628 * // Guaranteed Performance Register 629 * ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)}, 630 * // Desired Performance Register 631 * ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, 632 * .. 633 * .. 634 * .. 635 * 636 * } 637 * Each Register() encodes how to access that specific register. 638 * e.g. a sample PCC entry has the following encoding: 639 * 640 * Register ( 641 * PCC, 642 * AddressSpaceKeyword 643 * 8, 644 * //RegisterBitWidth 645 * 8, 646 * //RegisterBitOffset 647 * 0x30, 648 * //RegisterAddress 649 * 9 650 * //AccessSize (subspace ID) 651 * 0 652 * ) 653 * } 654 */ 655 656/** 657 * acpi_cppc_processor_probe - Search for per CPU _CPC objects. 658 * @pr: Ptr to acpi_processor containing this CPU's logical ID. 659 * 660 * Return: 0 for success or negative value for err. 661 */ 662int acpi_cppc_processor_probe(struct acpi_processor *pr) 663{ 664 struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL}; 665 union acpi_object *out_obj, *cpc_obj; 666 struct cpc_desc *cpc_ptr; 667 struct cpc_reg *gas_t; 668 struct device *cpu_dev; 669 acpi_handle handle = pr->handle; 670 unsigned int num_ent, i, cpc_rev; 671 int pcc_subspace_id = -1; 672 acpi_status status; 673 int ret = -EFAULT; 674 675 /* Parse the ACPI _CPC table for this CPU. */ 676 status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output, 677 ACPI_TYPE_PACKAGE); 678 if (ACPI_FAILURE(status)) { 679 ret = -ENODEV; 680 goto out_buf_free; 681 } 682 683 out_obj = (union acpi_object *) output.pointer; 684 685 cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL); 686 if (!cpc_ptr) { 687 ret = -ENOMEM; 688 goto out_buf_free; 689 } 690 691 /* First entry is NumEntries. */ 692 cpc_obj = &out_obj->package.elements[0]; 693 if (cpc_obj->type == ACPI_TYPE_INTEGER) { 694 num_ent = cpc_obj->integer.value; 695 if (num_ent <= 1) { 696 pr_debug("Unexpected _CPC NumEntries value (%d) for CPU:%d\n", 697 num_ent, pr->id); 698 goto out_free; 699 } 700 } else { 701 pr_debug("Unexpected entry type(%d) for NumEntries\n", 702 cpc_obj->type); 703 goto out_free; 704 } 705 706 /* Second entry should be revision. */ 707 cpc_obj = &out_obj->package.elements[1]; 708 if (cpc_obj->type == ACPI_TYPE_INTEGER) { 709 cpc_rev = cpc_obj->integer.value; 710 } else { 711 pr_debug("Unexpected entry type(%d) for Revision\n", 712 cpc_obj->type); 713 goto out_free; 714 } 715 716 if (cpc_rev < CPPC_V2_REV) { 717 pr_debug("Unsupported _CPC Revision (%d) for CPU:%d\n", cpc_rev, 718 pr->id); 719 goto out_free; 720 } 721 722 /* 723 * Disregard _CPC if the number of entries in the return pachage is not 724 * as expected, but support future revisions being proper supersets of 725 * the v3 and only causing more entries to be returned by _CPC. 726 */ 727 if ((cpc_rev == CPPC_V2_REV && num_ent != CPPC_V2_NUM_ENT) || 728 (cpc_rev == CPPC_V3_REV && num_ent != CPPC_V3_NUM_ENT) || 729 (cpc_rev > CPPC_V3_REV && num_ent <= CPPC_V3_NUM_ENT)) { 730 pr_debug("Unexpected number of _CPC return package entries (%d) for CPU:%d\n", 731 num_ent, pr->id); 732 goto out_free; 733 } 734 if (cpc_rev > CPPC_V3_REV) { 735 num_ent = CPPC_V3_NUM_ENT; 736 cpc_rev = CPPC_V3_REV; 737 } 738 739 cpc_ptr->num_entries = num_ent; 740 cpc_ptr->version = cpc_rev; 741 742 /* Iterate through remaining entries in _CPC */ 743 for (i = 2; i < num_ent; i++) { 744 cpc_obj = &out_obj->package.elements[i]; 745 746 if (cpc_obj->type == ACPI_TYPE_INTEGER) { 747 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER; 748 cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value; 749 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) { 750 gas_t = (struct cpc_reg *) 751 cpc_obj->buffer.pointer; 752 753 /* 754 * The PCC Subspace index is encoded inside 755 * the CPC table entries. The same PCC index 756 * will be used for all the PCC entries, 757 * so extract it only once. 758 */ 759 if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) { 760 if (pcc_subspace_id < 0) { 761 pcc_subspace_id = gas_t->access_width; 762 if (pcc_data_alloc(pcc_subspace_id)) 763 goto out_free; 764 } else if (pcc_subspace_id != gas_t->access_width) { 765 pr_debug("Mismatched PCC ids.\n"); 766 goto out_free; 767 } 768 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { 769 if (gas_t->address) { 770 void __iomem *addr; 771 772 addr = ioremap(gas_t->address, gas_t->bit_width/8); 773 if (!addr) 774 goto out_free; 775 cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr; 776 } 777 } else { 778 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) { 779 /* Support only PCC ,SYS MEM and FFH type regs */ 780 pr_debug("Unsupported register type: %d\n", gas_t->space_id); 781 goto out_free; 782 } 783 } 784 785 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER; 786 memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t)); 787 } else { 788 pr_debug("Err in entry:%d in CPC table of CPU:%d \n", i, pr->id); 789 goto out_free; 790 } 791 } 792 per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id; 793 794 /* 795 * Initialize the remaining cpc_regs as unsupported. 796 * Example: In case FW exposes CPPC v2, the below loop will initialize 797 * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported 798 */ 799 for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) { 800 cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER; 801 cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0; 802 } 803 804 805 /* Store CPU Logical ID */ 806 cpc_ptr->cpu_id = pr->id; 807 808 /* Parse PSD data for this CPU */ 809 ret = acpi_get_psd(cpc_ptr, handle); 810 if (ret) 811 goto out_free; 812 813 /* Register PCC channel once for all PCC subspace ID. */ 814 if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) { 815 ret = register_pcc_channel(pcc_subspace_id); 816 if (ret) 817 goto out_free; 818 819 init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock); 820 init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q); 821 } 822 823 /* Everything looks okay */ 824 pr_debug("Parsed CPC struct for CPU: %d\n", pr->id); 825 826 /* Add per logical CPU nodes for reading its feedback counters. */ 827 cpu_dev = get_cpu_device(pr->id); 828 if (!cpu_dev) { 829 ret = -EINVAL; 830 goto out_free; 831 } 832 833 /* Plug PSD data into this CPU's CPC descriptor. */ 834 per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr; 835 836 ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj, 837 "acpi_cppc"); 838 if (ret) { 839 per_cpu(cpc_desc_ptr, pr->id) = NULL; 840 kobject_put(&cpc_ptr->kobj); 841 goto out_free; 842 } 843 844 kfree(output.pointer); 845 return 0; 846 847out_free: 848 /* Free all the mapped sys mem areas for this CPU */ 849 for (i = 2; i < cpc_ptr->num_entries; i++) { 850 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr; 851 852 if (addr) 853 iounmap(addr); 854 } 855 kfree(cpc_ptr); 856 857out_buf_free: 858 kfree(output.pointer); 859 return ret; 860} 861EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe); 862 863/** 864 * acpi_cppc_processor_exit - Cleanup CPC structs. 865 * @pr: Ptr to acpi_processor containing this CPU's logical ID. 866 * 867 * Return: Void 868 */ 869void acpi_cppc_processor_exit(struct acpi_processor *pr) 870{ 871 struct cpc_desc *cpc_ptr; 872 unsigned int i; 873 void __iomem *addr; 874 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id); 875 876 if (pcc_ss_id >=0 && pcc_data[pcc_ss_id]) { 877 if (pcc_data[pcc_ss_id]->pcc_channel_acquired) { 878 pcc_data[pcc_ss_id]->refcount--; 879 if (!pcc_data[pcc_ss_id]->refcount) { 880 pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel); 881 kfree(pcc_data[pcc_ss_id]); 882 pcc_data[pcc_ss_id] = NULL; 883 } 884 } 885 } 886 887 cpc_ptr = per_cpu(cpc_desc_ptr, pr->id); 888 if (!cpc_ptr) 889 return; 890 891 /* Free all the mapped sys mem areas for this CPU */ 892 for (i = 2; i < cpc_ptr->num_entries; i++) { 893 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr; 894 if (addr) 895 iounmap(addr); 896 } 897 898 kobject_put(&cpc_ptr->kobj); 899 kfree(cpc_ptr); 900} 901EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit); 902 903/** 904 * cpc_read_ffh() - Read FFH register 905 * @cpunum: CPU number to read 906 * @reg: cppc register information 907 * @val: place holder for return value 908 * 909 * Read bit_width bits from a specified address and bit_offset 910 * 911 * Return: 0 for success and error code 912 */ 913int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val) 914{ 915 return -ENOTSUPP; 916} 917 918/** 919 * cpc_write_ffh() - Write FFH register 920 * @cpunum: CPU number to write 921 * @reg: cppc register information 922 * @val: value to write 923 * 924 * Write value of bit_width bits to a specified address and bit_offset 925 * 926 * Return: 0 for success and error code 927 */ 928int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) 929{ 930 return -ENOTSUPP; 931} 932 933/* 934 * Since cpc_read and cpc_write are called while holding pcc_lock, it should be 935 * as fast as possible. We have already mapped the PCC subspace during init, so 936 * we can directly write to it. 937 */ 938 939static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) 940{ 941 int ret_val = 0; 942 void __iomem *vaddr = 0; 943 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); 944 struct cpc_reg *reg = ®_res->cpc_entry.reg; 945 946 if (reg_res->type == ACPI_TYPE_INTEGER) { 947 *val = reg_res->cpc_entry.int_value; 948 return ret_val; 949 } 950 951 *val = 0; 952 if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) 953 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); 954 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) 955 vaddr = reg_res->sys_mem_vaddr; 956 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) 957 return cpc_read_ffh(cpu, reg, val); 958 else 959 return acpi_os_read_memory((acpi_physical_address)reg->address, 960 val, reg->bit_width); 961 962 switch (reg->bit_width) { 963 case 8: 964 *val = readb_relaxed(vaddr); 965 break; 966 case 16: 967 *val = readw_relaxed(vaddr); 968 break; 969 case 32: 970 *val = readl_relaxed(vaddr); 971 break; 972 case 64: 973 *val = readq_relaxed(vaddr); 974 break; 975 default: 976 pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n", 977 reg->bit_width, pcc_ss_id); 978 ret_val = -EFAULT; 979 } 980 981 return ret_val; 982} 983 984static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) 985{ 986 int ret_val = 0; 987 void __iomem *vaddr = 0; 988 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); 989 struct cpc_reg *reg = ®_res->cpc_entry.reg; 990 991 if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) 992 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); 993 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) 994 vaddr = reg_res->sys_mem_vaddr; 995 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) 996 return cpc_write_ffh(cpu, reg, val); 997 else 998 return acpi_os_write_memory((acpi_physical_address)reg->address, 999 val, reg->bit_width); 1000 1001 switch (reg->bit_width) { 1002 case 8: 1003 writeb_relaxed(val, vaddr); 1004 break; 1005 case 16: 1006 writew_relaxed(val, vaddr); 1007 break; 1008 case 32: 1009 writel_relaxed(val, vaddr); 1010 break; 1011 case 64: 1012 writeq_relaxed(val, vaddr); 1013 break; 1014 default: 1015 pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n", 1016 reg->bit_width, pcc_ss_id); 1017 ret_val = -EFAULT; 1018 break; 1019 } 1020 1021 return ret_val; 1022} 1023 1024/** 1025 * cppc_get_desired_perf - Get the value of desired performance register. 1026 * @cpunum: CPU from which to get desired performance. 1027 * @desired_perf: address of a variable to store the returned desired performance 1028 * 1029 * Return: 0 for success, -EIO otherwise. 1030 */ 1031int cppc_get_desired_perf(int cpunum, u64 *desired_perf) 1032{ 1033 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); 1034 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); 1035 struct cpc_register_resource *desired_reg; 1036 struct cppc_pcc_data *pcc_ss_data = NULL; 1037 1038 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; 1039 1040 if (CPC_IN_PCC(desired_reg)) { 1041 int ret = 0; 1042 1043 if (pcc_ss_id < 0) 1044 return -EIO; 1045 1046 pcc_ss_data = pcc_data[pcc_ss_id]; 1047 1048 down_write(&pcc_ss_data->pcc_lock); 1049 1050 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) 1051 cpc_read(cpunum, desired_reg, desired_perf); 1052 else 1053 ret = -EIO; 1054 1055 up_write(&pcc_ss_data->pcc_lock); 1056 1057 return ret; 1058 } 1059 1060 cpc_read(cpunum, desired_reg, desired_perf); 1061 1062 return 0; 1063} 1064EXPORT_SYMBOL_GPL(cppc_get_desired_perf); 1065 1066/** 1067 * cppc_get_perf_caps - Get a CPU's performance capabilities. 1068 * @cpunum: CPU from which to get capabilities info. 1069 * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h 1070 * 1071 * Return: 0 for success with perf_caps populated else -ERRNO. 1072 */ 1073int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps) 1074{ 1075 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); 1076 struct cpc_register_resource *highest_reg, *lowest_reg, 1077 *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg, 1078 *low_freq_reg = NULL, *nom_freq_reg = NULL; 1079 u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0; 1080 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); 1081 struct cppc_pcc_data *pcc_ss_data = NULL; 1082 int ret = 0, regs_in_pcc = 0; 1083 1084 if (!cpc_desc) { 1085 pr_debug("No CPC descriptor for CPU:%d\n", cpunum); 1086 return -ENODEV; 1087 } 1088 1089 highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF]; 1090 lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF]; 1091 lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF]; 1092 nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF]; 1093 low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ]; 1094 nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ]; 1095 guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF]; 1096 1097 /* Are any of the regs PCC ?*/ 1098 if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) || 1099 CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) || 1100 CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) { 1101 if (pcc_ss_id < 0) { 1102 pr_debug("Invalid pcc_ss_id\n"); 1103 return -ENODEV; 1104 } 1105 pcc_ss_data = pcc_data[pcc_ss_id]; 1106 regs_in_pcc = 1; 1107 down_write(&pcc_ss_data->pcc_lock); 1108 /* Ring doorbell once to update PCC subspace */ 1109 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { 1110 ret = -EIO; 1111 goto out_err; 1112 } 1113 } 1114 1115 cpc_read(cpunum, highest_reg, &high); 1116 perf_caps->highest_perf = high; 1117 1118 cpc_read(cpunum, lowest_reg, &low); 1119 perf_caps->lowest_perf = low; 1120 1121 cpc_read(cpunum, nominal_reg, &nom); 1122 perf_caps->nominal_perf = nom; 1123 1124 if (guaranteed_reg->type != ACPI_TYPE_BUFFER || 1125 IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) { 1126 perf_caps->guaranteed_perf = 0; 1127 } else { 1128 cpc_read(cpunum, guaranteed_reg, &guaranteed); 1129 perf_caps->guaranteed_perf = guaranteed; 1130 } 1131 1132 cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear); 1133 perf_caps->lowest_nonlinear_perf = min_nonlinear; 1134 1135 if (!high || !low || !nom || !min_nonlinear) 1136 ret = -EFAULT; 1137 1138 /* Read optional lowest and nominal frequencies if present */ 1139 if (CPC_SUPPORTED(low_freq_reg)) 1140 cpc_read(cpunum, low_freq_reg, &low_f); 1141 1142 if (CPC_SUPPORTED(nom_freq_reg)) 1143 cpc_read(cpunum, nom_freq_reg, &nom_f); 1144 1145 perf_caps->lowest_freq = low_f; 1146 perf_caps->nominal_freq = nom_f; 1147 1148 1149out_err: 1150 if (regs_in_pcc) 1151 up_write(&pcc_ss_data->pcc_lock); 1152 return ret; 1153} 1154EXPORT_SYMBOL_GPL(cppc_get_perf_caps); 1155 1156/** 1157 * cppc_get_perf_ctrs - Read a CPU's performance feedback counters. 1158 * @cpunum: CPU from which to read counters. 1159 * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h 1160 * 1161 * Return: 0 for success with perf_fb_ctrs populated else -ERRNO. 1162 */ 1163int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) 1164{ 1165 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); 1166 struct cpc_register_resource *delivered_reg, *reference_reg, 1167 *ref_perf_reg, *ctr_wrap_reg; 1168 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); 1169 struct cppc_pcc_data *pcc_ss_data = NULL; 1170 u64 delivered, reference, ref_perf, ctr_wrap_time; 1171 int ret = 0, regs_in_pcc = 0; 1172 1173 if (!cpc_desc) { 1174 pr_debug("No CPC descriptor for CPU:%d\n", cpunum); 1175 return -ENODEV; 1176 } 1177 1178 delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR]; 1179 reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR]; 1180 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF]; 1181 ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME]; 1182 1183 /* 1184 * If reference perf register is not supported then we should 1185 * use the nominal perf value 1186 */ 1187 if (!CPC_SUPPORTED(ref_perf_reg)) 1188 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF]; 1189 1190 /* Are any of the regs PCC ?*/ 1191 if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) || 1192 CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) { 1193 if (pcc_ss_id < 0) { 1194 pr_debug("Invalid pcc_ss_id\n"); 1195 return -ENODEV; 1196 } 1197 pcc_ss_data = pcc_data[pcc_ss_id]; 1198 down_write(&pcc_ss_data->pcc_lock); 1199 regs_in_pcc = 1; 1200 /* Ring doorbell once to update PCC subspace */ 1201 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { 1202 ret = -EIO; 1203 goto out_err; 1204 } 1205 } 1206 1207 cpc_read(cpunum, delivered_reg, &delivered); 1208 cpc_read(cpunum, reference_reg, &reference); 1209 cpc_read(cpunum, ref_perf_reg, &ref_perf); 1210 1211 /* 1212 * Per spec, if ctr_wrap_time optional register is unsupported, then the 1213 * performance counters are assumed to never wrap during the lifetime of 1214 * platform 1215 */ 1216 ctr_wrap_time = (u64)(~((u64)0)); 1217 if (CPC_SUPPORTED(ctr_wrap_reg)) 1218 cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time); 1219 1220 if (!delivered || !reference || !ref_perf) { 1221 ret = -EFAULT; 1222 goto out_err; 1223 } 1224 1225 perf_fb_ctrs->delivered = delivered; 1226 perf_fb_ctrs->reference = reference; 1227 perf_fb_ctrs->reference_perf = ref_perf; 1228 perf_fb_ctrs->wraparound_time = ctr_wrap_time; 1229out_err: 1230 if (regs_in_pcc) 1231 up_write(&pcc_ss_data->pcc_lock); 1232 return ret; 1233} 1234EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); 1235 1236/** 1237 * cppc_set_perf - Set a CPU's performance controls. 1238 * @cpu: CPU for which to set performance controls. 1239 * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h 1240 * 1241 * Return: 0 for success, -ERRNO otherwise. 1242 */ 1243int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) 1244{ 1245 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); 1246 struct cpc_register_resource *desired_reg; 1247 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); 1248 struct cppc_pcc_data *pcc_ss_data = NULL; 1249 int ret = 0; 1250 1251 if (!cpc_desc) { 1252 pr_debug("No CPC descriptor for CPU:%d\n", cpu); 1253 return -ENODEV; 1254 } 1255 1256 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; 1257 1258 /* 1259 * This is Phase-I where we want to write to CPC registers 1260 * -> We want all CPUs to be able to execute this phase in parallel 1261 * 1262 * Since read_lock can be acquired by multiple CPUs simultaneously we 1263 * achieve that goal here 1264 */ 1265 if (CPC_IN_PCC(desired_reg)) { 1266 if (pcc_ss_id < 0) { 1267 pr_debug("Invalid pcc_ss_id\n"); 1268 return -ENODEV; 1269 } 1270 pcc_ss_data = pcc_data[pcc_ss_id]; 1271 down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */ 1272 if (pcc_ss_data->platform_owns_pcc) { 1273 ret = check_pcc_chan(pcc_ss_id, false); 1274 if (ret) { 1275 up_read(&pcc_ss_data->pcc_lock); 1276 return ret; 1277 } 1278 } 1279 /* 1280 * Update the pending_write to make sure a PCC CMD_READ will not 1281 * arrive and steal the channel during the switch to write lock 1282 */ 1283 pcc_ss_data->pending_pcc_write_cmd = true; 1284 cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt; 1285 cpc_desc->write_cmd_status = 0; 1286 } 1287 1288 /* 1289 * Skip writing MIN/MAX until Linux knows how to come up with 1290 * useful values. 1291 */ 1292 cpc_write(cpu, desired_reg, perf_ctrls->desired_perf); 1293 1294 if (CPC_IN_PCC(desired_reg)) 1295 up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */ 1296 /* 1297 * This is Phase-II where we transfer the ownership of PCC to Platform 1298 * 1299 * Short Summary: Basically if we think of a group of cppc_set_perf 1300 * requests that happened in short overlapping interval. The last CPU to 1301 * come out of Phase-I will enter Phase-II and ring the doorbell. 1302 * 1303 * We have the following requirements for Phase-II: 1304 * 1. We want to execute Phase-II only when there are no CPUs 1305 * currently executing in Phase-I 1306 * 2. Once we start Phase-II we want to avoid all other CPUs from 1307 * entering Phase-I. 1308 * 3. We want only one CPU among all those who went through Phase-I 1309 * to run phase-II 1310 * 1311 * If write_trylock fails to get the lock and doesn't transfer the 1312 * PCC ownership to the platform, then one of the following will be TRUE 1313 * 1. There is at-least one CPU in Phase-I which will later execute 1314 * write_trylock, so the CPUs in Phase-I will be responsible for 1315 * executing the Phase-II. 1316 * 2. Some other CPU has beaten this CPU to successfully execute the 1317 * write_trylock and has already acquired the write_lock. We know for a 1318 * fact it (other CPU acquiring the write_lock) couldn't have happened 1319 * before this CPU's Phase-I as we held the read_lock. 1320 * 3. Some other CPU executing pcc CMD_READ has stolen the 1321 * down_write, in which case, send_pcc_cmd will check for pending 1322 * CMD_WRITE commands by checking the pending_pcc_write_cmd. 1323 * So this CPU can be certain that its request will be delivered 1324 * So in all cases, this CPU knows that its request will be delivered 1325 * by another CPU and can return 1326 * 1327 * After getting the down_write we still need to check for 1328 * pending_pcc_write_cmd to take care of the following scenario 1329 * The thread running this code could be scheduled out between 1330 * Phase-I and Phase-II. Before it is scheduled back on, another CPU 1331 * could have delivered the request to Platform by triggering the 1332 * doorbell and transferred the ownership of PCC to platform. So this 1333 * avoids triggering an unnecessary doorbell and more importantly before 1334 * triggering the doorbell it makes sure that the PCC channel ownership 1335 * is still with OSPM. 1336 * pending_pcc_write_cmd can also be cleared by a different CPU, if 1337 * there was a pcc CMD_READ waiting on down_write and it steals the lock 1338 * before the pcc CMD_WRITE is completed. pcc_send_cmd checks for this 1339 * case during a CMD_READ and if there are pending writes it delivers 1340 * the write command before servicing the read command 1341 */ 1342 if (CPC_IN_PCC(desired_reg)) { 1343 if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */ 1344 /* Update only if there are pending write commands */ 1345 if (pcc_ss_data->pending_pcc_write_cmd) 1346 send_pcc_cmd(pcc_ss_id, CMD_WRITE); 1347 up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */ 1348 } else 1349 /* Wait until pcc_write_cnt is updated by send_pcc_cmd */ 1350 wait_event(pcc_ss_data->pcc_write_wait_q, 1351 cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt); 1352 1353 /* send_pcc_cmd updates the status in case of failure */ 1354 ret = cpc_desc->write_cmd_status; 1355 } 1356 return ret; 1357} 1358EXPORT_SYMBOL_GPL(cppc_set_perf); 1359 1360/** 1361 * cppc_get_transition_latency - returns frequency transition latency in ns 1362 * 1363 * ACPI CPPC does not explicitly specifiy how a platform can specify the 1364 * transition latency for perfromance change requests. The closest we have 1365 * is the timing information from the PCCT tables which provides the info 1366 * on the number and frequency of PCC commands the platform can handle. 1367 */ 1368unsigned int cppc_get_transition_latency(int cpu_num) 1369{ 1370 /* 1371 * Expected transition latency is based on the PCCT timing values 1372 * Below are definition from ACPI spec: 1373 * pcc_nominal- Expected latency to process a command, in microseconds 1374 * pcc_mpar - The maximum number of periodic requests that the subspace 1375 * channel can support, reported in commands per minute. 0 1376 * indicates no limitation. 1377 * pcc_mrtt - The minimum amount of time that OSPM must wait after the 1378 * completion of a command before issuing the next command, 1379 * in microseconds. 1380 */ 1381 unsigned int latency_ns = 0; 1382 struct cpc_desc *cpc_desc; 1383 struct cpc_register_resource *desired_reg; 1384 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num); 1385 struct cppc_pcc_data *pcc_ss_data; 1386 1387 cpc_desc = per_cpu(cpc_desc_ptr, cpu_num); 1388 if (!cpc_desc) 1389 return CPUFREQ_ETERNAL; 1390 1391 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; 1392 if (!CPC_IN_PCC(desired_reg)) 1393 return CPUFREQ_ETERNAL; 1394 1395 if (pcc_ss_id < 0) 1396 return CPUFREQ_ETERNAL; 1397 1398 pcc_ss_data = pcc_data[pcc_ss_id]; 1399 if (pcc_ss_data->pcc_mpar) 1400 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar); 1401 1402 latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000); 1403 latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000); 1404 1405 return latency_ns; 1406} 1407EXPORT_SYMBOL_GPL(cppc_get_transition_latency); 1408