1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * ACPI support for Intel Lynxpoint LPSS. 4 * 5 * Copyright (C) 2013, Intel Corporation 6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> 7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com> 8 */ 9 10#include <linux/acpi.h> 11#include <linux/clkdev.h> 12#include <linux/clk-provider.h> 13#include <linux/dmi.h> 14#include <linux/err.h> 15#include <linux/io.h> 16#include <linux/mutex.h> 17#include <linux/pci.h> 18#include <linux/platform_device.h> 19#include <linux/platform_data/x86/clk-lpss.h> 20#include <linux/platform_data/x86/pmc_atom.h> 21#include <linux/pm_domain.h> 22#include <linux/pm_runtime.h> 23#include <linux/pwm.h> 24#include <linux/suspend.h> 25#include <linux/delay.h> 26 27#include "internal.h" 28 29#ifdef CONFIG_X86_INTEL_LPSS 30 31#include <asm/cpu_device_id.h> 32#include <asm/intel-family.h> 33#include <asm/iosf_mbi.h> 34 35#define LPSS_ADDR(desc) ((unsigned long)&desc) 36 37#define LPSS_CLK_SIZE 0x04 38#define LPSS_LTR_SIZE 0x18 39 40/* Offsets relative to LPSS_PRIVATE_OFFSET */ 41#define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) 42#define LPSS_RESETS 0x04 43#define LPSS_RESETS_RESET_FUNC BIT(0) 44#define LPSS_RESETS_RESET_APB BIT(1) 45#define LPSS_GENERAL 0x08 46#define LPSS_GENERAL_LTR_MODE_SW BIT(2) 47#define LPSS_GENERAL_UART_RTS_OVRD BIT(3) 48#define LPSS_SW_LTR 0x10 49#define LPSS_AUTO_LTR 0x14 50#define LPSS_LTR_SNOOP_REQ BIT(15) 51#define LPSS_LTR_SNOOP_MASK 0x0000FFFF 52#define LPSS_LTR_SNOOP_LAT_1US 0x800 53#define LPSS_LTR_SNOOP_LAT_32US 0xC00 54#define LPSS_LTR_SNOOP_LAT_SHIFT 5 55#define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 56#define LPSS_LTR_MAX_VAL 0x3FF 57#define LPSS_TX_INT 0x20 58#define LPSS_TX_INT_MASK BIT(1) 59 60#define LPSS_PRV_REG_COUNT 9 61 62/* LPSS Flags */ 63#define LPSS_CLK BIT(0) 64#define LPSS_CLK_GATE BIT(1) 65#define LPSS_CLK_DIVIDER BIT(2) 66#define LPSS_LTR BIT(3) 67#define LPSS_SAVE_CTX BIT(4) 68/* 69 * For some devices the DSDT AML code for another device turns off the device 70 * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff) 71 * as ctx register values. 72 * Luckily these devices always use the same ctx register values, so we can 73 * work around this by saving the ctx registers once on activation. 74 */ 75#define LPSS_SAVE_CTX_ONCE BIT(5) 76#define LPSS_NO_D3_DELAY BIT(6) 77 78struct lpss_private_data; 79 80struct lpss_device_desc { 81 unsigned int flags; 82 const char *clk_con_id; 83 unsigned int prv_offset; 84 size_t prv_size_override; 85 struct property_entry *properties; 86 void (*setup)(struct lpss_private_data *pdata); 87 bool resume_from_noirq; 88}; 89 90static const struct lpss_device_desc lpss_dma_desc = { 91 .flags = LPSS_CLK, 92}; 93 94struct lpss_private_data { 95 struct acpi_device *adev; 96 void __iomem *mmio_base; 97 resource_size_t mmio_size; 98 unsigned int fixed_clk_rate; 99 struct clk *clk; 100 const struct lpss_device_desc *dev_desc; 101 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; 102}; 103 104/* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */ 105static u32 pmc_atom_d3_mask = 0xfe000ffe; 106 107/* LPSS run time quirks */ 108static unsigned int lpss_quirks; 109 110/* 111 * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. 112 * 113 * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover 114 * it can be powered off automatically whenever the last LPSS device goes down. 115 * In case of no power any access to the DMA controller will hang the system. 116 * The behaviour is reproduced on some HP laptops based on Intel BayTrail as 117 * well as on ASuS T100TA transformer. 118 * 119 * This quirk overrides power state of entire LPSS island to keep DMA powered 120 * on whenever we have at least one other device in use. 121 */ 122#define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) 123 124/* UART Component Parameter Register */ 125#define LPSS_UART_CPR 0xF4 126#define LPSS_UART_CPR_AFCE BIT(4) 127 128static void lpss_uart_setup(struct lpss_private_data *pdata) 129{ 130 unsigned int offset; 131 u32 val; 132 133 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; 134 val = readl(pdata->mmio_base + offset); 135 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); 136 137 val = readl(pdata->mmio_base + LPSS_UART_CPR); 138 if (!(val & LPSS_UART_CPR_AFCE)) { 139 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; 140 val = readl(pdata->mmio_base + offset); 141 val |= LPSS_GENERAL_UART_RTS_OVRD; 142 writel(val, pdata->mmio_base + offset); 143 } 144} 145 146static void lpss_deassert_reset(struct lpss_private_data *pdata) 147{ 148 unsigned int offset; 149 u32 val; 150 151 offset = pdata->dev_desc->prv_offset + LPSS_RESETS; 152 val = readl(pdata->mmio_base + offset); 153 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; 154 writel(val, pdata->mmio_base + offset); 155} 156 157/* 158 * BYT PWM used for backlight control by the i915 driver on systems without 159 * the Crystal Cove PMIC. 160 */ 161static struct pwm_lookup byt_pwm_lookup[] = { 162 PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0", 163 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, 164 "pwm-lpss-platform"), 165}; 166 167static void byt_pwm_setup(struct lpss_private_data *pdata) 168{ 169 struct acpi_device *adev = pdata->adev; 170 171 /* Only call pwm_add_table for the first PWM controller */ 172 if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) 173 return; 174 175 pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup)); 176} 177 178#define LPSS_I2C_ENABLE 0x6c 179 180static void byt_i2c_setup(struct lpss_private_data *pdata) 181{ 182 const char *uid_str = acpi_device_uid(pdata->adev); 183 acpi_handle handle = pdata->adev->handle; 184 unsigned long long shared_host = 0; 185 acpi_status status; 186 long uid = 0; 187 188 /* Expected to always be true, but better safe then sorry */ 189 if (uid_str) 190 uid = simple_strtol(uid_str, NULL, 10); 191 192 /* Detect I2C bus shared with PUNIT and ignore its d3 status */ 193 status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host); 194 if (ACPI_SUCCESS(status) && shared_host && uid) 195 pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1)); 196 197 lpss_deassert_reset(pdata); 198 199 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) 200 pdata->fixed_clk_rate = 133000000; 201 202 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); 203} 204 205/* BSW PWM used for backlight control by the i915 driver */ 206static struct pwm_lookup bsw_pwm_lookup[] = { 207 PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0", 208 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, 209 "pwm-lpss-platform"), 210}; 211 212static void bsw_pwm_setup(struct lpss_private_data *pdata) 213{ 214 struct acpi_device *adev = pdata->adev; 215 216 /* Only call pwm_add_table for the first PWM controller */ 217 if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) 218 return; 219 220 pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup)); 221} 222 223static const struct lpss_device_desc lpt_dev_desc = { 224 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR 225 | LPSS_SAVE_CTX, 226 .prv_offset = 0x800, 227}; 228 229static const struct lpss_device_desc lpt_i2c_dev_desc = { 230 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX, 231 .prv_offset = 0x800, 232}; 233 234static struct property_entry uart_properties[] = { 235 PROPERTY_ENTRY_U32("reg-io-width", 4), 236 PROPERTY_ENTRY_U32("reg-shift", 2), 237 PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"), 238 { }, 239}; 240 241static const struct lpss_device_desc lpt_uart_dev_desc = { 242 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR 243 | LPSS_SAVE_CTX, 244 .clk_con_id = "baudclk", 245 .prv_offset = 0x800, 246 .setup = lpss_uart_setup, 247 .properties = uart_properties, 248}; 249 250static const struct lpss_device_desc lpt_sdio_dev_desc = { 251 .flags = LPSS_LTR, 252 .prv_offset = 0x1000, 253 .prv_size_override = 0x1018, 254}; 255 256static const struct lpss_device_desc byt_pwm_dev_desc = { 257 .flags = LPSS_SAVE_CTX, 258 .prv_offset = 0x800, 259 .setup = byt_pwm_setup, 260}; 261 262static const struct lpss_device_desc bsw_pwm_dev_desc = { 263 .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, 264 .prv_offset = 0x800, 265 .setup = bsw_pwm_setup, 266 .resume_from_noirq = true, 267}; 268 269static const struct lpss_device_desc byt_uart_dev_desc = { 270 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, 271 .clk_con_id = "baudclk", 272 .prv_offset = 0x800, 273 .setup = lpss_uart_setup, 274 .properties = uart_properties, 275}; 276 277static const struct lpss_device_desc bsw_uart_dev_desc = { 278 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX 279 | LPSS_NO_D3_DELAY, 280 .clk_con_id = "baudclk", 281 .prv_offset = 0x800, 282 .setup = lpss_uart_setup, 283 .properties = uart_properties, 284}; 285 286static const struct lpss_device_desc byt_spi_dev_desc = { 287 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, 288 .prv_offset = 0x400, 289}; 290 291static const struct lpss_device_desc byt_sdio_dev_desc = { 292 .flags = LPSS_CLK, 293}; 294 295static const struct lpss_device_desc byt_i2c_dev_desc = { 296 .flags = LPSS_CLK | LPSS_SAVE_CTX, 297 .prv_offset = 0x800, 298 .setup = byt_i2c_setup, 299 .resume_from_noirq = true, 300}; 301 302static const struct lpss_device_desc bsw_i2c_dev_desc = { 303 .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, 304 .prv_offset = 0x800, 305 .setup = byt_i2c_setup, 306 .resume_from_noirq = true, 307}; 308 309static const struct lpss_device_desc bsw_spi_dev_desc = { 310 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX 311 | LPSS_NO_D3_DELAY, 312 .prv_offset = 0x400, 313 .setup = lpss_deassert_reset, 314}; 315 316static const struct x86_cpu_id lpss_cpu_ids[] = { 317 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL), 318 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL), 319 {} 320}; 321 322#else 323 324#define LPSS_ADDR(desc) (0UL) 325 326#endif /* CONFIG_X86_INTEL_LPSS */ 327 328static const struct acpi_device_id acpi_lpss_device_ids[] = { 329 /* Generic LPSS devices */ 330 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, 331 332 /* Lynxpoint LPSS devices */ 333 { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, 334 { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, 335 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, 336 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, 337 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, 338 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, 339 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, 340 { "INT33C7", }, 341 342 /* BayTrail LPSS devices */ 343 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, 344 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, 345 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, 346 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, 347 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, 348 { "INT33B2", }, 349 { "INT33FC", }, 350 351 /* Braswell LPSS devices */ 352 { "80862286", LPSS_ADDR(lpss_dma_desc) }, 353 { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, 354 { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, 355 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, 356 { "808622C0", LPSS_ADDR(lpss_dma_desc) }, 357 { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, 358 359 /* Broadwell LPSS devices */ 360 { "INT3430", LPSS_ADDR(lpt_dev_desc) }, 361 { "INT3431", LPSS_ADDR(lpt_dev_desc) }, 362 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, 363 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, 364 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, 365 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, 366 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, 367 { "INT3437", }, 368 369 /* Wildcat Point LPSS devices */ 370 { "INT3438", LPSS_ADDR(lpt_dev_desc) }, 371 372 { } 373}; 374 375#ifdef CONFIG_X86_INTEL_LPSS 376 377static int is_memory(struct acpi_resource *res, void *not_used) 378{ 379 struct resource r; 380 return !acpi_dev_resource_memory(res, &r); 381} 382 383/* LPSS main clock device. */ 384static struct platform_device *lpss_clk_dev; 385 386static inline void lpt_register_clock_device(void) 387{ 388 lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); 389} 390 391static int register_device_clock(struct acpi_device *adev, 392 struct lpss_private_data *pdata) 393{ 394 const struct lpss_device_desc *dev_desc = pdata->dev_desc; 395 const char *devname = dev_name(&adev->dev); 396 struct clk *clk; 397 struct lpss_clk_data *clk_data; 398 const char *parent, *clk_name; 399 void __iomem *prv_base; 400 401 if (!lpss_clk_dev) 402 lpt_register_clock_device(); 403 404 if (IS_ERR(lpss_clk_dev)) 405 return PTR_ERR(lpss_clk_dev); 406 407 clk_data = platform_get_drvdata(lpss_clk_dev); 408 if (!clk_data) 409 return -ENODEV; 410 clk = clk_data->clk; 411 412 if (!pdata->mmio_base 413 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) 414 return -ENODATA; 415 416 parent = clk_data->name; 417 prv_base = pdata->mmio_base + dev_desc->prv_offset; 418 419 if (pdata->fixed_clk_rate) { 420 clk = clk_register_fixed_rate(NULL, devname, parent, 0, 421 pdata->fixed_clk_rate); 422 goto out; 423 } 424 425 if (dev_desc->flags & LPSS_CLK_GATE) { 426 clk = clk_register_gate(NULL, devname, parent, 0, 427 prv_base, 0, 0, NULL); 428 parent = devname; 429 } 430 431 if (dev_desc->flags & LPSS_CLK_DIVIDER) { 432 /* Prevent division by zero */ 433 if (!readl(prv_base)) 434 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); 435 436 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); 437 if (!clk_name) 438 return -ENOMEM; 439 clk = clk_register_fractional_divider(NULL, clk_name, parent, 440 0, prv_base, 441 1, 15, 16, 15, 0, NULL); 442 parent = clk_name; 443 444 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); 445 if (!clk_name) { 446 kfree(parent); 447 return -ENOMEM; 448 } 449 clk = clk_register_gate(NULL, clk_name, parent, 450 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, 451 prv_base, 31, 0, NULL); 452 kfree(parent); 453 kfree(clk_name); 454 } 455out: 456 if (IS_ERR(clk)) 457 return PTR_ERR(clk); 458 459 pdata->clk = clk; 460 clk_register_clkdev(clk, dev_desc->clk_con_id, devname); 461 return 0; 462} 463 464struct lpss_device_links { 465 const char *supplier_hid; 466 const char *supplier_uid; 467 const char *consumer_hid; 468 const char *consumer_uid; 469 u32 flags; 470 const struct dmi_system_id *dep_missing_ids; 471}; 472 473/* Please keep this list sorted alphabetically by vendor and model */ 474static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = { 475 { 476 .matches = { 477 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 478 DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"), 479 }, 480 }, 481 {} 482}; 483 484/* 485 * The _DEP method is used to identify dependencies but instead of creating 486 * device links for every handle in _DEP, only links in the following list are 487 * created. That is necessary because, in the general case, _DEP can refer to 488 * devices that might not have drivers, or that are on different buses, or where 489 * the supplier is not enumerated until after the consumer is probed. 490 */ 491static const struct lpss_device_links lpss_device_links[] = { 492 /* CHT External sdcard slot controller depends on PMIC I2C ctrl */ 493 {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME}, 494 /* CHT iGPU depends on PMIC I2C controller */ 495 {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 496 /* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */ 497 {"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME, 498 i2c1_dep_missing_dmi_ids}, 499 /* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */ 500 {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 501 /* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */ 502 {"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 503}; 504 505static bool acpi_lpss_is_supplier(struct acpi_device *adev, 506 const struct lpss_device_links *link) 507{ 508 return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid); 509} 510 511static bool acpi_lpss_is_consumer(struct acpi_device *adev, 512 const struct lpss_device_links *link) 513{ 514 return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid); 515} 516 517struct hid_uid { 518 const char *hid; 519 const char *uid; 520}; 521 522static int match_hid_uid(struct device *dev, const void *data) 523{ 524 struct acpi_device *adev = ACPI_COMPANION(dev); 525 const struct hid_uid *id = data; 526 527 if (!adev) 528 return 0; 529 530 return acpi_dev_hid_uid_match(adev, id->hid, id->uid); 531} 532 533static struct device *acpi_lpss_find_device(const char *hid, const char *uid) 534{ 535 struct device *dev; 536 537 struct hid_uid data = { 538 .hid = hid, 539 .uid = uid, 540 }; 541 542 dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid); 543 if (dev) 544 return dev; 545 546 return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid); 547} 548 549static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle) 550{ 551 struct acpi_handle_list dep_devices; 552 acpi_status status; 553 int i; 554 555 if (!acpi_has_method(adev->handle, "_DEP")) 556 return false; 557 558 status = acpi_evaluate_reference(adev->handle, "_DEP", NULL, 559 &dep_devices); 560 if (ACPI_FAILURE(status)) { 561 dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n"); 562 return false; 563 } 564 565 for (i = 0; i < dep_devices.count; i++) { 566 if (dep_devices.handles[i] == handle) 567 return true; 568 } 569 570 return false; 571} 572 573static void acpi_lpss_link_consumer(struct device *dev1, 574 const struct lpss_device_links *link) 575{ 576 struct device *dev2; 577 578 dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid); 579 if (!dev2) 580 return; 581 582 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) 583 || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1))) 584 device_link_add(dev2, dev1, link->flags); 585 586 put_device(dev2); 587} 588 589static void acpi_lpss_link_supplier(struct device *dev1, 590 const struct lpss_device_links *link) 591{ 592 struct device *dev2; 593 594 dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid); 595 if (!dev2) 596 return; 597 598 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) 599 || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2))) 600 device_link_add(dev1, dev2, link->flags); 601 602 put_device(dev2); 603} 604 605static void acpi_lpss_create_device_links(struct acpi_device *adev, 606 struct platform_device *pdev) 607{ 608 int i; 609 610 for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) { 611 const struct lpss_device_links *link = &lpss_device_links[i]; 612 613 if (acpi_lpss_is_supplier(adev, link)) 614 acpi_lpss_link_consumer(&pdev->dev, link); 615 616 if (acpi_lpss_is_consumer(adev, link)) 617 acpi_lpss_link_supplier(&pdev->dev, link); 618 } 619} 620 621static int acpi_lpss_create_device(struct acpi_device *adev, 622 const struct acpi_device_id *id) 623{ 624 const struct lpss_device_desc *dev_desc; 625 struct lpss_private_data *pdata; 626 struct resource_entry *rentry; 627 struct list_head resource_list; 628 struct platform_device *pdev; 629 int ret; 630 631 dev_desc = (const struct lpss_device_desc *)id->driver_data; 632 if (!dev_desc) { 633 pdev = acpi_create_platform_device(adev, NULL); 634 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; 635 } 636 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 637 if (!pdata) 638 return -ENOMEM; 639 640 INIT_LIST_HEAD(&resource_list); 641 ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); 642 if (ret < 0) 643 goto err_out; 644 645 list_for_each_entry(rentry, &resource_list, node) 646 if (resource_type(rentry->res) == IORESOURCE_MEM) { 647 if (dev_desc->prv_size_override) 648 pdata->mmio_size = dev_desc->prv_size_override; 649 else 650 pdata->mmio_size = resource_size(rentry->res); 651 pdata->mmio_base = ioremap(rentry->res->start, 652 pdata->mmio_size); 653 break; 654 } 655 656 acpi_dev_free_resource_list(&resource_list); 657 658 if (!pdata->mmio_base) { 659 /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */ 660 adev->pnp.type.platform_id = 0; 661 /* Skip the device, but continue the namespace scan. */ 662 ret = 0; 663 goto err_out; 664 } 665 666 pdata->adev = adev; 667 pdata->dev_desc = dev_desc; 668 669 if (dev_desc->setup) 670 dev_desc->setup(pdata); 671 672 if (dev_desc->flags & LPSS_CLK) { 673 ret = register_device_clock(adev, pdata); 674 if (ret) { 675 /* Skip the device, but continue the namespace scan. */ 676 ret = 0; 677 goto err_out; 678 } 679 } 680 681 /* 682 * This works around a known issue in ACPI tables where LPSS devices 683 * have _PS0 and _PS3 without _PSC (and no power resources), so 684 * acpi_bus_init_power() will assume that the BIOS has put them into D0. 685 */ 686 acpi_device_fix_up_power(adev); 687 688 adev->driver_data = pdata; 689 pdev = acpi_create_platform_device(adev, dev_desc->properties); 690 if (!IS_ERR_OR_NULL(pdev)) { 691 acpi_lpss_create_device_links(adev, pdev); 692 return 1; 693 } 694 695 ret = PTR_ERR(pdev); 696 adev->driver_data = NULL; 697 698 err_out: 699 kfree(pdata); 700 return ret; 701} 702 703static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) 704{ 705 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 706} 707 708static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, 709 unsigned int reg) 710{ 711 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 712} 713 714static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) 715{ 716 struct acpi_device *adev; 717 struct lpss_private_data *pdata; 718 unsigned long flags; 719 int ret; 720 721 ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); 722 if (WARN_ON(ret)) 723 return ret; 724 725 spin_lock_irqsave(&dev->power.lock, flags); 726 if (pm_runtime_suspended(dev)) { 727 ret = -EAGAIN; 728 goto out; 729 } 730 pdata = acpi_driver_data(adev); 731 if (WARN_ON(!pdata || !pdata->mmio_base)) { 732 ret = -ENODEV; 733 goto out; 734 } 735 *val = __lpss_reg_read(pdata, reg); 736 737 out: 738 spin_unlock_irqrestore(&dev->power.lock, flags); 739 return ret; 740} 741 742static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, 743 char *buf) 744{ 745 u32 ltr_value = 0; 746 unsigned int reg; 747 int ret; 748 749 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; 750 ret = lpss_reg_read(dev, reg, <r_value); 751 if (ret) 752 return ret; 753 754 return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); 755} 756 757static ssize_t lpss_ltr_mode_show(struct device *dev, 758 struct device_attribute *attr, char *buf) 759{ 760 u32 ltr_mode = 0; 761 char *outstr; 762 int ret; 763 764 ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); 765 if (ret) 766 return ret; 767 768 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; 769 return sprintf(buf, "%s\n", outstr); 770} 771 772static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); 773static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); 774static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); 775 776static struct attribute *lpss_attrs[] = { 777 &dev_attr_auto_ltr.attr, 778 &dev_attr_sw_ltr.attr, 779 &dev_attr_ltr_mode.attr, 780 NULL, 781}; 782 783static const struct attribute_group lpss_attr_group = { 784 .attrs = lpss_attrs, 785 .name = "lpss_ltr", 786}; 787 788static void acpi_lpss_set_ltr(struct device *dev, s32 val) 789{ 790 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 791 u32 ltr_mode, ltr_val; 792 793 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); 794 if (val < 0) { 795 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { 796 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; 797 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 798 } 799 return; 800 } 801 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; 802 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { 803 ltr_val |= LPSS_LTR_SNOOP_LAT_32US; 804 val = LPSS_LTR_MAX_VAL; 805 } else if (val > LPSS_LTR_MAX_VAL) { 806 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; 807 val >>= LPSS_LTR_SNOOP_LAT_SHIFT; 808 } else { 809 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; 810 } 811 ltr_val |= val; 812 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); 813 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { 814 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; 815 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 816 } 817} 818 819#ifdef CONFIG_PM 820/** 821 * acpi_lpss_save_ctx() - Save the private registers of LPSS device 822 * @dev: LPSS device 823 * @pdata: pointer to the private data of the LPSS device 824 * 825 * Most LPSS devices have private registers which may loose their context when 826 * the device is powered down. acpi_lpss_save_ctx() saves those registers into 827 * prv_reg_ctx array. 828 */ 829static void acpi_lpss_save_ctx(struct device *dev, 830 struct lpss_private_data *pdata) 831{ 832 unsigned int i; 833 834 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 835 unsigned long offset = i * sizeof(u32); 836 837 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); 838 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", 839 pdata->prv_reg_ctx[i], offset); 840 } 841} 842 843/** 844 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device 845 * @dev: LPSS device 846 * @pdata: pointer to the private data of the LPSS device 847 * 848 * Restores the registers that were previously stored with acpi_lpss_save_ctx(). 849 */ 850static void acpi_lpss_restore_ctx(struct device *dev, 851 struct lpss_private_data *pdata) 852{ 853 unsigned int i; 854 855 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 856 unsigned long offset = i * sizeof(u32); 857 858 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); 859 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", 860 pdata->prv_reg_ctx[i], offset); 861 } 862} 863 864static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) 865{ 866 /* 867 * The following delay is needed or the subsequent write operations may 868 * fail. The LPSS devices are actually PCI devices and the PCI spec 869 * expects 10ms delay before the device can be accessed after D3 to D0 870 * transition. However some platforms like BSW does not need this delay. 871 */ 872 unsigned int delay = 10; /* default 10ms delay */ 873 874 if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) 875 delay = 0; 876 877 msleep(delay); 878} 879 880static int acpi_lpss_activate(struct device *dev) 881{ 882 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 883 int ret; 884 885 ret = acpi_dev_resume(dev); 886 if (ret) 887 return ret; 888 889 acpi_lpss_d3_to_d0_delay(pdata); 890 891 /* 892 * This is called only on ->probe() stage where a device is either in 893 * known state defined by BIOS or most likely powered off. Due to this 894 * we have to deassert reset line to be sure that ->probe() will 895 * recognize the device. 896 */ 897 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) 898 lpss_deassert_reset(pdata); 899 900#ifdef CONFIG_PM 901 if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE) 902 acpi_lpss_save_ctx(dev, pdata); 903#endif 904 905 return 0; 906} 907 908static void acpi_lpss_dismiss(struct device *dev) 909{ 910 acpi_dev_suspend(dev, false); 911} 912 913/* IOSF SB for LPSS island */ 914#define LPSS_IOSF_UNIT_LPIOEP 0xA0 915#define LPSS_IOSF_UNIT_LPIO1 0xAB 916#define LPSS_IOSF_UNIT_LPIO2 0xAC 917 918#define LPSS_IOSF_PMCSR 0x84 919#define LPSS_PMCSR_D0 0 920#define LPSS_PMCSR_D3hot 3 921#define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) 922 923#define LPSS_IOSF_GPIODEF0 0x154 924#define LPSS_GPIODEF0_DMA1_D3 BIT(2) 925#define LPSS_GPIODEF0_DMA2_D3 BIT(3) 926#define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) 927#define LPSS_GPIODEF0_DMA_LLP BIT(13) 928 929static DEFINE_MUTEX(lpss_iosf_mutex); 930static bool lpss_iosf_d3_entered = true; 931 932static void lpss_iosf_enter_d3_state(void) 933{ 934 u32 value1 = 0; 935 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; 936 u32 value2 = LPSS_PMCSR_D3hot; 937 u32 mask2 = LPSS_PMCSR_Dx_MASK; 938 /* 939 * PMC provides an information about actual status of the LPSS devices. 940 * Here we read the values related to LPSS power island, i.e. LPSS 941 * devices, excluding both LPSS DMA controllers, along with SCC domain. 942 */ 943 u32 func_dis, d3_sts_0, pmc_status; 944 int ret; 945 946 ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); 947 if (ret) 948 return; 949 950 mutex_lock(&lpss_iosf_mutex); 951 952 ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); 953 if (ret) 954 goto exit; 955 956 /* 957 * Get the status of entire LPSS power island per device basis. 958 * Shutdown both LPSS DMA controllers if and only if all other devices 959 * are already in D3hot. 960 */ 961 pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask; 962 if (pmc_status) 963 goto exit; 964 965 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, 966 LPSS_IOSF_PMCSR, value2, mask2); 967 968 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, 969 LPSS_IOSF_PMCSR, value2, mask2); 970 971 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, 972 LPSS_IOSF_GPIODEF0, value1, mask1); 973 974 lpss_iosf_d3_entered = true; 975 976exit: 977 mutex_unlock(&lpss_iosf_mutex); 978} 979 980static void lpss_iosf_exit_d3_state(void) 981{ 982 u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | 983 LPSS_GPIODEF0_DMA_LLP; 984 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; 985 u32 value2 = LPSS_PMCSR_D0; 986 u32 mask2 = LPSS_PMCSR_Dx_MASK; 987 988 mutex_lock(&lpss_iosf_mutex); 989 990 if (!lpss_iosf_d3_entered) 991 goto exit; 992 993 lpss_iosf_d3_entered = false; 994 995 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, 996 LPSS_IOSF_GPIODEF0, value1, mask1); 997 998 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, 999 LPSS_IOSF_PMCSR, value2, mask2); 1000 1001 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, 1002 LPSS_IOSF_PMCSR, value2, mask2); 1003 1004exit: 1005 mutex_unlock(&lpss_iosf_mutex); 1006} 1007 1008static int acpi_lpss_suspend(struct device *dev, bool wakeup) 1009{ 1010 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1011 int ret; 1012 1013 if (pdata->dev_desc->flags & LPSS_SAVE_CTX) 1014 acpi_lpss_save_ctx(dev, pdata); 1015 1016 ret = acpi_dev_suspend(dev, wakeup); 1017 1018 /* 1019 * This call must be last in the sequence, otherwise PMC will return 1020 * wrong status for devices being about to be powered off. See 1021 * lpss_iosf_enter_d3_state() for further information. 1022 */ 1023 if (acpi_target_system_state() == ACPI_STATE_S0 && 1024 lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) 1025 lpss_iosf_enter_d3_state(); 1026 1027 return ret; 1028} 1029 1030static int acpi_lpss_resume(struct device *dev) 1031{ 1032 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1033 int ret; 1034 1035 /* 1036 * This call is kept first to be in symmetry with 1037 * acpi_lpss_runtime_suspend() one. 1038 */ 1039 if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) 1040 lpss_iosf_exit_d3_state(); 1041 1042 ret = acpi_dev_resume(dev); 1043 if (ret) 1044 return ret; 1045 1046 acpi_lpss_d3_to_d0_delay(pdata); 1047 1048 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) 1049 acpi_lpss_restore_ctx(dev, pdata); 1050 1051 return 0; 1052} 1053 1054#ifdef CONFIG_PM_SLEEP 1055static int acpi_lpss_do_suspend_late(struct device *dev) 1056{ 1057 int ret; 1058 1059 if (dev_pm_skip_suspend(dev)) 1060 return 0; 1061 1062 ret = pm_generic_suspend_late(dev); 1063 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); 1064} 1065 1066static int acpi_lpss_suspend_late(struct device *dev) 1067{ 1068 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1069 1070 if (pdata->dev_desc->resume_from_noirq) 1071 return 0; 1072 1073 return acpi_lpss_do_suspend_late(dev); 1074} 1075 1076static int acpi_lpss_suspend_noirq(struct device *dev) 1077{ 1078 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1079 int ret; 1080 1081 if (pdata->dev_desc->resume_from_noirq) { 1082 /* 1083 * The driver's ->suspend_late callback will be invoked by 1084 * acpi_lpss_do_suspend_late(), with the assumption that the 1085 * driver really wanted to run that code in ->suspend_noirq, but 1086 * it could not run after acpi_dev_suspend() and the driver 1087 * expected the latter to be called in the "late" phase. 1088 */ 1089 ret = acpi_lpss_do_suspend_late(dev); 1090 if (ret) 1091 return ret; 1092 } 1093 1094 return acpi_subsys_suspend_noirq(dev); 1095} 1096 1097static int acpi_lpss_do_resume_early(struct device *dev) 1098{ 1099 int ret = acpi_lpss_resume(dev); 1100 1101 return ret ? ret : pm_generic_resume_early(dev); 1102} 1103 1104static int acpi_lpss_resume_early(struct device *dev) 1105{ 1106 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1107 1108 if (pdata->dev_desc->resume_from_noirq) 1109 return 0; 1110 1111 if (dev_pm_skip_resume(dev)) 1112 return 0; 1113 1114 return acpi_lpss_do_resume_early(dev); 1115} 1116 1117static int acpi_lpss_resume_noirq(struct device *dev) 1118{ 1119 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1120 int ret; 1121 1122 /* Follow acpi_subsys_resume_noirq(). */ 1123 if (dev_pm_skip_resume(dev)) 1124 return 0; 1125 1126 ret = pm_generic_resume_noirq(dev); 1127 if (ret) 1128 return ret; 1129 1130 if (!pdata->dev_desc->resume_from_noirq) 1131 return 0; 1132 1133 /* 1134 * The driver's ->resume_early callback will be invoked by 1135 * acpi_lpss_do_resume_early(), with the assumption that the driver 1136 * really wanted to run that code in ->resume_noirq, but it could not 1137 * run before acpi_dev_resume() and the driver expected the latter to be 1138 * called in the "early" phase. 1139 */ 1140 return acpi_lpss_do_resume_early(dev); 1141} 1142 1143static int acpi_lpss_do_restore_early(struct device *dev) 1144{ 1145 int ret = acpi_lpss_resume(dev); 1146 1147 return ret ? ret : pm_generic_restore_early(dev); 1148} 1149 1150static int acpi_lpss_restore_early(struct device *dev) 1151{ 1152 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1153 1154 if (pdata->dev_desc->resume_from_noirq) 1155 return 0; 1156 1157 return acpi_lpss_do_restore_early(dev); 1158} 1159 1160static int acpi_lpss_restore_noirq(struct device *dev) 1161{ 1162 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1163 int ret; 1164 1165 ret = pm_generic_restore_noirq(dev); 1166 if (ret) 1167 return ret; 1168 1169 if (!pdata->dev_desc->resume_from_noirq) 1170 return 0; 1171 1172 /* This is analogous to what happens in acpi_lpss_resume_noirq(). */ 1173 return acpi_lpss_do_restore_early(dev); 1174} 1175 1176static int acpi_lpss_do_poweroff_late(struct device *dev) 1177{ 1178 int ret = pm_generic_poweroff_late(dev); 1179 1180 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); 1181} 1182 1183static int acpi_lpss_poweroff_late(struct device *dev) 1184{ 1185 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1186 1187 if (dev_pm_skip_suspend(dev)) 1188 return 0; 1189 1190 if (pdata->dev_desc->resume_from_noirq) 1191 return 0; 1192 1193 return acpi_lpss_do_poweroff_late(dev); 1194} 1195 1196static int acpi_lpss_poweroff_noirq(struct device *dev) 1197{ 1198 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1199 1200 if (dev_pm_skip_suspend(dev)) 1201 return 0; 1202 1203 if (pdata->dev_desc->resume_from_noirq) { 1204 /* This is analogous to the acpi_lpss_suspend_noirq() case. */ 1205 int ret = acpi_lpss_do_poweroff_late(dev); 1206 if (ret) 1207 return ret; 1208 } 1209 1210 return pm_generic_poweroff_noirq(dev); 1211} 1212#endif /* CONFIG_PM_SLEEP */ 1213 1214static int acpi_lpss_runtime_suspend(struct device *dev) 1215{ 1216 int ret = pm_generic_runtime_suspend(dev); 1217 1218 return ret ? ret : acpi_lpss_suspend(dev, true); 1219} 1220 1221static int acpi_lpss_runtime_resume(struct device *dev) 1222{ 1223 int ret = acpi_lpss_resume(dev); 1224 1225 return ret ? ret : pm_generic_runtime_resume(dev); 1226} 1227#endif /* CONFIG_PM */ 1228 1229static struct dev_pm_domain acpi_lpss_pm_domain = { 1230#ifdef CONFIG_PM 1231 .activate = acpi_lpss_activate, 1232 .dismiss = acpi_lpss_dismiss, 1233#endif 1234 .ops = { 1235#ifdef CONFIG_PM 1236#ifdef CONFIG_PM_SLEEP 1237 .prepare = acpi_subsys_prepare, 1238 .complete = acpi_subsys_complete, 1239 .suspend = acpi_subsys_suspend, 1240 .suspend_late = acpi_lpss_suspend_late, 1241 .suspend_noirq = acpi_lpss_suspend_noirq, 1242 .resume_noirq = acpi_lpss_resume_noirq, 1243 .resume_early = acpi_lpss_resume_early, 1244 .freeze = acpi_subsys_freeze, 1245 .poweroff = acpi_subsys_poweroff, 1246 .poweroff_late = acpi_lpss_poweroff_late, 1247 .poweroff_noirq = acpi_lpss_poweroff_noirq, 1248 .restore_noirq = acpi_lpss_restore_noirq, 1249 .restore_early = acpi_lpss_restore_early, 1250#endif 1251 .runtime_suspend = acpi_lpss_runtime_suspend, 1252 .runtime_resume = acpi_lpss_runtime_resume, 1253#endif 1254 }, 1255}; 1256 1257static int acpi_lpss_platform_notify(struct notifier_block *nb, 1258 unsigned long action, void *data) 1259{ 1260 struct platform_device *pdev = to_platform_device(data); 1261 struct lpss_private_data *pdata; 1262 struct acpi_device *adev; 1263 const struct acpi_device_id *id; 1264 1265 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); 1266 if (!id || !id->driver_data) 1267 return 0; 1268 1269 if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) 1270 return 0; 1271 1272 pdata = acpi_driver_data(adev); 1273 if (!pdata) 1274 return 0; 1275 1276 if (pdata->mmio_base && 1277 pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { 1278 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); 1279 return 0; 1280 } 1281 1282 switch (action) { 1283 case BUS_NOTIFY_BIND_DRIVER: 1284 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); 1285 break; 1286 case BUS_NOTIFY_DRIVER_NOT_BOUND: 1287 case BUS_NOTIFY_UNBOUND_DRIVER: 1288 dev_pm_domain_set(&pdev->dev, NULL); 1289 break; 1290 case BUS_NOTIFY_ADD_DEVICE: 1291 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); 1292 if (pdata->dev_desc->flags & LPSS_LTR) 1293 return sysfs_create_group(&pdev->dev.kobj, 1294 &lpss_attr_group); 1295 break; 1296 case BUS_NOTIFY_DEL_DEVICE: 1297 if (pdata->dev_desc->flags & LPSS_LTR) 1298 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); 1299 dev_pm_domain_set(&pdev->dev, NULL); 1300 break; 1301 default: 1302 break; 1303 } 1304 1305 return 0; 1306} 1307 1308static struct notifier_block acpi_lpss_nb = { 1309 .notifier_call = acpi_lpss_platform_notify, 1310}; 1311 1312static void acpi_lpss_bind(struct device *dev) 1313{ 1314 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1315 1316 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) 1317 return; 1318 1319 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) 1320 dev->power.set_latency_tolerance = acpi_lpss_set_ltr; 1321 else 1322 dev_err(dev, "MMIO size insufficient to access LTR\n"); 1323} 1324 1325static void acpi_lpss_unbind(struct device *dev) 1326{ 1327 dev->power.set_latency_tolerance = NULL; 1328} 1329 1330static struct acpi_scan_handler lpss_handler = { 1331 .ids = acpi_lpss_device_ids, 1332 .attach = acpi_lpss_create_device, 1333 .bind = acpi_lpss_bind, 1334 .unbind = acpi_lpss_unbind, 1335}; 1336 1337void __init acpi_lpss_init(void) 1338{ 1339 const struct x86_cpu_id *id; 1340 int ret; 1341 1342 ret = lpt_clk_init(); 1343 if (ret) 1344 return; 1345 1346 id = x86_match_cpu(lpss_cpu_ids); 1347 if (id) 1348 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; 1349 1350 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); 1351 acpi_scan_add_handler(&lpss_handler); 1352} 1353 1354#else 1355 1356static struct acpi_scan_handler lpss_handler = { 1357 .ids = acpi_lpss_device_ids, 1358}; 1359 1360void __init acpi_lpss_init(void) 1361{ 1362 acpi_scan_add_handler(&lpss_handler); 1363} 1364 1365#endif /* CONFIG_X86_INTEL_LPSS */ 1366