18c2ecf20Sopenharmony_ci/* 28c2ecf20Sopenharmony_ci * This header file describes this specific Xtensa processor's TIE extensions 38c2ecf20Sopenharmony_ci * that extend basic Xtensa core functionality. It is customized to this 48c2ecf20Sopenharmony_ci * Xtensa processor configuration. 58c2ecf20Sopenharmony_ci * 68c2ecf20Sopenharmony_ci * This file is subject to the terms and conditions of the GNU General Public 78c2ecf20Sopenharmony_ci * License. See the file "COPYING" in the main directory of this archive 88c2ecf20Sopenharmony_ci * for more details. 98c2ecf20Sopenharmony_ci * 108c2ecf20Sopenharmony_ci * Copyright (C) 1999-2007 Tensilica Inc. 118c2ecf20Sopenharmony_ci */ 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci#ifndef _XTENSA_CORE_TIE_H 148c2ecf20Sopenharmony_ci#define _XTENSA_CORE_TIE_H 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci#define XCHAL_CP_NUM 0 /* number of coprocessors */ 178c2ecf20Sopenharmony_ci#define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */ 188c2ecf20Sopenharmony_ci#define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */ 198c2ecf20Sopenharmony_ci#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci/* Filler info for unassigned coprocessors, to simplify arrays etc: */ 228c2ecf20Sopenharmony_ci#define XCHAL_NCP_SA_SIZE 0 238c2ecf20Sopenharmony_ci#define XCHAL_NCP_SA_ALIGN 1 248c2ecf20Sopenharmony_ci#define XCHAL_CP0_SA_SIZE 0 258c2ecf20Sopenharmony_ci#define XCHAL_CP0_SA_ALIGN 1 268c2ecf20Sopenharmony_ci#define XCHAL_CP1_SA_SIZE 0 278c2ecf20Sopenharmony_ci#define XCHAL_CP1_SA_ALIGN 1 288c2ecf20Sopenharmony_ci#define XCHAL_CP2_SA_SIZE 0 298c2ecf20Sopenharmony_ci#define XCHAL_CP2_SA_ALIGN 1 308c2ecf20Sopenharmony_ci#define XCHAL_CP3_SA_SIZE 0 318c2ecf20Sopenharmony_ci#define XCHAL_CP3_SA_ALIGN 1 328c2ecf20Sopenharmony_ci#define XCHAL_CP4_SA_SIZE 0 338c2ecf20Sopenharmony_ci#define XCHAL_CP4_SA_ALIGN 1 348c2ecf20Sopenharmony_ci#define XCHAL_CP5_SA_SIZE 0 358c2ecf20Sopenharmony_ci#define XCHAL_CP5_SA_ALIGN 1 368c2ecf20Sopenharmony_ci#define XCHAL_CP6_SA_SIZE 0 378c2ecf20Sopenharmony_ci#define XCHAL_CP6_SA_ALIGN 1 388c2ecf20Sopenharmony_ci#define XCHAL_CP7_SA_SIZE 0 398c2ecf20Sopenharmony_ci#define XCHAL_CP7_SA_ALIGN 1 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci/* Save area for non-coprocessor optional and custom (TIE) state: */ 428c2ecf20Sopenharmony_ci#define XCHAL_NCP_SA_SIZE 0 438c2ecf20Sopenharmony_ci#define XCHAL_NCP_SA_ALIGN 1 448c2ecf20Sopenharmony_ci 458c2ecf20Sopenharmony_ci/* Total save area for optional and custom state (NCP + CPn): */ 468c2ecf20Sopenharmony_ci#define XCHAL_TOTAL_SA_SIZE 0 /* with 16-byte align padding */ 478c2ecf20Sopenharmony_ci#define XCHAL_TOTAL_SA_ALIGN 1 /* actual minimum alignment */ 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_ci#define XCHAL_NCP_SA_NUM 0 508c2ecf20Sopenharmony_ci#define XCHAL_NCP_SA_LIST(s) 518c2ecf20Sopenharmony_ci#define XCHAL_CP0_SA_NUM 0 528c2ecf20Sopenharmony_ci#define XCHAL_CP0_SA_LIST(s) 538c2ecf20Sopenharmony_ci#define XCHAL_CP1_SA_NUM 0 548c2ecf20Sopenharmony_ci#define XCHAL_CP1_SA_LIST(s) 558c2ecf20Sopenharmony_ci#define XCHAL_CP2_SA_NUM 0 568c2ecf20Sopenharmony_ci#define XCHAL_CP2_SA_LIST(s) 578c2ecf20Sopenharmony_ci#define XCHAL_CP3_SA_NUM 0 588c2ecf20Sopenharmony_ci#define XCHAL_CP3_SA_LIST(s) 598c2ecf20Sopenharmony_ci#define XCHAL_CP4_SA_NUM 0 608c2ecf20Sopenharmony_ci#define XCHAL_CP4_SA_LIST(s) 618c2ecf20Sopenharmony_ci#define XCHAL_CP5_SA_NUM 0 628c2ecf20Sopenharmony_ci#define XCHAL_CP5_SA_LIST(s) 638c2ecf20Sopenharmony_ci#define XCHAL_CP6_SA_NUM 0 648c2ecf20Sopenharmony_ci#define XCHAL_CP6_SA_LIST(s) 658c2ecf20Sopenharmony_ci#define XCHAL_CP7_SA_NUM 0 668c2ecf20Sopenharmony_ci#define XCHAL_CP7_SA_LIST(s) 678c2ecf20Sopenharmony_ci 688c2ecf20Sopenharmony_ci/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ 698c2ecf20Sopenharmony_ci#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 708c2ecf20Sopenharmony_ci 718c2ecf20Sopenharmony_ci#endif /*_XTENSA_CORE_TIE_H*/ 728c2ecf20Sopenharmony_ci 73