18c2ecf20Sopenharmony_ci/* 28c2ecf20Sopenharmony_ci * include/asm-xtensa/pci-bridge.h 38c2ecf20Sopenharmony_ci * 48c2ecf20Sopenharmony_ci * This file is subject to the terms and conditions of the GNU General 58c2ecf20Sopenharmony_ci * Public License. See the file "COPYING" in the main directory of 68c2ecf20Sopenharmony_ci * this archive for more details. 78c2ecf20Sopenharmony_ci * 88c2ecf20Sopenharmony_ci * Copyright (C) 2005 Tensilica Inc. 98c2ecf20Sopenharmony_ci */ 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci#ifndef _XTENSA_PCI_BRIDGE_H 128c2ecf20Sopenharmony_ci#define _XTENSA_PCI_BRIDGE_H 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_cistruct device_node; 158c2ecf20Sopenharmony_cistruct pci_controller; 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci/* 188c2ecf20Sopenharmony_ci * pciauto_bus_scan() enumerates the pci space. 198c2ecf20Sopenharmony_ci */ 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ciextern int pciauto_bus_scan(struct pci_controller *, int); 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_cistruct pci_space { 248c2ecf20Sopenharmony_ci unsigned long start; 258c2ecf20Sopenharmony_ci unsigned long end; 268c2ecf20Sopenharmony_ci unsigned long base; 278c2ecf20Sopenharmony_ci}; 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci/* 308c2ecf20Sopenharmony_ci * Structure of a PCI controller (host bridge) 318c2ecf20Sopenharmony_ci */ 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_cistruct pci_controller { 348c2ecf20Sopenharmony_ci int index; /* used for pci_controller_num */ 358c2ecf20Sopenharmony_ci struct pci_controller *next; 368c2ecf20Sopenharmony_ci struct pci_bus *bus; 378c2ecf20Sopenharmony_ci void *arch_data; 388c2ecf20Sopenharmony_ci 398c2ecf20Sopenharmony_ci int first_busno; 408c2ecf20Sopenharmony_ci int last_busno; 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ci struct pci_ops *ops; 438c2ecf20Sopenharmony_ci volatile unsigned int *cfg_addr; 448c2ecf20Sopenharmony_ci volatile unsigned char *cfg_data; 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci /* Currently, we limit ourselves to 1 IO range and 3 mem 478c2ecf20Sopenharmony_ci * ranges since the common pci_bus structure can't handle more 488c2ecf20Sopenharmony_ci */ 498c2ecf20Sopenharmony_ci struct resource io_resource; 508c2ecf20Sopenharmony_ci struct resource mem_resources[3]; 518c2ecf20Sopenharmony_ci int mem_resource_count; 528c2ecf20Sopenharmony_ci 538c2ecf20Sopenharmony_ci /* Host bridge I/O and Memory space 548c2ecf20Sopenharmony_ci * Used for BAR placement algorithms 558c2ecf20Sopenharmony_ci */ 568c2ecf20Sopenharmony_ci struct pci_space io_space; 578c2ecf20Sopenharmony_ci struct pci_space mem_space; 588c2ecf20Sopenharmony_ci 598c2ecf20Sopenharmony_ci /* Return the interrupt number fo a device. */ 608c2ecf20Sopenharmony_ci int (*map_irq)(struct pci_dev*, u8, u8); 618c2ecf20Sopenharmony_ci 628c2ecf20Sopenharmony_ci}; 638c2ecf20Sopenharmony_ci 648c2ecf20Sopenharmony_cistatic inline void pcibios_init_resource(struct resource *res, 658c2ecf20Sopenharmony_ci unsigned long start, unsigned long end, int flags, char *name) 668c2ecf20Sopenharmony_ci{ 678c2ecf20Sopenharmony_ci res->start = start; 688c2ecf20Sopenharmony_ci res->end = end; 698c2ecf20Sopenharmony_ci res->flags = flags; 708c2ecf20Sopenharmony_ci res->name = name; 718c2ecf20Sopenharmony_ci res->parent = NULL; 728c2ecf20Sopenharmony_ci res->sibling = NULL; 738c2ecf20Sopenharmony_ci res->child = NULL; 748c2ecf20Sopenharmony_ci} 758c2ecf20Sopenharmony_ci 768c2ecf20Sopenharmony_ci 778c2ecf20Sopenharmony_ci/* These are used for config access before all the PCI probing has been done. */ 788c2ecf20Sopenharmony_ciint early_read_config_byte(struct pci_controller*, int, int, int, u8*); 798c2ecf20Sopenharmony_ciint early_read_config_word(struct pci_controller*, int, int, int, u16*); 808c2ecf20Sopenharmony_ciint early_read_config_dword(struct pci_controller*, int, int, int, u32*); 818c2ecf20Sopenharmony_ciint early_write_config_byte(struct pci_controller*, int, int, int, u8); 828c2ecf20Sopenharmony_ciint early_write_config_word(struct pci_controller*, int, int, int, u16); 838c2ecf20Sopenharmony_ciint early_write_config_dword(struct pci_controller*, int, int, int, u32); 848c2ecf20Sopenharmony_ci 858c2ecf20Sopenharmony_ci#endif /* _XTENSA_PCI_BRIDGE_H */ 86