18c2ecf20Sopenharmony_ci/* 28c2ecf20Sopenharmony_ci * Xtensa MX interrupt distributor 38c2ecf20Sopenharmony_ci * 48c2ecf20Sopenharmony_ci * This file is subject to the terms and conditions of the GNU General Public 58c2ecf20Sopenharmony_ci * License. See the file "COPYING" in the main directory of this archive 68c2ecf20Sopenharmony_ci * for more details. 78c2ecf20Sopenharmony_ci * 88c2ecf20Sopenharmony_ci * Copyright (C) 2008 - 2013 Tensilica Inc. 98c2ecf20Sopenharmony_ci */ 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci#ifndef _XTENSA_MXREGS_H 128c2ecf20Sopenharmony_ci#define _XTENSA_MXREGS_H 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci/* 158c2ecf20Sopenharmony_ci * RER/WER at, as Read/write external register 168c2ecf20Sopenharmony_ci * at: value 178c2ecf20Sopenharmony_ci * as: address 188c2ecf20Sopenharmony_ci * 198c2ecf20Sopenharmony_ci * Address Value 208c2ecf20Sopenharmony_ci * 00nn 0...0p..p Interrupt Routing, route IRQ n to processor p 218c2ecf20Sopenharmony_ci * 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p 228c2ecf20Sopenharmony_ci * 0180 0...0m..m Clear enable specified by mask (m) 238c2ecf20Sopenharmony_ci * 0184 0...0m..m Set enable specified by mask (m) 248c2ecf20Sopenharmony_ci * 0190 0...0x..x 8-bit IPI partition register 258c2ecf20Sopenharmony_ci * VVVVVVVVPPPPUUUUUUUUUUUUUUUUU 268c2ecf20Sopenharmony_ci * V (10-bit) Release/Version 278c2ecf20Sopenharmony_ci * P ( 4-bit) Number of cores - 1 288c2ecf20Sopenharmony_ci * U (18-bit) ID 298c2ecf20Sopenharmony_ci * 01a0 i.......i 32-bit ConfigID 308c2ecf20Sopenharmony_ci * 0200 0...0m..m RunStall core 'n' 318c2ecf20Sopenharmony_ci * 0220 c Cache coherency enabled 328c2ecf20Sopenharmony_ci */ 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ci#define MIROUT(irq) (0x000 + (irq)) 358c2ecf20Sopenharmony_ci#define MIPICAUSE(cpu) (0x100 + (cpu)) 368c2ecf20Sopenharmony_ci#define MIPISET(cause) (0x140 + (cause)) 378c2ecf20Sopenharmony_ci#define MIENG 0x180 388c2ecf20Sopenharmony_ci#define MIENGSET 0x184 398c2ecf20Sopenharmony_ci#define MIASG 0x188 /* Read Global Assert Register */ 408c2ecf20Sopenharmony_ci#define MIASGSET 0x18c /* Set Global Addert Regiter */ 418c2ecf20Sopenharmony_ci#define MIPIPART 0x190 428c2ecf20Sopenharmony_ci#define SYSCFGID 0x1a0 438c2ecf20Sopenharmony_ci#define MPSCORE 0x200 448c2ecf20Sopenharmony_ci#define CCON 0x220 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci#endif /* _XTENSA_MXREGS_H */ 47