1#include <linux/gfp.h> 2#include <linux/initrd.h> 3#include <linux/ioport.h> 4#include <linux/swap.h> 5#include <linux/memblock.h> 6#include <linux/swapfile.h> 7#include <linux/swapops.h> 8#include <linux/kmemleak.h> 9#include <linux/sched/task.h> 10#include <linux/sched/mm.h> 11 12#include <asm/set_memory.h> 13#include <asm/cpu_device_id.h> 14#include <asm/e820/api.h> 15#include <asm/init.h> 16#include <asm/page.h> 17#include <asm/page_types.h> 18#include <asm/sections.h> 19#include <asm/setup.h> 20#include <asm/tlbflush.h> 21#include <asm/tlb.h> 22#include <asm/proto.h> 23#include <asm/dma.h> /* for MAX_DMA_PFN */ 24#include <asm/microcode.h> 25#include <asm/kaslr.h> 26#include <asm/hypervisor.h> 27#include <asm/cpufeature.h> 28#include <asm/pti.h> 29#include <asm/text-patching.h> 30#include <asm/memtype.h> 31#include <asm/paravirt.h> 32 33/* 34 * We need to define the tracepoints somewhere, and tlb.c 35 * is only compied when SMP=y. 36 */ 37#define CREATE_TRACE_POINTS 38#include <trace/events/tlb.h> 39 40#include "mm_internal.h" 41 42/* 43 * Tables translating between page_cache_type_t and pte encoding. 44 * 45 * The default values are defined statically as minimal supported mode; 46 * WC and WT fall back to UC-. pat_init() updates these values to support 47 * more cache modes, WC and WT, when it is safe to do so. See pat_init() 48 * for the details. Note, __early_ioremap() used during early boot-time 49 * takes pgprot_t (pte encoding) and does not use these tables. 50 * 51 * Index into __cachemode2pte_tbl[] is the cachemode. 52 * 53 * Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte 54 * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2. 55 */ 56static uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = { 57 [_PAGE_CACHE_MODE_WB ] = 0 | 0 , 58 [_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD, 59 [_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD, 60 [_PAGE_CACHE_MODE_UC ] = _PAGE_PWT | _PAGE_PCD, 61 [_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD, 62 [_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD, 63}; 64 65unsigned long cachemode2protval(enum page_cache_mode pcm) 66{ 67 if (likely(pcm == 0)) 68 return 0; 69 return __cachemode2pte_tbl[pcm]; 70} 71EXPORT_SYMBOL(cachemode2protval); 72 73static uint8_t __pte2cachemode_tbl[8] = { 74 [__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB, 75 [__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_UC_MINUS, 76 [__pte2cm_idx( 0 | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC_MINUS, 77 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC, 78 [__pte2cm_idx( 0 | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_WB, 79 [__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS, 80 [__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS, 81 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC, 82}; 83 84/* 85 * Check that the write-protect PAT entry is set for write-protect. 86 * To do this without making assumptions how PAT has been set up (Xen has 87 * another layout than the kernel), translate the _PAGE_CACHE_MODE_WP cache 88 * mode via the __cachemode2pte_tbl[] into protection bits (those protection 89 * bits will select a cache mode of WP or better), and then translate the 90 * protection bits back into the cache mode using __pte2cm_idx() and the 91 * __pte2cachemode_tbl[] array. This will return the really used cache mode. 92 */ 93bool x86_has_pat_wp(void) 94{ 95 uint16_t prot = __cachemode2pte_tbl[_PAGE_CACHE_MODE_WP]; 96 97 return __pte2cachemode_tbl[__pte2cm_idx(prot)] == _PAGE_CACHE_MODE_WP; 98} 99 100enum page_cache_mode pgprot2cachemode(pgprot_t pgprot) 101{ 102 unsigned long masked; 103 104 masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK; 105 if (likely(masked == 0)) 106 return 0; 107 return __pte2cachemode_tbl[__pte2cm_idx(masked)]; 108} 109 110static unsigned long __initdata pgt_buf_start; 111static unsigned long __initdata pgt_buf_end; 112static unsigned long __initdata pgt_buf_top; 113 114static unsigned long min_pfn_mapped; 115 116static bool __initdata can_use_brk_pgt = true; 117 118/* 119 * Pages returned are already directly mapped. 120 * 121 * Changing that is likely to break Xen, see commit: 122 * 123 * 279b706 x86,xen: introduce x86_init.mapping.pagetable_reserve 124 * 125 * for detailed information. 126 */ 127__ref void *alloc_low_pages(unsigned int num) 128{ 129 unsigned long pfn; 130 int i; 131 132 if (after_bootmem) { 133 unsigned int order; 134 135 order = get_order((unsigned long)num << PAGE_SHIFT); 136 return (void *)__get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 137 } 138 139 if ((pgt_buf_end + num) > pgt_buf_top || !can_use_brk_pgt) { 140 unsigned long ret = 0; 141 142 if (min_pfn_mapped < max_pfn_mapped) { 143 ret = memblock_find_in_range( 144 min_pfn_mapped << PAGE_SHIFT, 145 max_pfn_mapped << PAGE_SHIFT, 146 PAGE_SIZE * num , PAGE_SIZE); 147 } 148 if (ret) 149 memblock_reserve(ret, PAGE_SIZE * num); 150 else if (can_use_brk_pgt) 151 ret = __pa(extend_brk(PAGE_SIZE * num, PAGE_SIZE)); 152 153 if (!ret) 154 panic("alloc_low_pages: can not alloc memory"); 155 156 pfn = ret >> PAGE_SHIFT; 157 } else { 158 pfn = pgt_buf_end; 159 pgt_buf_end += num; 160 } 161 162 for (i = 0; i < num; i++) { 163 void *adr; 164 165 adr = __va((pfn + i) << PAGE_SHIFT); 166 clear_page(adr); 167 } 168 169 return __va(pfn << PAGE_SHIFT); 170} 171 172/* 173 * By default need 3 4k for initial PMD_SIZE, 3 4k for 0-ISA_END_ADDRESS. 174 * With KASLR memory randomization, depending on the machine e820 memory 175 * and the PUD alignment. We may need twice more pages when KASLR memory 176 * randomization is enabled. 177 */ 178#ifndef CONFIG_RANDOMIZE_MEMORY 179#define INIT_PGD_PAGE_COUNT 6 180#else 181#define INIT_PGD_PAGE_COUNT 12 182#endif 183#define INIT_PGT_BUF_SIZE (INIT_PGD_PAGE_COUNT * PAGE_SIZE) 184RESERVE_BRK(early_pgt_alloc, INIT_PGT_BUF_SIZE); 185void __init early_alloc_pgt_buf(void) 186{ 187 unsigned long tables = INIT_PGT_BUF_SIZE; 188 phys_addr_t base; 189 190 base = __pa(extend_brk(tables, PAGE_SIZE)); 191 192 pgt_buf_start = base >> PAGE_SHIFT; 193 pgt_buf_end = pgt_buf_start; 194 pgt_buf_top = pgt_buf_start + (tables >> PAGE_SHIFT); 195} 196 197int after_bootmem; 198 199early_param_on_off("gbpages", "nogbpages", direct_gbpages, CONFIG_X86_DIRECT_GBPAGES); 200 201struct map_range { 202 unsigned long start; 203 unsigned long end; 204 unsigned page_size_mask; 205}; 206 207static int page_size_mask; 208 209/* 210 * Save some of cr4 feature set we're using (e.g. Pentium 4MB 211 * enable and PPro Global page enable), so that any CPU's that boot 212 * up after us can get the correct flags. Invoked on the boot CPU. 213 */ 214static inline void cr4_set_bits_and_update_boot(unsigned long mask) 215{ 216 mmu_cr4_features |= mask; 217 if (trampoline_cr4_features) 218 *trampoline_cr4_features = mmu_cr4_features; 219 cr4_set_bits(mask); 220} 221 222static void __init probe_page_size_mask(void) 223{ 224 /* 225 * For pagealloc debugging, identity mapping will use small pages. 226 * This will simplify cpa(), which otherwise needs to support splitting 227 * large pages into small in interrupt context, etc. 228 */ 229 if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled()) 230 page_size_mask |= 1 << PG_LEVEL_2M; 231 else 232 direct_gbpages = 0; 233 234 /* Enable PSE if available */ 235 if (boot_cpu_has(X86_FEATURE_PSE)) 236 cr4_set_bits_and_update_boot(X86_CR4_PSE); 237 238 /* Enable PGE if available */ 239 __supported_pte_mask &= ~_PAGE_GLOBAL; 240 if (boot_cpu_has(X86_FEATURE_PGE)) { 241 cr4_set_bits_and_update_boot(X86_CR4_PGE); 242 __supported_pte_mask |= _PAGE_GLOBAL; 243 } 244 245 /* By the default is everything supported: */ 246 __default_kernel_pte_mask = __supported_pte_mask; 247 /* Except when with PTI where the kernel is mostly non-Global: */ 248 if (cpu_feature_enabled(X86_FEATURE_PTI)) 249 __default_kernel_pte_mask &= ~_PAGE_GLOBAL; 250 251 /* Enable 1 GB linear kernel mappings if available: */ 252 if (direct_gbpages && boot_cpu_has(X86_FEATURE_GBPAGES)) { 253 printk(KERN_INFO "Using GB pages for direct mapping\n"); 254 page_size_mask |= 1 << PG_LEVEL_1G; 255 } else { 256 direct_gbpages = 0; 257 } 258} 259 260#define INTEL_MATCH(_model) { .vendor = X86_VENDOR_INTEL, \ 261 .family = 6, \ 262 .model = _model, \ 263 } 264/* 265 * INVLPG may not properly flush Global entries 266 * on these CPUs when PCIDs are enabled. 267 */ 268static const struct x86_cpu_id invlpg_miss_ids[] = { 269 INTEL_MATCH(INTEL_FAM6_ALDERLAKE ), 270 INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ), 271 INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ), 272 INTEL_MATCH(INTEL_FAM6_RAPTORLAKE ), 273 INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P), 274 INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S), 275 {} 276}; 277 278static void setup_pcid(void) 279{ 280 if (!IS_ENABLED(CONFIG_X86_64)) 281 return; 282 283 if (!boot_cpu_has(X86_FEATURE_PCID)) 284 return; 285 286 if (x86_match_cpu(invlpg_miss_ids)) { 287 pr_info("Incomplete global flushes, disabling PCID"); 288 setup_clear_cpu_cap(X86_FEATURE_PCID); 289 return; 290 } 291 292 if (boot_cpu_has(X86_FEATURE_PGE)) { 293 /* 294 * This can't be cr4_set_bits_and_update_boot() -- the 295 * trampoline code can't handle CR4.PCIDE and it wouldn't 296 * do any good anyway. Despite the name, 297 * cr4_set_bits_and_update_boot() doesn't actually cause 298 * the bits in question to remain set all the way through 299 * the secondary boot asm. 300 * 301 * Instead, we brute-force it and set CR4.PCIDE manually in 302 * start_secondary(). 303 */ 304 cr4_set_bits(X86_CR4_PCIDE); 305 306 /* 307 * INVPCID's single-context modes (2/3) only work if we set 308 * X86_CR4_PCIDE, *and* we INVPCID support. It's unusable 309 * on systems that have X86_CR4_PCIDE clear, or that have 310 * no INVPCID support at all. 311 */ 312 if (boot_cpu_has(X86_FEATURE_INVPCID)) 313 setup_force_cpu_cap(X86_FEATURE_INVPCID_SINGLE); 314 } else { 315 /* 316 * flush_tlb_all(), as currently implemented, won't work if 317 * PCID is on but PGE is not. Since that combination 318 * doesn't exist on real hardware, there's no reason to try 319 * to fully support it, but it's polite to avoid corrupting 320 * data if we're on an improperly configured VM. 321 */ 322 setup_clear_cpu_cap(X86_FEATURE_PCID); 323 } 324} 325 326#ifdef CONFIG_X86_32 327#define NR_RANGE_MR 3 328#else /* CONFIG_X86_64 */ 329#define NR_RANGE_MR 5 330#endif 331 332static int __meminit save_mr(struct map_range *mr, int nr_range, 333 unsigned long start_pfn, unsigned long end_pfn, 334 unsigned long page_size_mask) 335{ 336 if (start_pfn < end_pfn) { 337 if (nr_range >= NR_RANGE_MR) 338 panic("run out of range for init_memory_mapping\n"); 339 mr[nr_range].start = start_pfn<<PAGE_SHIFT; 340 mr[nr_range].end = end_pfn<<PAGE_SHIFT; 341 mr[nr_range].page_size_mask = page_size_mask; 342 nr_range++; 343 } 344 345 return nr_range; 346} 347 348/* 349 * adjust the page_size_mask for small range to go with 350 * big page size instead small one if nearby are ram too. 351 */ 352static void __ref adjust_range_page_size_mask(struct map_range *mr, 353 int nr_range) 354{ 355 int i; 356 357 for (i = 0; i < nr_range; i++) { 358 if ((page_size_mask & (1<<PG_LEVEL_2M)) && 359 !(mr[i].page_size_mask & (1<<PG_LEVEL_2M))) { 360 unsigned long start = round_down(mr[i].start, PMD_SIZE); 361 unsigned long end = round_up(mr[i].end, PMD_SIZE); 362 363#ifdef CONFIG_X86_32 364 if ((end >> PAGE_SHIFT) > max_low_pfn) 365 continue; 366#endif 367 368 if (memblock_is_region_memory(start, end - start)) 369 mr[i].page_size_mask |= 1<<PG_LEVEL_2M; 370 } 371 if ((page_size_mask & (1<<PG_LEVEL_1G)) && 372 !(mr[i].page_size_mask & (1<<PG_LEVEL_1G))) { 373 unsigned long start = round_down(mr[i].start, PUD_SIZE); 374 unsigned long end = round_up(mr[i].end, PUD_SIZE); 375 376 if (memblock_is_region_memory(start, end - start)) 377 mr[i].page_size_mask |= 1<<PG_LEVEL_1G; 378 } 379 } 380} 381 382static const char *page_size_string(struct map_range *mr) 383{ 384 static const char str_1g[] = "1G"; 385 static const char str_2m[] = "2M"; 386 static const char str_4m[] = "4M"; 387 static const char str_4k[] = "4k"; 388 389 if (mr->page_size_mask & (1<<PG_LEVEL_1G)) 390 return str_1g; 391 /* 392 * 32-bit without PAE has a 4M large page size. 393 * PG_LEVEL_2M is misnamed, but we can at least 394 * print out the right size in the string. 395 */ 396 if (IS_ENABLED(CONFIG_X86_32) && 397 !IS_ENABLED(CONFIG_X86_PAE) && 398 mr->page_size_mask & (1<<PG_LEVEL_2M)) 399 return str_4m; 400 401 if (mr->page_size_mask & (1<<PG_LEVEL_2M)) 402 return str_2m; 403 404 return str_4k; 405} 406 407static int __meminit split_mem_range(struct map_range *mr, int nr_range, 408 unsigned long start, 409 unsigned long end) 410{ 411 unsigned long start_pfn, end_pfn, limit_pfn; 412 unsigned long pfn; 413 int i; 414 415 limit_pfn = PFN_DOWN(end); 416 417 /* head if not big page alignment ? */ 418 pfn = start_pfn = PFN_DOWN(start); 419#ifdef CONFIG_X86_32 420 /* 421 * Don't use a large page for the first 2/4MB of memory 422 * because there are often fixed size MTRRs in there 423 * and overlapping MTRRs into large pages can cause 424 * slowdowns. 425 */ 426 if (pfn == 0) 427 end_pfn = PFN_DOWN(PMD_SIZE); 428 else 429 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 430#else /* CONFIG_X86_64 */ 431 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 432#endif 433 if (end_pfn > limit_pfn) 434 end_pfn = limit_pfn; 435 if (start_pfn < end_pfn) { 436 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); 437 pfn = end_pfn; 438 } 439 440 /* big page (2M) range */ 441 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 442#ifdef CONFIG_X86_32 443 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 444#else /* CONFIG_X86_64 */ 445 end_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE)); 446 if (end_pfn > round_down(limit_pfn, PFN_DOWN(PMD_SIZE))) 447 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 448#endif 449 450 if (start_pfn < end_pfn) { 451 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 452 page_size_mask & (1<<PG_LEVEL_2M)); 453 pfn = end_pfn; 454 } 455 456#ifdef CONFIG_X86_64 457 /* big page (1G) range */ 458 start_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE)); 459 end_pfn = round_down(limit_pfn, PFN_DOWN(PUD_SIZE)); 460 if (start_pfn < end_pfn) { 461 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 462 page_size_mask & 463 ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G))); 464 pfn = end_pfn; 465 } 466 467 /* tail is not big page (1G) alignment */ 468 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 469 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 470 if (start_pfn < end_pfn) { 471 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 472 page_size_mask & (1<<PG_LEVEL_2M)); 473 pfn = end_pfn; 474 } 475#endif 476 477 /* tail is not big page (2M) alignment */ 478 start_pfn = pfn; 479 end_pfn = limit_pfn; 480 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); 481 482 if (!after_bootmem) 483 adjust_range_page_size_mask(mr, nr_range); 484 485 /* try to merge same page size and continuous */ 486 for (i = 0; nr_range > 1 && i < nr_range - 1; i++) { 487 unsigned long old_start; 488 if (mr[i].end != mr[i+1].start || 489 mr[i].page_size_mask != mr[i+1].page_size_mask) 490 continue; 491 /* move it */ 492 old_start = mr[i].start; 493 memmove(&mr[i], &mr[i+1], 494 (nr_range - 1 - i) * sizeof(struct map_range)); 495 mr[i--].start = old_start; 496 nr_range--; 497 } 498 499 for (i = 0; i < nr_range; i++) 500 pr_debug(" [mem %#010lx-%#010lx] page %s\n", 501 mr[i].start, mr[i].end - 1, 502 page_size_string(&mr[i])); 503 504 return nr_range; 505} 506 507struct range pfn_mapped[E820_MAX_ENTRIES]; 508int nr_pfn_mapped; 509 510static void add_pfn_range_mapped(unsigned long start_pfn, unsigned long end_pfn) 511{ 512 nr_pfn_mapped = add_range_with_merge(pfn_mapped, E820_MAX_ENTRIES, 513 nr_pfn_mapped, start_pfn, end_pfn); 514 nr_pfn_mapped = clean_sort_range(pfn_mapped, E820_MAX_ENTRIES); 515 516 max_pfn_mapped = max(max_pfn_mapped, end_pfn); 517 518 if (start_pfn < (1UL<<(32-PAGE_SHIFT))) 519 max_low_pfn_mapped = max(max_low_pfn_mapped, 520 min(end_pfn, 1UL<<(32-PAGE_SHIFT))); 521} 522 523bool pfn_range_is_mapped(unsigned long start_pfn, unsigned long end_pfn) 524{ 525 int i; 526 527 for (i = 0; i < nr_pfn_mapped; i++) 528 if ((start_pfn >= pfn_mapped[i].start) && 529 (end_pfn <= pfn_mapped[i].end)) 530 return true; 531 532 return false; 533} 534 535/* 536 * Setup the direct mapping of the physical memory at PAGE_OFFSET. 537 * This runs before bootmem is initialized and gets pages directly from 538 * the physical memory. To access them they are temporarily mapped. 539 */ 540unsigned long __ref init_memory_mapping(unsigned long start, 541 unsigned long end, pgprot_t prot) 542{ 543 struct map_range mr[NR_RANGE_MR]; 544 unsigned long ret = 0; 545 int nr_range, i; 546 547 pr_debug("init_memory_mapping: [mem %#010lx-%#010lx]\n", 548 start, end - 1); 549 550 memset(mr, 0, sizeof(mr)); 551 nr_range = split_mem_range(mr, 0, start, end); 552 553 for (i = 0; i < nr_range; i++) 554 ret = kernel_physical_mapping_init(mr[i].start, mr[i].end, 555 mr[i].page_size_mask, 556 prot); 557 558 add_pfn_range_mapped(start >> PAGE_SHIFT, ret >> PAGE_SHIFT); 559 560 return ret >> PAGE_SHIFT; 561} 562 563/* 564 * We need to iterate through the E820 memory map and create direct mappings 565 * for only E820_TYPE_RAM and E820_KERN_RESERVED regions. We cannot simply 566 * create direct mappings for all pfns from [0 to max_low_pfn) and 567 * [4GB to max_pfn) because of possible memory holes in high addresses 568 * that cannot be marked as UC by fixed/variable range MTRRs. 569 * Depending on the alignment of E820 ranges, this may possibly result 570 * in using smaller size (i.e. 4K instead of 2M or 1G) page tables. 571 * 572 * init_mem_mapping() calls init_range_memory_mapping() with big range. 573 * That range would have hole in the middle or ends, and only ram parts 574 * will be mapped in init_range_memory_mapping(). 575 */ 576static unsigned long __init init_range_memory_mapping( 577 unsigned long r_start, 578 unsigned long r_end) 579{ 580 unsigned long start_pfn, end_pfn; 581 unsigned long mapped_ram_size = 0; 582 int i; 583 584 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) { 585 u64 start = clamp_val(PFN_PHYS(start_pfn), r_start, r_end); 586 u64 end = clamp_val(PFN_PHYS(end_pfn), r_start, r_end); 587 if (start >= end) 588 continue; 589 590 /* 591 * if it is overlapping with brk pgt, we need to 592 * alloc pgt buf from memblock instead. 593 */ 594 can_use_brk_pgt = max(start, (u64)pgt_buf_end<<PAGE_SHIFT) >= 595 min(end, (u64)pgt_buf_top<<PAGE_SHIFT); 596 init_memory_mapping(start, end, PAGE_KERNEL); 597 mapped_ram_size += end - start; 598 can_use_brk_pgt = true; 599 } 600 601 return mapped_ram_size; 602} 603 604static unsigned long __init get_new_step_size(unsigned long step_size) 605{ 606 /* 607 * Initial mapped size is PMD_SIZE (2M). 608 * We can not set step_size to be PUD_SIZE (1G) yet. 609 * In worse case, when we cross the 1G boundary, and 610 * PG_LEVEL_2M is not set, we will need 1+1+512 pages (2M + 8k) 611 * to map 1G range with PTE. Hence we use one less than the 612 * difference of page table level shifts. 613 * 614 * Don't need to worry about overflow in the top-down case, on 32bit, 615 * when step_size is 0, round_down() returns 0 for start, and that 616 * turns it into 0x100000000ULL. 617 * In the bottom-up case, round_up(x, 0) returns 0 though too, which 618 * needs to be taken into consideration by the code below. 619 */ 620 return step_size << (PMD_SHIFT - PAGE_SHIFT - 1); 621} 622 623/** 624 * memory_map_top_down - Map [map_start, map_end) top down 625 * @map_start: start address of the target memory range 626 * @map_end: end address of the target memory range 627 * 628 * This function will setup direct mapping for memory range 629 * [map_start, map_end) in top-down. That said, the page tables 630 * will be allocated at the end of the memory, and we map the 631 * memory in top-down. 632 */ 633static void __init memory_map_top_down(unsigned long map_start, 634 unsigned long map_end) 635{ 636 unsigned long real_end, start, last_start; 637 unsigned long step_size; 638 unsigned long addr; 639 unsigned long mapped_ram_size = 0; 640 641 /* xen has big range in reserved near end of ram, skip it at first.*/ 642 addr = memblock_find_in_range(map_start, map_end, PMD_SIZE, PMD_SIZE); 643 real_end = addr + PMD_SIZE; 644 645 /* step_size need to be small so pgt_buf from BRK could cover it */ 646 step_size = PMD_SIZE; 647 max_pfn_mapped = 0; /* will get exact value next */ 648 min_pfn_mapped = real_end >> PAGE_SHIFT; 649 last_start = start = real_end; 650 651 /* 652 * We start from the top (end of memory) and go to the bottom. 653 * The memblock_find_in_range() gets us a block of RAM from the 654 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages 655 * for page table. 656 */ 657 while (last_start > map_start) { 658 if (last_start > step_size) { 659 start = round_down(last_start - 1, step_size); 660 if (start < map_start) 661 start = map_start; 662 } else 663 start = map_start; 664 mapped_ram_size += init_range_memory_mapping(start, 665 last_start); 666 last_start = start; 667 min_pfn_mapped = last_start >> PAGE_SHIFT; 668 if (mapped_ram_size >= step_size) 669 step_size = get_new_step_size(step_size); 670 } 671 672 if (real_end < map_end) 673 init_range_memory_mapping(real_end, map_end); 674} 675 676/** 677 * memory_map_bottom_up - Map [map_start, map_end) bottom up 678 * @map_start: start address of the target memory range 679 * @map_end: end address of the target memory range 680 * 681 * This function will setup direct mapping for memory range 682 * [map_start, map_end) in bottom-up. Since we have limited the 683 * bottom-up allocation above the kernel, the page tables will 684 * be allocated just above the kernel and we map the memory 685 * in [map_start, map_end) in bottom-up. 686 */ 687static void __init memory_map_bottom_up(unsigned long map_start, 688 unsigned long map_end) 689{ 690 unsigned long next, start; 691 unsigned long mapped_ram_size = 0; 692 /* step_size need to be small so pgt_buf from BRK could cover it */ 693 unsigned long step_size = PMD_SIZE; 694 695 start = map_start; 696 min_pfn_mapped = start >> PAGE_SHIFT; 697 698 /* 699 * We start from the bottom (@map_start) and go to the top (@map_end). 700 * The memblock_find_in_range() gets us a block of RAM from the 701 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages 702 * for page table. 703 */ 704 while (start < map_end) { 705 if (step_size && map_end - start > step_size) { 706 next = round_up(start + 1, step_size); 707 if (next > map_end) 708 next = map_end; 709 } else { 710 next = map_end; 711 } 712 713 mapped_ram_size += init_range_memory_mapping(start, next); 714 start = next; 715 716 if (mapped_ram_size >= step_size) 717 step_size = get_new_step_size(step_size); 718 } 719} 720 721/* 722 * The real mode trampoline, which is required for bootstrapping CPUs 723 * occupies only a small area under the low 1MB. See reserve_real_mode() 724 * for details. 725 * 726 * If KASLR is disabled the first PGD entry of the direct mapping is copied 727 * to map the real mode trampoline. 728 * 729 * If KASLR is enabled, copy only the PUD which covers the low 1MB 730 * area. This limits the randomization granularity to 1GB for both 4-level 731 * and 5-level paging. 732 */ 733static void __init init_trampoline(void) 734{ 735#ifdef CONFIG_X86_64 736 if (!kaslr_memory_enabled()) 737 trampoline_pgd_entry = init_top_pgt[pgd_index(__PAGE_OFFSET)]; 738 else 739 init_trampoline_kaslr(); 740#endif 741} 742 743void __init init_mem_mapping(void) 744{ 745 unsigned long end; 746 747 pti_check_boottime_disable(); 748 probe_page_size_mask(); 749 setup_pcid(); 750 751#ifdef CONFIG_X86_64 752 end = max_pfn << PAGE_SHIFT; 753#else 754 end = max_low_pfn << PAGE_SHIFT; 755#endif 756 757 /* the ISA range is always mapped regardless of memory holes */ 758 init_memory_mapping(0, ISA_END_ADDRESS, PAGE_KERNEL); 759 760 /* Init the trampoline, possibly with KASLR memory offset */ 761 init_trampoline(); 762 763 /* 764 * If the allocation is in bottom-up direction, we setup direct mapping 765 * in bottom-up, otherwise we setup direct mapping in top-down. 766 */ 767 if (memblock_bottom_up()) { 768 unsigned long kernel_end = __pa_symbol(_end); 769 770 /* 771 * we need two separate calls here. This is because we want to 772 * allocate page tables above the kernel. So we first map 773 * [kernel_end, end) to make memory above the kernel be mapped 774 * as soon as possible. And then use page tables allocated above 775 * the kernel to map [ISA_END_ADDRESS, kernel_end). 776 */ 777 memory_map_bottom_up(kernel_end, end); 778 memory_map_bottom_up(ISA_END_ADDRESS, kernel_end); 779 } else { 780 memory_map_top_down(ISA_END_ADDRESS, end); 781 } 782 783#ifdef CONFIG_X86_64 784 if (max_pfn > max_low_pfn) { 785 /* can we preseve max_low_pfn ?*/ 786 max_low_pfn = max_pfn; 787 } 788#else 789 early_ioremap_page_table_range_init(); 790#endif 791 792 load_cr3(swapper_pg_dir); 793 __flush_tlb_all(); 794 795 x86_init.hyper.init_mem_mapping(); 796 797 early_memtest(0, max_pfn_mapped << PAGE_SHIFT); 798} 799 800/* 801 * Initialize an mm_struct to be used during poking and a pointer to be used 802 * during patching. 803 */ 804void __init poking_init(void) 805{ 806 spinlock_t *ptl; 807 pte_t *ptep; 808 809 poking_mm = mm_alloc(); 810 BUG_ON(!poking_mm); 811 812 /* Xen PV guests need the PGD to be pinned. */ 813 paravirt_arch_dup_mmap(NULL, poking_mm); 814 815 /* 816 * Randomize the poking address, but make sure that the following page 817 * will be mapped at the same PMD. We need 2 pages, so find space for 3, 818 * and adjust the address if the PMD ends after the first one. 819 */ 820 poking_addr = TASK_UNMAPPED_BASE; 821 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 822 poking_addr += (kaslr_get_random_long("Poking") & PAGE_MASK) % 823 (TASK_SIZE - TASK_UNMAPPED_BASE - 3 * PAGE_SIZE); 824 825 if (((poking_addr + PAGE_SIZE) & ~PMD_MASK) == 0) 826 poking_addr += PAGE_SIZE; 827 828 /* 829 * We need to trigger the allocation of the page-tables that will be 830 * needed for poking now. Later, poking may be performed in an atomic 831 * section, which might cause allocation to fail. 832 */ 833 ptep = get_locked_pte(poking_mm, poking_addr, &ptl); 834 BUG_ON(!ptep); 835 pte_unmap_unlock(ptep, ptl); 836} 837 838/* 839 * devmem_is_allowed() checks to see if /dev/mem access to a certain address 840 * is valid. The argument is a physical page number. 841 * 842 * On x86, access has to be given to the first megabyte of RAM because that 843 * area traditionally contains BIOS code and data regions used by X, dosemu, 844 * and similar apps. Since they map the entire memory range, the whole range 845 * must be allowed (for mapping), but any areas that would otherwise be 846 * disallowed are flagged as being "zero filled" instead of rejected. 847 * Access has to be given to non-kernel-ram areas as well, these contain the 848 * PCI mmio resources as well as potential bios/acpi data regions. 849 */ 850int devmem_is_allowed(unsigned long pagenr) 851{ 852 if (region_intersects(PFN_PHYS(pagenr), PAGE_SIZE, 853 IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE) 854 != REGION_DISJOINT) { 855 /* 856 * For disallowed memory regions in the low 1MB range, 857 * request that the page be shown as all zeros. 858 */ 859 if (pagenr < 256) 860 return 2; 861 862 return 0; 863 } 864 865 /* 866 * This must follow RAM test, since System RAM is considered a 867 * restricted resource under CONFIG_STRICT_IOMEM. 868 */ 869 if (iomem_is_exclusive(pagenr << PAGE_SHIFT)) { 870 /* Low 1MB bypasses iomem restrictions. */ 871 if (pagenr < 256) 872 return 1; 873 874 return 0; 875 } 876 877 return 1; 878} 879 880void free_init_pages(const char *what, unsigned long begin, unsigned long end) 881{ 882 unsigned long begin_aligned, end_aligned; 883 884 /* Make sure boundaries are page aligned */ 885 begin_aligned = PAGE_ALIGN(begin); 886 end_aligned = end & PAGE_MASK; 887 888 if (WARN_ON(begin_aligned != begin || end_aligned != end)) { 889 begin = begin_aligned; 890 end = end_aligned; 891 } 892 893 if (begin >= end) 894 return; 895 896 /* 897 * If debugging page accesses then do not free this memory but 898 * mark them not present - any buggy init-section access will 899 * create a kernel page fault: 900 */ 901 if (debug_pagealloc_enabled()) { 902 pr_info("debug: unmapping init [mem %#010lx-%#010lx]\n", 903 begin, end - 1); 904 /* 905 * Inform kmemleak about the hole in the memory since the 906 * corresponding pages will be unmapped. 907 */ 908 kmemleak_free_part((void *)begin, end - begin); 909 set_memory_np(begin, (end - begin) >> PAGE_SHIFT); 910 } else { 911 /* 912 * We just marked the kernel text read only above, now that 913 * we are going to free part of that, we need to make that 914 * writeable and non-executable first. 915 */ 916 set_memory_nx(begin, (end - begin) >> PAGE_SHIFT); 917 set_memory_rw(begin, (end - begin) >> PAGE_SHIFT); 918 919 free_reserved_area((void *)begin, (void *)end, 920 POISON_FREE_INITMEM, what); 921 } 922} 923 924/* 925 * begin/end can be in the direct map or the "high kernel mapping" 926 * used for the kernel image only. free_init_pages() will do the 927 * right thing for either kind of address. 928 */ 929void free_kernel_image_pages(const char *what, void *begin, void *end) 930{ 931 unsigned long begin_ul = (unsigned long)begin; 932 unsigned long end_ul = (unsigned long)end; 933 unsigned long len_pages = (end_ul - begin_ul) >> PAGE_SHIFT; 934 935 free_init_pages(what, begin_ul, end_ul); 936 937 /* 938 * PTI maps some of the kernel into userspace. For performance, 939 * this includes some kernel areas that do not contain secrets. 940 * Those areas might be adjacent to the parts of the kernel image 941 * being freed, which may contain secrets. Remove the "high kernel 942 * image mapping" for these freed areas, ensuring they are not even 943 * potentially vulnerable to Meltdown regardless of the specific 944 * optimizations PTI is currently using. 945 * 946 * The "noalias" prevents unmapping the direct map alias which is 947 * needed to access the freed pages. 948 * 949 * This is only valid for 64bit kernels. 32bit has only one mapping 950 * which can't be treated in this way for obvious reasons. 951 */ 952 if (IS_ENABLED(CONFIG_X86_64) && cpu_feature_enabled(X86_FEATURE_PTI)) 953 set_memory_np_noalias(begin_ul, len_pages); 954} 955 956void __ref free_initmem(void) 957{ 958 e820__reallocate_tables(); 959 960 mem_encrypt_free_decrypted_mem(); 961 962 free_kernel_image_pages("unused kernel image (initmem)", 963 &__init_begin, &__init_end); 964} 965 966#ifdef CONFIG_BLK_DEV_INITRD 967void __init free_initrd_mem(unsigned long start, unsigned long end) 968{ 969 /* 970 * end could be not aligned, and We can not align that, 971 * decompresser could be confused by aligned initrd_end 972 * We already reserve the end partial page before in 973 * - i386_start_kernel() 974 * - x86_64_start_kernel() 975 * - relocate_initrd() 976 * So here We can do PAGE_ALIGN() safely to get partial page to be freed 977 */ 978 free_init_pages("initrd", start, PAGE_ALIGN(end)); 979} 980#endif 981 982/* 983 * Calculate the precise size of the DMA zone (first 16 MB of RAM), 984 * and pass it to the MM layer - to help it set zone watermarks more 985 * accurately. 986 * 987 * Done on 64-bit systems only for the time being, although 32-bit systems 988 * might benefit from this as well. 989 */ 990void __init memblock_find_dma_reserve(void) 991{ 992#ifdef CONFIG_X86_64 993 u64 nr_pages = 0, nr_free_pages = 0; 994 unsigned long start_pfn, end_pfn; 995 phys_addr_t start_addr, end_addr; 996 int i; 997 u64 u; 998 999 /* 1000 * Iterate over all memory ranges (free and reserved ones alike), 1001 * to calculate the total number of pages in the first 16 MB of RAM: 1002 */ 1003 nr_pages = 0; 1004 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) { 1005 start_pfn = min(start_pfn, MAX_DMA_PFN); 1006 end_pfn = min(end_pfn, MAX_DMA_PFN); 1007 1008 nr_pages += end_pfn - start_pfn; 1009 } 1010 1011 /* 1012 * Iterate over free memory ranges to calculate the number of free 1013 * pages in the DMA zone, while not counting potential partial 1014 * pages at the beginning or the end of the range: 1015 */ 1016 nr_free_pages = 0; 1017 for_each_free_mem_range(u, NUMA_NO_NODE, MEMBLOCK_NONE, &start_addr, &end_addr, NULL) { 1018 start_pfn = min_t(unsigned long, PFN_UP(start_addr), MAX_DMA_PFN); 1019 end_pfn = min_t(unsigned long, PFN_DOWN(end_addr), MAX_DMA_PFN); 1020 1021 if (start_pfn < end_pfn) 1022 nr_free_pages += end_pfn - start_pfn; 1023 } 1024 1025 set_dma_reserve(nr_pages - nr_free_pages); 1026#endif 1027} 1028 1029void __init zone_sizes_init(void) 1030{ 1031 unsigned long max_zone_pfns[MAX_NR_ZONES]; 1032 1033 memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); 1034 1035#ifdef CONFIG_ZONE_DMA 1036 max_zone_pfns[ZONE_DMA] = min(MAX_DMA_PFN, max_low_pfn); 1037#endif 1038#ifdef CONFIG_ZONE_DMA32 1039 max_zone_pfns[ZONE_DMA32] = min(MAX_DMA32_PFN, max_low_pfn); 1040#endif 1041 max_zone_pfns[ZONE_NORMAL] = max_low_pfn; 1042#ifdef CONFIG_HIGHMEM 1043 max_zone_pfns[ZONE_HIGHMEM] = max_pfn; 1044#endif 1045 1046 free_area_init(max_zone_pfns); 1047} 1048 1049__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate) = { 1050 .loaded_mm = &init_mm, 1051 .next_asid = 1, 1052 .cr4 = ~0UL, /* fail hard if we screw up cr4 shadow initialization */ 1053}; 1054 1055void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache) 1056{ 1057 /* entry 0 MUST be WB (hardwired to speed up translations) */ 1058 BUG_ON(!entry && cache != _PAGE_CACHE_MODE_WB); 1059 1060 __cachemode2pte_tbl[cache] = __cm_idx2pte(entry); 1061 __pte2cachemode_tbl[entry] = cache; 1062} 1063 1064#ifdef CONFIG_SWAP 1065unsigned long max_swapfile_size(void) 1066{ 1067 unsigned long pages; 1068 1069 pages = generic_max_swapfile_size(); 1070 1071 if (boot_cpu_has_bug(X86_BUG_L1TF) && l1tf_mitigation != L1TF_MITIGATION_OFF) { 1072 /* Limit the swap file size to MAX_PA/2 for L1TF workaround */ 1073 unsigned long long l1tf_limit = l1tf_pfn_limit(); 1074 /* 1075 * We encode swap offsets also with 3 bits below those for pfn 1076 * which makes the usable limit higher. 1077 */ 1078#if CONFIG_PGTABLE_LEVELS > 2 1079 l1tf_limit <<= PAGE_SHIFT - SWP_OFFSET_FIRST_BIT; 1080#endif 1081 pages = min_t(unsigned long long, l1tf_limit, pages); 1082 } 1083 return pages; 1084} 1085#endif 1086