18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */
28c2ecf20Sopenharmony_ci/*---------------------------------------------------------------------------+
38c2ecf20Sopenharmony_ci |  control_w.h                                                              |
48c2ecf20Sopenharmony_ci |                                                                           |
58c2ecf20Sopenharmony_ci | Copyright (C) 1992,1993                                                   |
68c2ecf20Sopenharmony_ci |                       W. Metzenthen, 22 Parker St, Ormond, Vic 3163,      |
78c2ecf20Sopenharmony_ci |                       Australia.  E-mail   billm@vaxc.cc.monash.edu.au    |
88c2ecf20Sopenharmony_ci |                                                                           |
98c2ecf20Sopenharmony_ci +---------------------------------------------------------------------------*/
108c2ecf20Sopenharmony_ci
118c2ecf20Sopenharmony_ci#ifndef _CONTROLW_H_
128c2ecf20Sopenharmony_ci#define _CONTROLW_H_
138c2ecf20Sopenharmony_ci
148c2ecf20Sopenharmony_ci#ifdef __ASSEMBLY__
158c2ecf20Sopenharmony_ci#define	_Const_(x)	$##x
168c2ecf20Sopenharmony_ci#else
178c2ecf20Sopenharmony_ci#define	_Const_(x)	x
188c2ecf20Sopenharmony_ci#endif
198c2ecf20Sopenharmony_ci
208c2ecf20Sopenharmony_ci#define CW_RC		_Const_(0x0C00)	/* rounding control */
218c2ecf20Sopenharmony_ci#define CW_PC		_Const_(0x0300)	/* precision control */
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_ci#define CW_Precision	Const_(0x0020)	/* loss of precision mask */
248c2ecf20Sopenharmony_ci#define CW_Underflow	Const_(0x0010)	/* underflow mask */
258c2ecf20Sopenharmony_ci#define CW_Overflow	Const_(0x0008)	/* overflow mask */
268c2ecf20Sopenharmony_ci#define CW_ZeroDiv	Const_(0x0004)	/* divide by zero mask */
278c2ecf20Sopenharmony_ci#define CW_Denormal	Const_(0x0002)	/* denormalized operand mask */
288c2ecf20Sopenharmony_ci#define CW_Invalid	Const_(0x0001)	/* invalid operation mask */
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_ci#define CW_Exceptions  	_Const_(0x003f)	/* all masks */
318c2ecf20Sopenharmony_ci
328c2ecf20Sopenharmony_ci#define RC_RND		_Const_(0x0000)
338c2ecf20Sopenharmony_ci#define RC_DOWN		_Const_(0x0400)
348c2ecf20Sopenharmony_ci#define RC_UP		_Const_(0x0800)
358c2ecf20Sopenharmony_ci#define RC_CHOP		_Const_(0x0C00)
368c2ecf20Sopenharmony_ci
378c2ecf20Sopenharmony_ci/* p 15-5: Precision control bits affect only the following:
388c2ecf20Sopenharmony_ci   ADD, SUB(R), MUL, DIV(R), and SQRT */
398c2ecf20Sopenharmony_ci#define PR_24_BITS        _Const_(0x000)
408c2ecf20Sopenharmony_ci#define PR_53_BITS        _Const_(0x200)
418c2ecf20Sopenharmony_ci#define PR_64_BITS        _Const_(0x300)
428c2ecf20Sopenharmony_ci#define PR_RESERVED_BITS  _Const_(0x100)
438c2ecf20Sopenharmony_ci/* FULL_PRECISION simulates all exceptions masked */
448c2ecf20Sopenharmony_ci#define FULL_PRECISION  (PR_64_BITS | RC_RND | 0x3f)
458c2ecf20Sopenharmony_ci
468c2ecf20Sopenharmony_ci#endif /* _CONTROLW_H_ */
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