1// SPDX-License-Identifier: GPL-2.0-only 2/****************************************************************************** 3 * emulate.c 4 * 5 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. 6 * 7 * Copyright (c) 2005 Keir Fraser 8 * 9 * Linux coding style, mod r/m decoder, segment base fixes, real-mode 10 * privileged instructions: 11 * 12 * Copyright (C) 2006 Qumranet 13 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 14 * 15 * Avi Kivity <avi@qumranet.com> 16 * Yaniv Kamay <yaniv@qumranet.com> 17 * 18 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 19 */ 20 21#include <linux/kvm_host.h> 22#include "kvm_cache_regs.h" 23#include "kvm_emulate.h" 24#include <linux/stringify.h> 25#include <asm/fpu/api.h> 26#include <asm/debugreg.h> 27#include <asm/nospec-branch.h> 28 29#include "x86.h" 30#include "tss.h" 31#include "mmu.h" 32#include "pmu.h" 33 34/* 35 * Operand types 36 */ 37#define OpNone 0ull 38#define OpImplicit 1ull /* No generic decode */ 39#define OpReg 2ull /* Register */ 40#define OpMem 3ull /* Memory */ 41#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ 42#define OpDI 5ull /* ES:DI/EDI/RDI */ 43#define OpMem64 6ull /* Memory, 64-bit */ 44#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ 45#define OpDX 8ull /* DX register */ 46#define OpCL 9ull /* CL register (for shifts) */ 47#define OpImmByte 10ull /* 8-bit sign extended immediate */ 48#define OpOne 11ull /* Implied 1 */ 49#define OpImm 12ull /* Sign extended up to 32-bit immediate */ 50#define OpMem16 13ull /* Memory operand (16-bit). */ 51#define OpMem32 14ull /* Memory operand (32-bit). */ 52#define OpImmU 15ull /* Immediate operand, zero extended */ 53#define OpSI 16ull /* SI/ESI/RSI */ 54#define OpImmFAddr 17ull /* Immediate far address */ 55#define OpMemFAddr 18ull /* Far address in memory */ 56#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ 57#define OpES 20ull /* ES */ 58#define OpCS 21ull /* CS */ 59#define OpSS 22ull /* SS */ 60#define OpDS 23ull /* DS */ 61#define OpFS 24ull /* FS */ 62#define OpGS 25ull /* GS */ 63#define OpMem8 26ull /* 8-bit zero extended memory operand */ 64#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */ 65#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */ 66#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */ 67#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */ 68 69#define OpBits 5 /* Width of operand field */ 70#define OpMask ((1ull << OpBits) - 1) 71 72/* 73 * Opcode effective-address decode tables. 74 * Note that we only emulate instructions that have at least one memory 75 * operand (excluding implicit stack references). We assume that stack 76 * references and instruction fetches will never occur in special memory 77 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need 78 * not be handled. 79 */ 80 81/* Operand sizes: 8-bit operands or specified/overridden size. */ 82#define ByteOp (1<<0) /* 8-bit operands. */ 83/* Destination operand type. */ 84#define DstShift 1 85#define ImplicitOps (OpImplicit << DstShift) 86#define DstReg (OpReg << DstShift) 87#define DstMem (OpMem << DstShift) 88#define DstAcc (OpAcc << DstShift) 89#define DstDI (OpDI << DstShift) 90#define DstMem64 (OpMem64 << DstShift) 91#define DstMem16 (OpMem16 << DstShift) 92#define DstImmUByte (OpImmUByte << DstShift) 93#define DstDX (OpDX << DstShift) 94#define DstAccLo (OpAccLo << DstShift) 95#define DstMask (OpMask << DstShift) 96/* Source operand type. */ 97#define SrcShift 6 98#define SrcNone (OpNone << SrcShift) 99#define SrcReg (OpReg << SrcShift) 100#define SrcMem (OpMem << SrcShift) 101#define SrcMem16 (OpMem16 << SrcShift) 102#define SrcMem32 (OpMem32 << SrcShift) 103#define SrcImm (OpImm << SrcShift) 104#define SrcImmByte (OpImmByte << SrcShift) 105#define SrcOne (OpOne << SrcShift) 106#define SrcImmUByte (OpImmUByte << SrcShift) 107#define SrcImmU (OpImmU << SrcShift) 108#define SrcSI (OpSI << SrcShift) 109#define SrcXLat (OpXLat << SrcShift) 110#define SrcImmFAddr (OpImmFAddr << SrcShift) 111#define SrcMemFAddr (OpMemFAddr << SrcShift) 112#define SrcAcc (OpAcc << SrcShift) 113#define SrcImmU16 (OpImmU16 << SrcShift) 114#define SrcImm64 (OpImm64 << SrcShift) 115#define SrcDX (OpDX << SrcShift) 116#define SrcMem8 (OpMem8 << SrcShift) 117#define SrcAccHi (OpAccHi << SrcShift) 118#define SrcMask (OpMask << SrcShift) 119#define BitOp (1<<11) 120#define MemAbs (1<<12) /* Memory operand is absolute displacement */ 121#define String (1<<13) /* String instruction (rep capable) */ 122#define Stack (1<<14) /* Stack instruction (push/pop) */ 123#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ 124#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ 125#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ 126#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ 127#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ 128#define Escape (5<<15) /* Escape to coprocessor instruction */ 129#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */ 130#define ModeDual (7<<15) /* Different instruction for 32/64 bit */ 131#define Sse (1<<18) /* SSE Vector instruction */ 132/* Generic ModRM decode. */ 133#define ModRM (1<<19) 134/* Destination is only written; never read. */ 135#define Mov (1<<20) 136/* Misc flags */ 137#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ 138#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */ 139#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ 140#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ 141#define Undefined (1<<25) /* No Such Instruction */ 142#define Lock (1<<26) /* lock prefix is allowed for the instruction */ 143#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ 144#define No64 (1<<28) 145#define PageTable (1 << 29) /* instruction used to write page table */ 146#define NotImpl (1 << 30) /* instruction is not implemented */ 147/* Source 2 operand type */ 148#define Src2Shift (31) 149#define Src2None (OpNone << Src2Shift) 150#define Src2Mem (OpMem << Src2Shift) 151#define Src2CL (OpCL << Src2Shift) 152#define Src2ImmByte (OpImmByte << Src2Shift) 153#define Src2One (OpOne << Src2Shift) 154#define Src2Imm (OpImm << Src2Shift) 155#define Src2ES (OpES << Src2Shift) 156#define Src2CS (OpCS << Src2Shift) 157#define Src2SS (OpSS << Src2Shift) 158#define Src2DS (OpDS << Src2Shift) 159#define Src2FS (OpFS << Src2Shift) 160#define Src2GS (OpGS << Src2Shift) 161#define Src2Mask (OpMask << Src2Shift) 162#define Mmx ((u64)1 << 40) /* MMX Vector instruction */ 163#define AlignMask ((u64)7 << 41) 164#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ 165#define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) */ 166#define Avx ((u64)3 << 41) /* Advanced Vector Extensions */ 167#define Aligned16 ((u64)4 << 41) /* Aligned to 16 byte boundary (e.g. FXSAVE) */ 168#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */ 169#define NoWrite ((u64)1 << 45) /* No writeback */ 170#define SrcWrite ((u64)1 << 46) /* Write back src operand */ 171#define NoMod ((u64)1 << 47) /* Mod field is ignored */ 172#define Intercept ((u64)1 << 48) /* Has valid intercept field */ 173#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */ 174#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */ 175#define NearBranch ((u64)1 << 52) /* Near branches */ 176#define No16 ((u64)1 << 53) /* No 16 bit operand */ 177#define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */ 178#define TwoMemOp ((u64)1 << 55) /* Instruction has two memory operand */ 179 180#define DstXacc (DstAccLo | SrcAccHi | SrcWrite) 181 182#define X2(x...) x, x 183#define X3(x...) X2(x), x 184#define X4(x...) X2(x), X2(x) 185#define X5(x...) X4(x), x 186#define X6(x...) X4(x), X2(x) 187#define X7(x...) X4(x), X3(x) 188#define X8(x...) X4(x), X4(x) 189#define X16(x...) X8(x), X8(x) 190 191struct opcode { 192 u64 flags : 56; 193 u64 intercept : 8; 194 union { 195 int (*execute)(struct x86_emulate_ctxt *ctxt); 196 const struct opcode *group; 197 const struct group_dual *gdual; 198 const struct gprefix *gprefix; 199 const struct escape *esc; 200 const struct instr_dual *idual; 201 const struct mode_dual *mdual; 202 void (*fastop)(struct fastop *fake); 203 } u; 204 int (*check_perm)(struct x86_emulate_ctxt *ctxt); 205}; 206 207struct group_dual { 208 struct opcode mod012[8]; 209 struct opcode mod3[8]; 210}; 211 212struct gprefix { 213 struct opcode pfx_no; 214 struct opcode pfx_66; 215 struct opcode pfx_f2; 216 struct opcode pfx_f3; 217}; 218 219struct escape { 220 struct opcode op[8]; 221 struct opcode high[64]; 222}; 223 224struct instr_dual { 225 struct opcode mod012; 226 struct opcode mod3; 227}; 228 229struct mode_dual { 230 struct opcode mode32; 231 struct opcode mode64; 232}; 233 234#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a 235 236enum x86_transfer_type { 237 X86_TRANSFER_NONE, 238 X86_TRANSFER_CALL_JMP, 239 X86_TRANSFER_RET, 240 X86_TRANSFER_TASK_SWITCH, 241}; 242 243static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr) 244{ 245 if (!(ctxt->regs_valid & (1 << nr))) { 246 ctxt->regs_valid |= 1 << nr; 247 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr); 248 } 249 return ctxt->_regs[nr]; 250} 251 252static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr) 253{ 254 ctxt->regs_valid |= 1 << nr; 255 ctxt->regs_dirty |= 1 << nr; 256 return &ctxt->_regs[nr]; 257} 258 259static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr) 260{ 261 reg_read(ctxt, nr); 262 return reg_write(ctxt, nr); 263} 264 265static void writeback_registers(struct x86_emulate_ctxt *ctxt) 266{ 267 unsigned reg; 268 269 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16) 270 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]); 271} 272 273static void invalidate_registers(struct x86_emulate_ctxt *ctxt) 274{ 275 ctxt->regs_dirty = 0; 276 ctxt->regs_valid = 0; 277} 278 279/* 280 * These EFLAGS bits are restored from saved value during emulation, and 281 * any changes are written back to the saved value after emulation. 282 */ 283#define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\ 284 X86_EFLAGS_PF|X86_EFLAGS_CF) 285 286#ifdef CONFIG_X86_64 287#define ON64(x) x 288#else 289#define ON64(x) 290#endif 291 292/* 293 * fastop functions have a special calling convention: 294 * 295 * dst: rax (in/out) 296 * src: rdx (in/out) 297 * src2: rcx (in) 298 * flags: rflags (in/out) 299 * ex: rsi (in:fastop pointer, out:zero if exception) 300 * 301 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for 302 * different operand sizes can be reached by calculation, rather than a jump 303 * table (which would be bigger than the code). 304 * 305 * The 16 byte alignment, considering 5 bytes for the RET thunk, 3 for ENDBR 306 * and 1 for the straight line speculation INT3, leaves 7 bytes for the 307 * body of the function. Currently none is larger than 4. 308 */ 309static int fastop(struct x86_emulate_ctxt *ctxt, fastop_t fop); 310 311#define FASTOP_SIZE 16 312 313#define __FOP_FUNC(name) \ 314 ".align " __stringify(FASTOP_SIZE) " \n\t" \ 315 ".type " name ", @function \n\t" \ 316 name ":\n\t" 317 318#define FOP_FUNC(name) \ 319 __FOP_FUNC(#name) 320 321#define __FOP_RET(name) \ 322 ASM_RET \ 323 ".size " name ", .-" name "\n\t" 324 325#define FOP_RET(name) \ 326 __FOP_RET(#name) 327 328#define __FOP_START(op, align) \ 329 extern void em_##op(struct fastop *fake); \ 330 asm(".pushsection .text, \"ax\" \n\t" \ 331 ".global em_" #op " \n\t" \ 332 ".align " __stringify(align) " \n\t" \ 333 "em_" #op ":\n\t" 334 335#define FOP_START(op) __FOP_START(op, FASTOP_SIZE) 336 337#define FOP_END \ 338 ".popsection") 339 340#define __FOPNOP(name) \ 341 __FOP_FUNC(name) \ 342 __FOP_RET(name) 343 344#define FOPNOP() \ 345 __FOPNOP(__stringify(__UNIQUE_ID(nop))) 346 347#define FOP1E(op, dst) \ 348 __FOP_FUNC(#op "_" #dst) \ 349 "10: " #op " %" #dst " \n\t" \ 350 __FOP_RET(#op "_" #dst) 351 352#define FOP1EEX(op, dst) \ 353 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception) 354 355#define FASTOP1(op) \ 356 FOP_START(op) \ 357 FOP1E(op##b, al) \ 358 FOP1E(op##w, ax) \ 359 FOP1E(op##l, eax) \ 360 ON64(FOP1E(op##q, rax)) \ 361 FOP_END 362 363/* 1-operand, using src2 (for MUL/DIV r/m) */ 364#define FASTOP1SRC2(op, name) \ 365 FOP_START(name) \ 366 FOP1E(op, cl) \ 367 FOP1E(op, cx) \ 368 FOP1E(op, ecx) \ 369 ON64(FOP1E(op, rcx)) \ 370 FOP_END 371 372/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */ 373#define FASTOP1SRC2EX(op, name) \ 374 FOP_START(name) \ 375 FOP1EEX(op, cl) \ 376 FOP1EEX(op, cx) \ 377 FOP1EEX(op, ecx) \ 378 ON64(FOP1EEX(op, rcx)) \ 379 FOP_END 380 381#define FOP2E(op, dst, src) \ 382 __FOP_FUNC(#op "_" #dst "_" #src) \ 383 #op " %" #src ", %" #dst " \n\t" \ 384 __FOP_RET(#op "_" #dst "_" #src) 385 386#define FASTOP2(op) \ 387 FOP_START(op) \ 388 FOP2E(op##b, al, dl) \ 389 FOP2E(op##w, ax, dx) \ 390 FOP2E(op##l, eax, edx) \ 391 ON64(FOP2E(op##q, rax, rdx)) \ 392 FOP_END 393 394/* 2 operand, word only */ 395#define FASTOP2W(op) \ 396 FOP_START(op) \ 397 FOPNOP() \ 398 FOP2E(op##w, ax, dx) \ 399 FOP2E(op##l, eax, edx) \ 400 ON64(FOP2E(op##q, rax, rdx)) \ 401 FOP_END 402 403/* 2 operand, src is CL */ 404#define FASTOP2CL(op) \ 405 FOP_START(op) \ 406 FOP2E(op##b, al, cl) \ 407 FOP2E(op##w, ax, cl) \ 408 FOP2E(op##l, eax, cl) \ 409 ON64(FOP2E(op##q, rax, cl)) \ 410 FOP_END 411 412/* 2 operand, src and dest are reversed */ 413#define FASTOP2R(op, name) \ 414 FOP_START(name) \ 415 FOP2E(op##b, dl, al) \ 416 FOP2E(op##w, dx, ax) \ 417 FOP2E(op##l, edx, eax) \ 418 ON64(FOP2E(op##q, rdx, rax)) \ 419 FOP_END 420 421#define FOP3E(op, dst, src, src2) \ 422 __FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \ 423 #op " %" #src2 ", %" #src ", %" #dst " \n\t"\ 424 __FOP_RET(#op "_" #dst "_" #src "_" #src2) 425 426/* 3-operand, word-only, src2=cl */ 427#define FASTOP3WCL(op) \ 428 FOP_START(op) \ 429 FOPNOP() \ 430 FOP3E(op##w, ax, dx, cl) \ 431 FOP3E(op##l, eax, edx, cl) \ 432 ON64(FOP3E(op##q, rax, rdx, cl)) \ 433 FOP_END 434 435/* Special case for SETcc - 1 instruction per cc */ 436 437/* 438 * Depending on .config the SETcc functions look like: 439 * 440 * SETcc %al [3 bytes] 441 * RET | JMP __x86_return_thunk [1,5 bytes; CONFIG_RETHUNK] 442 * INT3 [1 byte; CONFIG_SLS] 443 */ 444#define SETCC_ALIGN 16 445 446#define FOP_SETCC(op) \ 447 ".align " __stringify(SETCC_ALIGN) " \n\t" \ 448 ".type " #op ", @function \n\t" \ 449 #op ": \n\t" \ 450 #op " %al \n\t" \ 451 __FOP_RET(#op) \ 452 ".skip " __stringify(SETCC_ALIGN) " - (.-" #op "), 0xcc \n\t" 453 454asm(".pushsection .fixup, \"ax\"\n" 455 "kvm_fastop_exception: xor %esi, %esi; " ASM_RET 456 ".popsection"); 457 458__FOP_START(setcc, SETCC_ALIGN) 459FOP_SETCC(seto) 460FOP_SETCC(setno) 461FOP_SETCC(setc) 462FOP_SETCC(setnc) 463FOP_SETCC(setz) 464FOP_SETCC(setnz) 465FOP_SETCC(setbe) 466FOP_SETCC(setnbe) 467FOP_SETCC(sets) 468FOP_SETCC(setns) 469FOP_SETCC(setp) 470FOP_SETCC(setnp) 471FOP_SETCC(setl) 472FOP_SETCC(setnl) 473FOP_SETCC(setle) 474FOP_SETCC(setnle) 475FOP_END; 476 477FOP_START(salc) 478FOP_FUNC(salc) 479"pushf; sbb %al, %al; popf \n\t" 480FOP_RET(salc) 481FOP_END; 482 483/* 484 * XXX: inoutclob user must know where the argument is being expanded. 485 * Relying on CONFIG_CC_HAS_ASM_GOTO would allow us to remove _fault. 486 */ 487#define asm_safe(insn, inoutclob...) \ 488({ \ 489 int _fault = 0; \ 490 \ 491 asm volatile("1:" insn "\n" \ 492 "2:\n" \ 493 ".pushsection .fixup, \"ax\"\n" \ 494 "3: movl $1, %[_fault]\n" \ 495 " jmp 2b\n" \ 496 ".popsection\n" \ 497 _ASM_EXTABLE(1b, 3b) \ 498 : [_fault] "+qm"(_fault) inoutclob ); \ 499 \ 500 _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \ 501}) 502 503static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, 504 enum x86_intercept intercept, 505 enum x86_intercept_stage stage) 506{ 507 struct x86_instruction_info info = { 508 .intercept = intercept, 509 .rep_prefix = ctxt->rep_prefix, 510 .modrm_mod = ctxt->modrm_mod, 511 .modrm_reg = ctxt->modrm_reg, 512 .modrm_rm = ctxt->modrm_rm, 513 .src_val = ctxt->src.val64, 514 .dst_val = ctxt->dst.val64, 515 .src_bytes = ctxt->src.bytes, 516 .dst_bytes = ctxt->dst.bytes, 517 .ad_bytes = ctxt->ad_bytes, 518 .next_rip = ctxt->eip, 519 }; 520 521 return ctxt->ops->intercept(ctxt, &info, stage); 522} 523 524static void assign_masked(ulong *dest, ulong src, ulong mask) 525{ 526 *dest = (*dest & ~mask) | (src & mask); 527} 528 529static void assign_register(unsigned long *reg, u64 val, int bytes) 530{ 531 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ 532 switch (bytes) { 533 case 1: 534 *(u8 *)reg = (u8)val; 535 break; 536 case 2: 537 *(u16 *)reg = (u16)val; 538 break; 539 case 4: 540 *reg = (u32)val; 541 break; /* 64b: zero-extend */ 542 case 8: 543 *reg = val; 544 break; 545 } 546} 547 548static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) 549{ 550 return (1UL << (ctxt->ad_bytes << 3)) - 1; 551} 552 553static ulong stack_mask(struct x86_emulate_ctxt *ctxt) 554{ 555 u16 sel; 556 struct desc_struct ss; 557 558 if (ctxt->mode == X86EMUL_MODE_PROT64) 559 return ~0UL; 560 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS); 561 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */ 562} 563 564static int stack_size(struct x86_emulate_ctxt *ctxt) 565{ 566 return (__fls(stack_mask(ctxt)) + 1) >> 3; 567} 568 569/* Access/update address held in a register, based on addressing mode. */ 570static inline unsigned long 571address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) 572{ 573 if (ctxt->ad_bytes == sizeof(unsigned long)) 574 return reg; 575 else 576 return reg & ad_mask(ctxt); 577} 578 579static inline unsigned long 580register_address(struct x86_emulate_ctxt *ctxt, int reg) 581{ 582 return address_mask(ctxt, reg_read(ctxt, reg)); 583} 584 585static void masked_increment(ulong *reg, ulong mask, int inc) 586{ 587 assign_masked(reg, *reg + inc, mask); 588} 589 590static inline void 591register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc) 592{ 593 ulong *preg = reg_rmw(ctxt, reg); 594 595 assign_register(preg, *preg + inc, ctxt->ad_bytes); 596} 597 598static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc) 599{ 600 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc); 601} 602 603static u32 desc_limit_scaled(struct desc_struct *desc) 604{ 605 u32 limit = get_desc_limit(desc); 606 607 return desc->g ? (limit << 12) | 0xfff : limit; 608} 609 610static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) 611{ 612 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) 613 return 0; 614 615 return ctxt->ops->get_cached_segment_base(ctxt, seg); 616} 617 618static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, 619 u32 error, bool valid) 620{ 621 WARN_ON(vec > 0x1f); 622 ctxt->exception.vector = vec; 623 ctxt->exception.error_code = error; 624 ctxt->exception.error_code_valid = valid; 625 return X86EMUL_PROPAGATE_FAULT; 626} 627 628static int emulate_db(struct x86_emulate_ctxt *ctxt) 629{ 630 return emulate_exception(ctxt, DB_VECTOR, 0, false); 631} 632 633static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) 634{ 635 return emulate_exception(ctxt, GP_VECTOR, err, true); 636} 637 638static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) 639{ 640 return emulate_exception(ctxt, SS_VECTOR, err, true); 641} 642 643static int emulate_ud(struct x86_emulate_ctxt *ctxt) 644{ 645 return emulate_exception(ctxt, UD_VECTOR, 0, false); 646} 647 648static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) 649{ 650 return emulate_exception(ctxt, TS_VECTOR, err, true); 651} 652 653static int emulate_de(struct x86_emulate_ctxt *ctxt) 654{ 655 return emulate_exception(ctxt, DE_VECTOR, 0, false); 656} 657 658static int emulate_nm(struct x86_emulate_ctxt *ctxt) 659{ 660 return emulate_exception(ctxt, NM_VECTOR, 0, false); 661} 662 663static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) 664{ 665 u16 selector; 666 struct desc_struct desc; 667 668 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); 669 return selector; 670} 671 672static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, 673 unsigned seg) 674{ 675 u16 dummy; 676 u32 base3; 677 struct desc_struct desc; 678 679 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); 680 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); 681} 682 683static inline u8 ctxt_virt_addr_bits(struct x86_emulate_ctxt *ctxt) 684{ 685 return (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_LA57) ? 57 : 48; 686} 687 688static inline bool emul_is_noncanonical_address(u64 la, 689 struct x86_emulate_ctxt *ctxt) 690{ 691 return !__is_canonical_address(la, ctxt_virt_addr_bits(ctxt)); 692} 693 694/* 695 * x86 defines three classes of vector instructions: explicitly 696 * aligned, explicitly unaligned, and the rest, which change behaviour 697 * depending on whether they're AVX encoded or not. 698 * 699 * Also included is CMPXCHG16B which is not a vector instruction, yet it is 700 * subject to the same check. FXSAVE and FXRSTOR are checked here too as their 701 * 512 bytes of data must be aligned to a 16 byte boundary. 702 */ 703static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size) 704{ 705 u64 alignment = ctxt->d & AlignMask; 706 707 if (likely(size < 16)) 708 return 1; 709 710 switch (alignment) { 711 case Unaligned: 712 case Avx: 713 return 1; 714 case Aligned16: 715 return 16; 716 case Aligned: 717 default: 718 return size; 719 } 720} 721 722static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt, 723 struct segmented_address addr, 724 unsigned *max_size, unsigned size, 725 bool write, bool fetch, 726 enum x86emul_mode mode, ulong *linear) 727{ 728 struct desc_struct desc; 729 bool usable; 730 ulong la; 731 u32 lim; 732 u16 sel; 733 u8 va_bits; 734 735 la = seg_base(ctxt, addr.seg) + addr.ea; 736 *max_size = 0; 737 switch (mode) { 738 case X86EMUL_MODE_PROT64: 739 *linear = la; 740 va_bits = ctxt_virt_addr_bits(ctxt); 741 if (!__is_canonical_address(la, va_bits)) 742 goto bad; 743 744 *max_size = min_t(u64, ~0u, (1ull << va_bits) - la); 745 if (size > *max_size) 746 goto bad; 747 break; 748 default: 749 *linear = la = (u32)la; 750 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, 751 addr.seg); 752 if (!usable) 753 goto bad; 754 /* code segment in protected mode or read-only data segment */ 755 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8)) 756 || !(desc.type & 2)) && write) 757 goto bad; 758 /* unreadable code segment */ 759 if (!fetch && (desc.type & 8) && !(desc.type & 2)) 760 goto bad; 761 lim = desc_limit_scaled(&desc); 762 if (!(desc.type & 8) && (desc.type & 4)) { 763 /* expand-down segment */ 764 if (addr.ea <= lim) 765 goto bad; 766 lim = desc.d ? 0xffffffff : 0xffff; 767 } 768 if (addr.ea > lim) 769 goto bad; 770 if (lim == 0xffffffff) 771 *max_size = ~0u; 772 else { 773 *max_size = (u64)lim + 1 - addr.ea; 774 if (size > *max_size) 775 goto bad; 776 } 777 break; 778 } 779 if (la & (insn_alignment(ctxt, size) - 1)) 780 return emulate_gp(ctxt, 0); 781 return X86EMUL_CONTINUE; 782bad: 783 if (addr.seg == VCPU_SREG_SS) 784 return emulate_ss(ctxt, 0); 785 else 786 return emulate_gp(ctxt, 0); 787} 788 789static int linearize(struct x86_emulate_ctxt *ctxt, 790 struct segmented_address addr, 791 unsigned size, bool write, 792 ulong *linear) 793{ 794 unsigned max_size; 795 return __linearize(ctxt, addr, &max_size, size, write, false, 796 ctxt->mode, linear); 797} 798 799static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst) 800{ 801 ulong linear; 802 int rc; 803 unsigned max_size; 804 struct segmented_address addr = { .seg = VCPU_SREG_CS, 805 .ea = dst }; 806 807 if (ctxt->op_bytes != sizeof(unsigned long)) 808 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1); 809 rc = __linearize(ctxt, addr, &max_size, 1, false, true, ctxt->mode, &linear); 810 if (rc == X86EMUL_CONTINUE) 811 ctxt->_eip = addr.ea; 812 return rc; 813} 814 815static inline int emulator_recalc_and_set_mode(struct x86_emulate_ctxt *ctxt) 816{ 817 u64 efer; 818 struct desc_struct cs; 819 u16 selector; 820 u32 base3; 821 822 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 823 824 if (!(ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PE)) { 825 /* Real mode. cpu must not have long mode active */ 826 if (efer & EFER_LMA) 827 return X86EMUL_UNHANDLEABLE; 828 ctxt->mode = X86EMUL_MODE_REAL; 829 return X86EMUL_CONTINUE; 830 } 831 832 if (ctxt->eflags & X86_EFLAGS_VM) { 833 /* Protected/VM86 mode. cpu must not have long mode active */ 834 if (efer & EFER_LMA) 835 return X86EMUL_UNHANDLEABLE; 836 ctxt->mode = X86EMUL_MODE_VM86; 837 return X86EMUL_CONTINUE; 838 } 839 840 if (!ctxt->ops->get_segment(ctxt, &selector, &cs, &base3, VCPU_SREG_CS)) 841 return X86EMUL_UNHANDLEABLE; 842 843 if (efer & EFER_LMA) { 844 if (cs.l) { 845 /* Proper long mode */ 846 ctxt->mode = X86EMUL_MODE_PROT64; 847 } else if (cs.d) { 848 /* 32 bit compatibility mode*/ 849 ctxt->mode = X86EMUL_MODE_PROT32; 850 } else { 851 ctxt->mode = X86EMUL_MODE_PROT16; 852 } 853 } else { 854 /* Legacy 32 bit / 16 bit mode */ 855 ctxt->mode = cs.d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; 856 } 857 858 return X86EMUL_CONTINUE; 859} 860 861static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst) 862{ 863 return assign_eip(ctxt, dst); 864} 865 866static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst) 867{ 868 int rc = emulator_recalc_and_set_mode(ctxt); 869 870 if (rc != X86EMUL_CONTINUE) 871 return rc; 872 873 return assign_eip(ctxt, dst); 874} 875 876static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) 877{ 878 return assign_eip_near(ctxt, ctxt->_eip + rel); 879} 880 881static int linear_read_system(struct x86_emulate_ctxt *ctxt, ulong linear, 882 void *data, unsigned size) 883{ 884 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, true); 885} 886 887static int linear_write_system(struct x86_emulate_ctxt *ctxt, 888 ulong linear, void *data, 889 unsigned int size) 890{ 891 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, true); 892} 893 894static int segmented_read_std(struct x86_emulate_ctxt *ctxt, 895 struct segmented_address addr, 896 void *data, 897 unsigned size) 898{ 899 int rc; 900 ulong linear; 901 902 rc = linearize(ctxt, addr, size, false, &linear); 903 if (rc != X86EMUL_CONTINUE) 904 return rc; 905 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, false); 906} 907 908static int segmented_write_std(struct x86_emulate_ctxt *ctxt, 909 struct segmented_address addr, 910 void *data, 911 unsigned int size) 912{ 913 int rc; 914 ulong linear; 915 916 rc = linearize(ctxt, addr, size, true, &linear); 917 if (rc != X86EMUL_CONTINUE) 918 return rc; 919 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, false); 920} 921 922/* 923 * Prefetch the remaining bytes of the instruction without crossing page 924 * boundary if they are not in fetch_cache yet. 925 */ 926static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size) 927{ 928 int rc; 929 unsigned size, max_size; 930 unsigned long linear; 931 int cur_size = ctxt->fetch.end - ctxt->fetch.data; 932 struct segmented_address addr = { .seg = VCPU_SREG_CS, 933 .ea = ctxt->eip + cur_size }; 934 935 /* 936 * We do not know exactly how many bytes will be needed, and 937 * __linearize is expensive, so fetch as much as possible. We 938 * just have to avoid going beyond the 15 byte limit, the end 939 * of the segment, or the end of the page. 940 * 941 * __linearize is called with size 0 so that it does not do any 942 * boundary check itself. Instead, we use max_size to check 943 * against op_size. 944 */ 945 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode, 946 &linear); 947 if (unlikely(rc != X86EMUL_CONTINUE)) 948 return rc; 949 950 size = min_t(unsigned, 15UL ^ cur_size, max_size); 951 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear)); 952 953 /* 954 * One instruction can only straddle two pages, 955 * and one has been loaded at the beginning of 956 * x86_decode_insn. So, if not enough bytes 957 * still, we must have hit the 15-byte boundary. 958 */ 959 if (unlikely(size < op_size)) 960 return emulate_gp(ctxt, 0); 961 962 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end, 963 size, &ctxt->exception); 964 if (unlikely(rc != X86EMUL_CONTINUE)) 965 return rc; 966 ctxt->fetch.end += size; 967 return X86EMUL_CONTINUE; 968} 969 970static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, 971 unsigned size) 972{ 973 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr; 974 975 if (unlikely(done_size < size)) 976 return __do_insn_fetch_bytes(ctxt, size - done_size); 977 else 978 return X86EMUL_CONTINUE; 979} 980 981/* Fetch next part of the instruction being emulated. */ 982#define insn_fetch(_type, _ctxt) \ 983({ _type _x; \ 984 \ 985 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \ 986 if (rc != X86EMUL_CONTINUE) \ 987 goto done; \ 988 ctxt->_eip += sizeof(_type); \ 989 memcpy(&_x, ctxt->fetch.ptr, sizeof(_type)); \ 990 ctxt->fetch.ptr += sizeof(_type); \ 991 _x; \ 992}) 993 994#define insn_fetch_arr(_arr, _size, _ctxt) \ 995({ \ 996 rc = do_insn_fetch_bytes(_ctxt, _size); \ 997 if (rc != X86EMUL_CONTINUE) \ 998 goto done; \ 999 ctxt->_eip += (_size); \ 1000 memcpy(_arr, ctxt->fetch.ptr, _size); \ 1001 ctxt->fetch.ptr += (_size); \ 1002}) 1003 1004/* 1005 * Given the 'reg' portion of a ModRM byte, and a register block, return a 1006 * pointer into the block that addresses the relevant register. 1007 * @highbyte_regs specifies whether to decode AH,CH,DH,BH. 1008 */ 1009static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg, 1010 int byteop) 1011{ 1012 void *p; 1013 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop; 1014 1015 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) 1016 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1; 1017 else 1018 p = reg_rmw(ctxt, modrm_reg); 1019 return p; 1020} 1021 1022static int read_descriptor(struct x86_emulate_ctxt *ctxt, 1023 struct segmented_address addr, 1024 u16 *size, unsigned long *address, int op_bytes) 1025{ 1026 int rc; 1027 1028 if (op_bytes == 2) 1029 op_bytes = 3; 1030 *address = 0; 1031 rc = segmented_read_std(ctxt, addr, size, 2); 1032 if (rc != X86EMUL_CONTINUE) 1033 return rc; 1034 addr.ea += 2; 1035 rc = segmented_read_std(ctxt, addr, address, op_bytes); 1036 return rc; 1037} 1038 1039FASTOP2(add); 1040FASTOP2(or); 1041FASTOP2(adc); 1042FASTOP2(sbb); 1043FASTOP2(and); 1044FASTOP2(sub); 1045FASTOP2(xor); 1046FASTOP2(cmp); 1047FASTOP2(test); 1048 1049FASTOP1SRC2(mul, mul_ex); 1050FASTOP1SRC2(imul, imul_ex); 1051FASTOP1SRC2EX(div, div_ex); 1052FASTOP1SRC2EX(idiv, idiv_ex); 1053 1054FASTOP3WCL(shld); 1055FASTOP3WCL(shrd); 1056 1057FASTOP2W(imul); 1058 1059FASTOP1(not); 1060FASTOP1(neg); 1061FASTOP1(inc); 1062FASTOP1(dec); 1063 1064FASTOP2CL(rol); 1065FASTOP2CL(ror); 1066FASTOP2CL(rcl); 1067FASTOP2CL(rcr); 1068FASTOP2CL(shl); 1069FASTOP2CL(shr); 1070FASTOP2CL(sar); 1071 1072FASTOP2W(bsf); 1073FASTOP2W(bsr); 1074FASTOP2W(bt); 1075FASTOP2W(bts); 1076FASTOP2W(btr); 1077FASTOP2W(btc); 1078 1079FASTOP2(xadd); 1080 1081FASTOP2R(cmp, cmp_r); 1082 1083static int em_bsf_c(struct x86_emulate_ctxt *ctxt) 1084{ 1085 /* If src is zero, do not writeback, but update flags */ 1086 if (ctxt->src.val == 0) 1087 ctxt->dst.type = OP_NONE; 1088 return fastop(ctxt, em_bsf); 1089} 1090 1091static int em_bsr_c(struct x86_emulate_ctxt *ctxt) 1092{ 1093 /* If src is zero, do not writeback, but update flags */ 1094 if (ctxt->src.val == 0) 1095 ctxt->dst.type = OP_NONE; 1096 return fastop(ctxt, em_bsr); 1097} 1098 1099static __always_inline u8 test_cc(unsigned int condition, unsigned long flags) 1100{ 1101 u8 rc; 1102 void (*fop)(void) = (void *)em_setcc + SETCC_ALIGN * (condition & 0xf); 1103 1104 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF; 1105 asm("push %[flags]; popf; " CALL_NOSPEC 1106 : "=a"(rc) : [thunk_target]"r"(fop), [flags]"r"(flags)); 1107 return rc; 1108} 1109 1110static void fetch_register_operand(struct operand *op) 1111{ 1112 switch (op->bytes) { 1113 case 1: 1114 op->val = *(u8 *)op->addr.reg; 1115 break; 1116 case 2: 1117 op->val = *(u16 *)op->addr.reg; 1118 break; 1119 case 4: 1120 op->val = *(u32 *)op->addr.reg; 1121 break; 1122 case 8: 1123 op->val = *(u64 *)op->addr.reg; 1124 break; 1125 } 1126} 1127 1128static void emulator_get_fpu(void) 1129{ 1130 fpregs_lock(); 1131 1132 fpregs_assert_state_consistent(); 1133 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 1134 switch_fpu_return(); 1135} 1136 1137static void emulator_put_fpu(void) 1138{ 1139 fpregs_unlock(); 1140} 1141 1142static void read_sse_reg(sse128_t *data, int reg) 1143{ 1144 emulator_get_fpu(); 1145 switch (reg) { 1146 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break; 1147 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break; 1148 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break; 1149 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break; 1150 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break; 1151 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break; 1152 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break; 1153 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break; 1154#ifdef CONFIG_X86_64 1155 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break; 1156 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break; 1157 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break; 1158 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break; 1159 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break; 1160 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break; 1161 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break; 1162 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break; 1163#endif 1164 default: BUG(); 1165 } 1166 emulator_put_fpu(); 1167} 1168 1169static void write_sse_reg(sse128_t *data, int reg) 1170{ 1171 emulator_get_fpu(); 1172 switch (reg) { 1173 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break; 1174 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break; 1175 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break; 1176 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break; 1177 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break; 1178 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break; 1179 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break; 1180 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break; 1181#ifdef CONFIG_X86_64 1182 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break; 1183 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break; 1184 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break; 1185 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break; 1186 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break; 1187 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break; 1188 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break; 1189 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break; 1190#endif 1191 default: BUG(); 1192 } 1193 emulator_put_fpu(); 1194} 1195 1196static void read_mmx_reg(u64 *data, int reg) 1197{ 1198 emulator_get_fpu(); 1199 switch (reg) { 1200 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break; 1201 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break; 1202 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break; 1203 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break; 1204 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break; 1205 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break; 1206 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break; 1207 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break; 1208 default: BUG(); 1209 } 1210 emulator_put_fpu(); 1211} 1212 1213static void write_mmx_reg(u64 *data, int reg) 1214{ 1215 emulator_get_fpu(); 1216 switch (reg) { 1217 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break; 1218 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break; 1219 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break; 1220 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break; 1221 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break; 1222 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break; 1223 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break; 1224 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break; 1225 default: BUG(); 1226 } 1227 emulator_put_fpu(); 1228} 1229 1230static int em_fninit(struct x86_emulate_ctxt *ctxt) 1231{ 1232 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1233 return emulate_nm(ctxt); 1234 1235 emulator_get_fpu(); 1236 asm volatile("fninit"); 1237 emulator_put_fpu(); 1238 return X86EMUL_CONTINUE; 1239} 1240 1241static int em_fnstcw(struct x86_emulate_ctxt *ctxt) 1242{ 1243 u16 fcw; 1244 1245 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1246 return emulate_nm(ctxt); 1247 1248 emulator_get_fpu(); 1249 asm volatile("fnstcw %0": "+m"(fcw)); 1250 emulator_put_fpu(); 1251 1252 ctxt->dst.val = fcw; 1253 1254 return X86EMUL_CONTINUE; 1255} 1256 1257static int em_fnstsw(struct x86_emulate_ctxt *ctxt) 1258{ 1259 u16 fsw; 1260 1261 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1262 return emulate_nm(ctxt); 1263 1264 emulator_get_fpu(); 1265 asm volatile("fnstsw %0": "+m"(fsw)); 1266 emulator_put_fpu(); 1267 1268 ctxt->dst.val = fsw; 1269 1270 return X86EMUL_CONTINUE; 1271} 1272 1273static void decode_register_operand(struct x86_emulate_ctxt *ctxt, 1274 struct operand *op) 1275{ 1276 unsigned reg = ctxt->modrm_reg; 1277 1278 if (!(ctxt->d & ModRM)) 1279 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); 1280 1281 if (ctxt->d & Sse) { 1282 op->type = OP_XMM; 1283 op->bytes = 16; 1284 op->addr.xmm = reg; 1285 read_sse_reg(&op->vec_val, reg); 1286 return; 1287 } 1288 if (ctxt->d & Mmx) { 1289 reg &= 7; 1290 op->type = OP_MM; 1291 op->bytes = 8; 1292 op->addr.mm = reg; 1293 return; 1294 } 1295 1296 op->type = OP_REG; 1297 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1298 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp); 1299 1300 fetch_register_operand(op); 1301 op->orig_val = op->val; 1302} 1303 1304static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) 1305{ 1306 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP) 1307 ctxt->modrm_seg = VCPU_SREG_SS; 1308} 1309 1310static int decode_modrm(struct x86_emulate_ctxt *ctxt, 1311 struct operand *op) 1312{ 1313 u8 sib; 1314 int index_reg, base_reg, scale; 1315 int rc = X86EMUL_CONTINUE; 1316 ulong modrm_ea = 0; 1317 1318 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */ 1319 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */ 1320 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */ 1321 1322 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6; 1323 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; 1324 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07); 1325 ctxt->modrm_seg = VCPU_SREG_DS; 1326 1327 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) { 1328 op->type = OP_REG; 1329 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1330 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1331 ctxt->d & ByteOp); 1332 if (ctxt->d & Sse) { 1333 op->type = OP_XMM; 1334 op->bytes = 16; 1335 op->addr.xmm = ctxt->modrm_rm; 1336 read_sse_reg(&op->vec_val, ctxt->modrm_rm); 1337 return rc; 1338 } 1339 if (ctxt->d & Mmx) { 1340 op->type = OP_MM; 1341 op->bytes = 8; 1342 op->addr.mm = ctxt->modrm_rm & 7; 1343 return rc; 1344 } 1345 fetch_register_operand(op); 1346 return rc; 1347 } 1348 1349 op->type = OP_MEM; 1350 1351 if (ctxt->ad_bytes == 2) { 1352 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX); 1353 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP); 1354 unsigned si = reg_read(ctxt, VCPU_REGS_RSI); 1355 unsigned di = reg_read(ctxt, VCPU_REGS_RDI); 1356 1357 /* 16-bit ModR/M decode. */ 1358 switch (ctxt->modrm_mod) { 1359 case 0: 1360 if (ctxt->modrm_rm == 6) 1361 modrm_ea += insn_fetch(u16, ctxt); 1362 break; 1363 case 1: 1364 modrm_ea += insn_fetch(s8, ctxt); 1365 break; 1366 case 2: 1367 modrm_ea += insn_fetch(u16, ctxt); 1368 break; 1369 } 1370 switch (ctxt->modrm_rm) { 1371 case 0: 1372 modrm_ea += bx + si; 1373 break; 1374 case 1: 1375 modrm_ea += bx + di; 1376 break; 1377 case 2: 1378 modrm_ea += bp + si; 1379 break; 1380 case 3: 1381 modrm_ea += bp + di; 1382 break; 1383 case 4: 1384 modrm_ea += si; 1385 break; 1386 case 5: 1387 modrm_ea += di; 1388 break; 1389 case 6: 1390 if (ctxt->modrm_mod != 0) 1391 modrm_ea += bp; 1392 break; 1393 case 7: 1394 modrm_ea += bx; 1395 break; 1396 } 1397 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || 1398 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) 1399 ctxt->modrm_seg = VCPU_SREG_SS; 1400 modrm_ea = (u16)modrm_ea; 1401 } else { 1402 /* 32/64-bit ModR/M decode. */ 1403 if ((ctxt->modrm_rm & 7) == 4) { 1404 sib = insn_fetch(u8, ctxt); 1405 index_reg |= (sib >> 3) & 7; 1406 base_reg |= sib & 7; 1407 scale = sib >> 6; 1408 1409 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) 1410 modrm_ea += insn_fetch(s32, ctxt); 1411 else { 1412 modrm_ea += reg_read(ctxt, base_reg); 1413 adjust_modrm_seg(ctxt, base_reg); 1414 /* Increment ESP on POP [ESP] */ 1415 if ((ctxt->d & IncSP) && 1416 base_reg == VCPU_REGS_RSP) 1417 modrm_ea += ctxt->op_bytes; 1418 } 1419 if (index_reg != 4) 1420 modrm_ea += reg_read(ctxt, index_reg) << scale; 1421 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { 1422 modrm_ea += insn_fetch(s32, ctxt); 1423 if (ctxt->mode == X86EMUL_MODE_PROT64) 1424 ctxt->rip_relative = 1; 1425 } else { 1426 base_reg = ctxt->modrm_rm; 1427 modrm_ea += reg_read(ctxt, base_reg); 1428 adjust_modrm_seg(ctxt, base_reg); 1429 } 1430 switch (ctxt->modrm_mod) { 1431 case 1: 1432 modrm_ea += insn_fetch(s8, ctxt); 1433 break; 1434 case 2: 1435 modrm_ea += insn_fetch(s32, ctxt); 1436 break; 1437 } 1438 } 1439 op->addr.mem.ea = modrm_ea; 1440 if (ctxt->ad_bytes != 8) 1441 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; 1442 1443done: 1444 return rc; 1445} 1446 1447static int decode_abs(struct x86_emulate_ctxt *ctxt, 1448 struct operand *op) 1449{ 1450 int rc = X86EMUL_CONTINUE; 1451 1452 op->type = OP_MEM; 1453 switch (ctxt->ad_bytes) { 1454 case 2: 1455 op->addr.mem.ea = insn_fetch(u16, ctxt); 1456 break; 1457 case 4: 1458 op->addr.mem.ea = insn_fetch(u32, ctxt); 1459 break; 1460 case 8: 1461 op->addr.mem.ea = insn_fetch(u64, ctxt); 1462 break; 1463 } 1464done: 1465 return rc; 1466} 1467 1468static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) 1469{ 1470 long sv = 0, mask; 1471 1472 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { 1473 mask = ~((long)ctxt->dst.bytes * 8 - 1); 1474 1475 if (ctxt->src.bytes == 2) 1476 sv = (s16)ctxt->src.val & (s16)mask; 1477 else if (ctxt->src.bytes == 4) 1478 sv = (s32)ctxt->src.val & (s32)mask; 1479 else 1480 sv = (s64)ctxt->src.val & (s64)mask; 1481 1482 ctxt->dst.addr.mem.ea = address_mask(ctxt, 1483 ctxt->dst.addr.mem.ea + (sv >> 3)); 1484 } 1485 1486 /* only subword offset */ 1487 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; 1488} 1489 1490static int read_emulated(struct x86_emulate_ctxt *ctxt, 1491 unsigned long addr, void *dest, unsigned size) 1492{ 1493 int rc; 1494 struct read_cache *mc = &ctxt->mem_read; 1495 1496 if (mc->pos < mc->end) 1497 goto read_cached; 1498 1499 WARN_ON((mc->end + size) >= sizeof(mc->data)); 1500 1501 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size, 1502 &ctxt->exception); 1503 if (rc != X86EMUL_CONTINUE) 1504 return rc; 1505 1506 mc->end += size; 1507 1508read_cached: 1509 memcpy(dest, mc->data + mc->pos, size); 1510 mc->pos += size; 1511 return X86EMUL_CONTINUE; 1512} 1513 1514static int segmented_read(struct x86_emulate_ctxt *ctxt, 1515 struct segmented_address addr, 1516 void *data, 1517 unsigned size) 1518{ 1519 int rc; 1520 ulong linear; 1521 1522 rc = linearize(ctxt, addr, size, false, &linear); 1523 if (rc != X86EMUL_CONTINUE) 1524 return rc; 1525 return read_emulated(ctxt, linear, data, size); 1526} 1527 1528static int segmented_write(struct x86_emulate_ctxt *ctxt, 1529 struct segmented_address addr, 1530 const void *data, 1531 unsigned size) 1532{ 1533 int rc; 1534 ulong linear; 1535 1536 rc = linearize(ctxt, addr, size, true, &linear); 1537 if (rc != X86EMUL_CONTINUE) 1538 return rc; 1539 return ctxt->ops->write_emulated(ctxt, linear, data, size, 1540 &ctxt->exception); 1541} 1542 1543static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, 1544 struct segmented_address addr, 1545 const void *orig_data, const void *data, 1546 unsigned size) 1547{ 1548 int rc; 1549 ulong linear; 1550 1551 rc = linearize(ctxt, addr, size, true, &linear); 1552 if (rc != X86EMUL_CONTINUE) 1553 return rc; 1554 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, 1555 size, &ctxt->exception); 1556} 1557 1558static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, 1559 unsigned int size, unsigned short port, 1560 void *dest) 1561{ 1562 struct read_cache *rc = &ctxt->io_read; 1563 1564 if (rc->pos == rc->end) { /* refill pio read ahead */ 1565 unsigned int in_page, n; 1566 unsigned int count = ctxt->rep_prefix ? 1567 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1; 1568 in_page = (ctxt->eflags & X86_EFLAGS_DF) ? 1569 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) : 1570 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)); 1571 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count); 1572 if (n == 0) 1573 n = 1; 1574 rc->pos = rc->end = 0; 1575 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) 1576 return 0; 1577 rc->end = n * size; 1578 } 1579 1580 if (ctxt->rep_prefix && (ctxt->d & String) && 1581 !(ctxt->eflags & X86_EFLAGS_DF)) { 1582 ctxt->dst.data = rc->data + rc->pos; 1583 ctxt->dst.type = OP_MEM_STR; 1584 ctxt->dst.count = (rc->end - rc->pos) / size; 1585 rc->pos = rc->end; 1586 } else { 1587 memcpy(dest, rc->data + rc->pos, size); 1588 rc->pos += size; 1589 } 1590 return 1; 1591} 1592 1593static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, 1594 u16 index, struct desc_struct *desc) 1595{ 1596 struct desc_ptr dt; 1597 ulong addr; 1598 1599 ctxt->ops->get_idt(ctxt, &dt); 1600 1601 if (dt.size < index * 8 + 7) 1602 return emulate_gp(ctxt, index << 3 | 0x2); 1603 1604 addr = dt.address + index * 8; 1605 return linear_read_system(ctxt, addr, desc, sizeof(*desc)); 1606} 1607 1608static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, 1609 u16 selector, struct desc_ptr *dt) 1610{ 1611 const struct x86_emulate_ops *ops = ctxt->ops; 1612 u32 base3 = 0; 1613 1614 if (selector & 1 << 2) { 1615 struct desc_struct desc; 1616 u16 sel; 1617 1618 memset(dt, 0, sizeof(*dt)); 1619 if (!ops->get_segment(ctxt, &sel, &desc, &base3, 1620 VCPU_SREG_LDTR)) 1621 return; 1622 1623 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ 1624 dt->address = get_desc_base(&desc) | ((u64)base3 << 32); 1625 } else 1626 ops->get_gdt(ctxt, dt); 1627} 1628 1629static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt, 1630 u16 selector, ulong *desc_addr_p) 1631{ 1632 struct desc_ptr dt; 1633 u16 index = selector >> 3; 1634 ulong addr; 1635 1636 get_descriptor_table_ptr(ctxt, selector, &dt); 1637 1638 if (dt.size < index * 8 + 7) 1639 return emulate_gp(ctxt, selector & 0xfffc); 1640 1641 addr = dt.address + index * 8; 1642 1643#ifdef CONFIG_X86_64 1644 if (addr >> 32 != 0) { 1645 u64 efer = 0; 1646 1647 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1648 if (!(efer & EFER_LMA)) 1649 addr &= (u32)-1; 1650 } 1651#endif 1652 1653 *desc_addr_p = addr; 1654 return X86EMUL_CONTINUE; 1655} 1656 1657/* allowed just for 8 bytes segments */ 1658static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1659 u16 selector, struct desc_struct *desc, 1660 ulong *desc_addr_p) 1661{ 1662 int rc; 1663 1664 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p); 1665 if (rc != X86EMUL_CONTINUE) 1666 return rc; 1667 1668 return linear_read_system(ctxt, *desc_addr_p, desc, sizeof(*desc)); 1669} 1670 1671/* allowed just for 8 bytes segments */ 1672static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1673 u16 selector, struct desc_struct *desc) 1674{ 1675 int rc; 1676 ulong addr; 1677 1678 rc = get_descriptor_ptr(ctxt, selector, &addr); 1679 if (rc != X86EMUL_CONTINUE) 1680 return rc; 1681 1682 return linear_write_system(ctxt, addr, desc, sizeof(*desc)); 1683} 1684 1685static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1686 u16 selector, int seg, u8 cpl, 1687 enum x86_transfer_type transfer, 1688 struct desc_struct *desc) 1689{ 1690 struct desc_struct seg_desc, old_desc; 1691 u8 dpl, rpl; 1692 unsigned err_vec = GP_VECTOR; 1693 u32 err_code = 0; 1694 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ 1695 ulong desc_addr; 1696 int ret; 1697 u16 dummy; 1698 u32 base3 = 0; 1699 1700 memset(&seg_desc, 0, sizeof(seg_desc)); 1701 1702 if (ctxt->mode == X86EMUL_MODE_REAL) { 1703 /* set real mode segment descriptor (keep limit etc. for 1704 * unreal mode) */ 1705 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg); 1706 set_desc_base(&seg_desc, selector << 4); 1707 goto load; 1708 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) { 1709 /* VM86 needs a clean new segment descriptor */ 1710 set_desc_base(&seg_desc, selector << 4); 1711 set_desc_limit(&seg_desc, 0xffff); 1712 seg_desc.type = 3; 1713 seg_desc.p = 1; 1714 seg_desc.s = 1; 1715 seg_desc.dpl = 3; 1716 goto load; 1717 } 1718 1719 rpl = selector & 3; 1720 1721 /* TR should be in GDT only */ 1722 if (seg == VCPU_SREG_TR && (selector & (1 << 2))) 1723 goto exception; 1724 1725 /* NULL selector is not valid for TR, CS and (except for long mode) SS */ 1726 if (null_selector) { 1727 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR) 1728 goto exception; 1729 1730 if (seg == VCPU_SREG_SS) { 1731 if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl) 1732 goto exception; 1733 1734 /* 1735 * ctxt->ops->set_segment expects the CPL to be in 1736 * SS.DPL, so fake an expand-up 32-bit data segment. 1737 */ 1738 seg_desc.type = 3; 1739 seg_desc.p = 1; 1740 seg_desc.s = 1; 1741 seg_desc.dpl = cpl; 1742 seg_desc.d = 1; 1743 seg_desc.g = 1; 1744 } 1745 1746 /* Skip all following checks */ 1747 goto load; 1748 } 1749 1750 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr); 1751 if (ret != X86EMUL_CONTINUE) 1752 return ret; 1753 1754 err_code = selector & 0xfffc; 1755 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR : 1756 GP_VECTOR; 1757 1758 /* can't load system descriptor into segment selector */ 1759 if (seg <= VCPU_SREG_GS && !seg_desc.s) { 1760 if (transfer == X86_TRANSFER_CALL_JMP) 1761 return X86EMUL_UNHANDLEABLE; 1762 goto exception; 1763 } 1764 1765 dpl = seg_desc.dpl; 1766 1767 switch (seg) { 1768 case VCPU_SREG_SS: 1769 /* 1770 * segment is not a writable data segment or segment 1771 * selector's RPL != CPL or segment selector's RPL != CPL 1772 */ 1773 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) 1774 goto exception; 1775 break; 1776 case VCPU_SREG_CS: 1777 if (!(seg_desc.type & 8)) 1778 goto exception; 1779 1780 if (seg_desc.type & 4) { 1781 /* conforming */ 1782 if (dpl > cpl) 1783 goto exception; 1784 } else { 1785 /* nonconforming */ 1786 if (rpl > cpl || dpl != cpl) 1787 goto exception; 1788 } 1789 /* in long-mode d/b must be clear if l is set */ 1790 if (seg_desc.d && seg_desc.l) { 1791 u64 efer = 0; 1792 1793 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1794 if (efer & EFER_LMA) 1795 goto exception; 1796 } 1797 1798 /* CS(RPL) <- CPL */ 1799 selector = (selector & 0xfffc) | cpl; 1800 break; 1801 case VCPU_SREG_TR: 1802 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) 1803 goto exception; 1804 break; 1805 case VCPU_SREG_LDTR: 1806 if (seg_desc.s || seg_desc.type != 2) 1807 goto exception; 1808 break; 1809 default: /* DS, ES, FS, or GS */ 1810 /* 1811 * segment is not a data or readable code segment or 1812 * ((segment is a data or nonconforming code segment) 1813 * and (both RPL and CPL > DPL)) 1814 */ 1815 if ((seg_desc.type & 0xa) == 0x8 || 1816 (((seg_desc.type & 0xc) != 0xc) && 1817 (rpl > dpl && cpl > dpl))) 1818 goto exception; 1819 break; 1820 } 1821 1822 if (!seg_desc.p) { 1823 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; 1824 goto exception; 1825 } 1826 1827 if (seg_desc.s) { 1828 /* mark segment as accessed */ 1829 if (!(seg_desc.type & 1)) { 1830 seg_desc.type |= 1; 1831 ret = write_segment_descriptor(ctxt, selector, 1832 &seg_desc); 1833 if (ret != X86EMUL_CONTINUE) 1834 return ret; 1835 } 1836 } else if (ctxt->mode == X86EMUL_MODE_PROT64) { 1837 ret = linear_read_system(ctxt, desc_addr+8, &base3, sizeof(base3)); 1838 if (ret != X86EMUL_CONTINUE) 1839 return ret; 1840 if (emul_is_noncanonical_address(get_desc_base(&seg_desc) | 1841 ((u64)base3 << 32), ctxt)) 1842 return emulate_gp(ctxt, err_code); 1843 } 1844 1845 if (seg == VCPU_SREG_TR) { 1846 old_desc = seg_desc; 1847 seg_desc.type |= 2; /* busy */ 1848 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc, 1849 sizeof(seg_desc), &ctxt->exception); 1850 if (ret != X86EMUL_CONTINUE) 1851 return ret; 1852 } 1853load: 1854 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg); 1855 if (desc) 1856 *desc = seg_desc; 1857 return X86EMUL_CONTINUE; 1858exception: 1859 return emulate_exception(ctxt, err_vec, err_code, true); 1860} 1861 1862static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1863 u16 selector, int seg) 1864{ 1865 u8 cpl = ctxt->ops->cpl(ctxt); 1866 1867 /* 1868 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but 1869 * they can load it at CPL<3 (Intel's manual says only LSS can, 1870 * but it's wrong). 1871 * 1872 * However, the Intel manual says that putting IST=1/DPL=3 in 1873 * an interrupt gate will result in SS=3 (the AMD manual instead 1874 * says it doesn't), so allow SS=3 in __load_segment_descriptor 1875 * and only forbid it here. 1876 */ 1877 if (seg == VCPU_SREG_SS && selector == 3 && 1878 ctxt->mode == X86EMUL_MODE_PROT64) 1879 return emulate_exception(ctxt, GP_VECTOR, 0, true); 1880 1881 return __load_segment_descriptor(ctxt, selector, seg, cpl, 1882 X86_TRANSFER_NONE, NULL); 1883} 1884 1885static void write_register_operand(struct operand *op) 1886{ 1887 return assign_register(op->addr.reg, op->val, op->bytes); 1888} 1889 1890static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op) 1891{ 1892 switch (op->type) { 1893 case OP_REG: 1894 write_register_operand(op); 1895 break; 1896 case OP_MEM: 1897 if (ctxt->lock_prefix) 1898 return segmented_cmpxchg(ctxt, 1899 op->addr.mem, 1900 &op->orig_val, 1901 &op->val, 1902 op->bytes); 1903 else 1904 return segmented_write(ctxt, 1905 op->addr.mem, 1906 &op->val, 1907 op->bytes); 1908 break; 1909 case OP_MEM_STR: 1910 return segmented_write(ctxt, 1911 op->addr.mem, 1912 op->data, 1913 op->bytes * op->count); 1914 break; 1915 case OP_XMM: 1916 write_sse_reg(&op->vec_val, op->addr.xmm); 1917 break; 1918 case OP_MM: 1919 write_mmx_reg(&op->mm_val, op->addr.mm); 1920 break; 1921 case OP_NONE: 1922 /* no writeback */ 1923 break; 1924 default: 1925 break; 1926 } 1927 return X86EMUL_CONTINUE; 1928} 1929 1930static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes) 1931{ 1932 struct segmented_address addr; 1933 1934 rsp_increment(ctxt, -bytes); 1935 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1936 addr.seg = VCPU_SREG_SS; 1937 1938 return segmented_write(ctxt, addr, data, bytes); 1939} 1940 1941static int em_push(struct x86_emulate_ctxt *ctxt) 1942{ 1943 /* Disable writeback. */ 1944 ctxt->dst.type = OP_NONE; 1945 return push(ctxt, &ctxt->src.val, ctxt->op_bytes); 1946} 1947 1948static int emulate_pop(struct x86_emulate_ctxt *ctxt, 1949 void *dest, int len) 1950{ 1951 int rc; 1952 struct segmented_address addr; 1953 1954 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1955 addr.seg = VCPU_SREG_SS; 1956 rc = segmented_read(ctxt, addr, dest, len); 1957 if (rc != X86EMUL_CONTINUE) 1958 return rc; 1959 1960 rsp_increment(ctxt, len); 1961 return rc; 1962} 1963 1964static int em_pop(struct x86_emulate_ctxt *ctxt) 1965{ 1966 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1967} 1968 1969static int emulate_popf(struct x86_emulate_ctxt *ctxt, 1970 void *dest, int len) 1971{ 1972 int rc; 1973 unsigned long val, change_mask; 1974 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 1975 int cpl = ctxt->ops->cpl(ctxt); 1976 1977 rc = emulate_pop(ctxt, &val, len); 1978 if (rc != X86EMUL_CONTINUE) 1979 return rc; 1980 1981 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 1982 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF | 1983 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT | 1984 X86_EFLAGS_AC | X86_EFLAGS_ID; 1985 1986 switch(ctxt->mode) { 1987 case X86EMUL_MODE_PROT64: 1988 case X86EMUL_MODE_PROT32: 1989 case X86EMUL_MODE_PROT16: 1990 if (cpl == 0) 1991 change_mask |= X86_EFLAGS_IOPL; 1992 if (cpl <= iopl) 1993 change_mask |= X86_EFLAGS_IF; 1994 break; 1995 case X86EMUL_MODE_VM86: 1996 if (iopl < 3) 1997 return emulate_gp(ctxt, 0); 1998 change_mask |= X86_EFLAGS_IF; 1999 break; 2000 default: /* real mode */ 2001 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF); 2002 break; 2003 } 2004 2005 *(unsigned long *)dest = 2006 (ctxt->eflags & ~change_mask) | (val & change_mask); 2007 2008 return rc; 2009} 2010 2011static int em_popf(struct x86_emulate_ctxt *ctxt) 2012{ 2013 ctxt->dst.type = OP_REG; 2014 ctxt->dst.addr.reg = &ctxt->eflags; 2015 ctxt->dst.bytes = ctxt->op_bytes; 2016 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); 2017} 2018 2019static int em_enter(struct x86_emulate_ctxt *ctxt) 2020{ 2021 int rc; 2022 unsigned frame_size = ctxt->src.val; 2023 unsigned nesting_level = ctxt->src2.val & 31; 2024 ulong rbp; 2025 2026 if (nesting_level) 2027 return X86EMUL_UNHANDLEABLE; 2028 2029 rbp = reg_read(ctxt, VCPU_REGS_RBP); 2030 rc = push(ctxt, &rbp, stack_size(ctxt)); 2031 if (rc != X86EMUL_CONTINUE) 2032 return rc; 2033 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP), 2034 stack_mask(ctxt)); 2035 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), 2036 reg_read(ctxt, VCPU_REGS_RSP) - frame_size, 2037 stack_mask(ctxt)); 2038 return X86EMUL_CONTINUE; 2039} 2040 2041static int em_leave(struct x86_emulate_ctxt *ctxt) 2042{ 2043 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP), 2044 stack_mask(ctxt)); 2045 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes); 2046} 2047 2048static int em_push_sreg(struct x86_emulate_ctxt *ctxt) 2049{ 2050 int seg = ctxt->src2.val; 2051 2052 ctxt->src.val = get_segment_selector(ctxt, seg); 2053 if (ctxt->op_bytes == 4) { 2054 rsp_increment(ctxt, -2); 2055 ctxt->op_bytes = 2; 2056 } 2057 2058 return em_push(ctxt); 2059} 2060 2061static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) 2062{ 2063 int seg = ctxt->src2.val; 2064 unsigned long selector; 2065 int rc; 2066 2067 rc = emulate_pop(ctxt, &selector, 2); 2068 if (rc != X86EMUL_CONTINUE) 2069 return rc; 2070 2071 if (seg == VCPU_SREG_SS) 2072 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 2073 if (ctxt->op_bytes > 2) 2074 rsp_increment(ctxt, ctxt->op_bytes - 2); 2075 2076 rc = load_segment_descriptor(ctxt, (u16)selector, seg); 2077 return rc; 2078} 2079 2080static int em_pusha(struct x86_emulate_ctxt *ctxt) 2081{ 2082 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP); 2083 int rc = X86EMUL_CONTINUE; 2084 int reg = VCPU_REGS_RAX; 2085 2086 while (reg <= VCPU_REGS_RDI) { 2087 (reg == VCPU_REGS_RSP) ? 2088 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg)); 2089 2090 rc = em_push(ctxt); 2091 if (rc != X86EMUL_CONTINUE) 2092 return rc; 2093 2094 ++reg; 2095 } 2096 2097 return rc; 2098} 2099 2100static int em_pushf(struct x86_emulate_ctxt *ctxt) 2101{ 2102 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM; 2103 return em_push(ctxt); 2104} 2105 2106static int em_popa(struct x86_emulate_ctxt *ctxt) 2107{ 2108 int rc = X86EMUL_CONTINUE; 2109 int reg = VCPU_REGS_RDI; 2110 u32 val; 2111 2112 while (reg >= VCPU_REGS_RAX) { 2113 if (reg == VCPU_REGS_RSP) { 2114 rsp_increment(ctxt, ctxt->op_bytes); 2115 --reg; 2116 } 2117 2118 rc = emulate_pop(ctxt, &val, ctxt->op_bytes); 2119 if (rc != X86EMUL_CONTINUE) 2120 break; 2121 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes); 2122 --reg; 2123 } 2124 return rc; 2125} 2126 2127static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 2128{ 2129 const struct x86_emulate_ops *ops = ctxt->ops; 2130 int rc; 2131 struct desc_ptr dt; 2132 gva_t cs_addr; 2133 gva_t eip_addr; 2134 u16 cs, eip; 2135 2136 /* TODO: Add limit checks */ 2137 ctxt->src.val = ctxt->eflags; 2138 rc = em_push(ctxt); 2139 if (rc != X86EMUL_CONTINUE) 2140 return rc; 2141 2142 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC); 2143 2144 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); 2145 rc = em_push(ctxt); 2146 if (rc != X86EMUL_CONTINUE) 2147 return rc; 2148 2149 ctxt->src.val = ctxt->_eip; 2150 rc = em_push(ctxt); 2151 if (rc != X86EMUL_CONTINUE) 2152 return rc; 2153 2154 ops->get_idt(ctxt, &dt); 2155 2156 eip_addr = dt.address + (irq << 2); 2157 cs_addr = dt.address + (irq << 2) + 2; 2158 2159 rc = linear_read_system(ctxt, cs_addr, &cs, 2); 2160 if (rc != X86EMUL_CONTINUE) 2161 return rc; 2162 2163 rc = linear_read_system(ctxt, eip_addr, &eip, 2); 2164 if (rc != X86EMUL_CONTINUE) 2165 return rc; 2166 2167 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); 2168 if (rc != X86EMUL_CONTINUE) 2169 return rc; 2170 2171 ctxt->_eip = eip; 2172 2173 return rc; 2174} 2175 2176int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 2177{ 2178 int rc; 2179 2180 invalidate_registers(ctxt); 2181 rc = __emulate_int_real(ctxt, irq); 2182 if (rc == X86EMUL_CONTINUE) 2183 writeback_registers(ctxt); 2184 return rc; 2185} 2186 2187static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) 2188{ 2189 switch(ctxt->mode) { 2190 case X86EMUL_MODE_REAL: 2191 return __emulate_int_real(ctxt, irq); 2192 case X86EMUL_MODE_VM86: 2193 case X86EMUL_MODE_PROT16: 2194 case X86EMUL_MODE_PROT32: 2195 case X86EMUL_MODE_PROT64: 2196 default: 2197 /* Protected mode interrupts unimplemented yet */ 2198 return X86EMUL_UNHANDLEABLE; 2199 } 2200} 2201 2202static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) 2203{ 2204 int rc = X86EMUL_CONTINUE; 2205 unsigned long temp_eip = 0; 2206 unsigned long temp_eflags = 0; 2207 unsigned long cs = 0; 2208 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 2209 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF | 2210 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF | 2211 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF | 2212 X86_EFLAGS_AC | X86_EFLAGS_ID | 2213 X86_EFLAGS_FIXED; 2214 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF | 2215 X86_EFLAGS_VIP; 2216 2217 /* TODO: Add stack limit check */ 2218 2219 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); 2220 2221 if (rc != X86EMUL_CONTINUE) 2222 return rc; 2223 2224 if (temp_eip & ~0xffff) 2225 return emulate_gp(ctxt, 0); 2226 2227 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2228 2229 if (rc != X86EMUL_CONTINUE) 2230 return rc; 2231 2232 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); 2233 2234 if (rc != X86EMUL_CONTINUE) 2235 return rc; 2236 2237 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); 2238 2239 if (rc != X86EMUL_CONTINUE) 2240 return rc; 2241 2242 ctxt->_eip = temp_eip; 2243 2244 if (ctxt->op_bytes == 4) 2245 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); 2246 else if (ctxt->op_bytes == 2) { 2247 ctxt->eflags &= ~0xffff; 2248 ctxt->eflags |= temp_eflags; 2249 } 2250 2251 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ 2252 ctxt->eflags |= X86_EFLAGS_FIXED; 2253 ctxt->ops->set_nmi_mask(ctxt, false); 2254 2255 return rc; 2256} 2257 2258static int em_iret(struct x86_emulate_ctxt *ctxt) 2259{ 2260 switch(ctxt->mode) { 2261 case X86EMUL_MODE_REAL: 2262 return emulate_iret_real(ctxt); 2263 case X86EMUL_MODE_VM86: 2264 case X86EMUL_MODE_PROT16: 2265 case X86EMUL_MODE_PROT32: 2266 case X86EMUL_MODE_PROT64: 2267 default: 2268 /* iret from protected mode unimplemented yet */ 2269 return X86EMUL_UNHANDLEABLE; 2270 } 2271} 2272 2273static int em_jmp_far(struct x86_emulate_ctxt *ctxt) 2274{ 2275 int rc; 2276 unsigned short sel; 2277 struct desc_struct new_desc; 2278 u8 cpl = ctxt->ops->cpl(ctxt); 2279 2280 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2281 2282 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 2283 X86_TRANSFER_CALL_JMP, 2284 &new_desc); 2285 if (rc != X86EMUL_CONTINUE) 2286 return rc; 2287 2288 rc = assign_eip_far(ctxt, ctxt->src.val); 2289 /* Error handling is not implemented. */ 2290 if (rc != X86EMUL_CONTINUE) 2291 return X86EMUL_UNHANDLEABLE; 2292 2293 return rc; 2294} 2295 2296static int em_jmp_abs(struct x86_emulate_ctxt *ctxt) 2297{ 2298 return assign_eip_near(ctxt, ctxt->src.val); 2299} 2300 2301static int em_call_near_abs(struct x86_emulate_ctxt *ctxt) 2302{ 2303 int rc; 2304 long int old_eip; 2305 2306 old_eip = ctxt->_eip; 2307 rc = assign_eip_near(ctxt, ctxt->src.val); 2308 if (rc != X86EMUL_CONTINUE) 2309 return rc; 2310 ctxt->src.val = old_eip; 2311 rc = em_push(ctxt); 2312 return rc; 2313} 2314 2315static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) 2316{ 2317 u64 old = ctxt->dst.orig_val64; 2318 2319 if (ctxt->dst.bytes == 16) 2320 return X86EMUL_UNHANDLEABLE; 2321 2322 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) || 2323 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) { 2324 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0); 2325 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32); 2326 ctxt->eflags &= ~X86_EFLAGS_ZF; 2327 } else { 2328 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) | 2329 (u32) reg_read(ctxt, VCPU_REGS_RBX); 2330 2331 ctxt->eflags |= X86_EFLAGS_ZF; 2332 } 2333 return X86EMUL_CONTINUE; 2334} 2335 2336static int em_ret(struct x86_emulate_ctxt *ctxt) 2337{ 2338 int rc; 2339 unsigned long eip; 2340 2341 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2342 if (rc != X86EMUL_CONTINUE) 2343 return rc; 2344 2345 return assign_eip_near(ctxt, eip); 2346} 2347 2348static int em_ret_far(struct x86_emulate_ctxt *ctxt) 2349{ 2350 int rc; 2351 unsigned long eip, cs; 2352 int cpl = ctxt->ops->cpl(ctxt); 2353 struct desc_struct new_desc; 2354 2355 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2356 if (rc != X86EMUL_CONTINUE) 2357 return rc; 2358 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2359 if (rc != X86EMUL_CONTINUE) 2360 return rc; 2361 /* Outer-privilege level return is not implemented */ 2362 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl) 2363 return X86EMUL_UNHANDLEABLE; 2364 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl, 2365 X86_TRANSFER_RET, 2366 &new_desc); 2367 if (rc != X86EMUL_CONTINUE) 2368 return rc; 2369 rc = assign_eip_far(ctxt, eip); 2370 /* Error handling is not implemented. */ 2371 if (rc != X86EMUL_CONTINUE) 2372 return X86EMUL_UNHANDLEABLE; 2373 2374 return rc; 2375} 2376 2377static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt) 2378{ 2379 int rc; 2380 2381 rc = em_ret_far(ctxt); 2382 if (rc != X86EMUL_CONTINUE) 2383 return rc; 2384 rsp_increment(ctxt, ctxt->src.val); 2385 return X86EMUL_CONTINUE; 2386} 2387 2388static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) 2389{ 2390 /* Save real source value, then compare EAX against destination. */ 2391 ctxt->dst.orig_val = ctxt->dst.val; 2392 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX); 2393 ctxt->src.orig_val = ctxt->src.val; 2394 ctxt->src.val = ctxt->dst.orig_val; 2395 fastop(ctxt, em_cmp); 2396 2397 if (ctxt->eflags & X86_EFLAGS_ZF) { 2398 /* Success: write back to memory; no update of EAX */ 2399 ctxt->src.type = OP_NONE; 2400 ctxt->dst.val = ctxt->src.orig_val; 2401 } else { 2402 /* Failure: write the value we saw to EAX. */ 2403 ctxt->src.type = OP_REG; 2404 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 2405 ctxt->src.val = ctxt->dst.orig_val; 2406 /* Create write-cycle to dest by writing the same value */ 2407 ctxt->dst.val = ctxt->dst.orig_val; 2408 } 2409 return X86EMUL_CONTINUE; 2410} 2411 2412static int em_lseg(struct x86_emulate_ctxt *ctxt) 2413{ 2414 int seg = ctxt->src2.val; 2415 unsigned short sel; 2416 int rc; 2417 2418 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2419 2420 rc = load_segment_descriptor(ctxt, sel, seg); 2421 if (rc != X86EMUL_CONTINUE) 2422 return rc; 2423 2424 ctxt->dst.val = ctxt->src.val; 2425 return rc; 2426} 2427 2428static int emulator_has_longmode(struct x86_emulate_ctxt *ctxt) 2429{ 2430#ifdef CONFIG_X86_64 2431 return ctxt->ops->guest_has_long_mode(ctxt); 2432#else 2433 return false; 2434#endif 2435} 2436 2437static void rsm_set_desc_flags(struct desc_struct *desc, u32 flags) 2438{ 2439 desc->g = (flags >> 23) & 1; 2440 desc->d = (flags >> 22) & 1; 2441 desc->l = (flags >> 21) & 1; 2442 desc->avl = (flags >> 20) & 1; 2443 desc->p = (flags >> 15) & 1; 2444 desc->dpl = (flags >> 13) & 3; 2445 desc->s = (flags >> 12) & 1; 2446 desc->type = (flags >> 8) & 15; 2447} 2448 2449static int rsm_load_seg_32(struct x86_emulate_ctxt *ctxt, const char *smstate, 2450 int n) 2451{ 2452 struct desc_struct desc; 2453 int offset; 2454 u16 selector; 2455 2456 selector = GET_SMSTATE(u32, smstate, 0x7fa8 + n * 4); 2457 2458 if (n < 3) 2459 offset = 0x7f84 + n * 12; 2460 else 2461 offset = 0x7f2c + (n - 3) * 12; 2462 2463 set_desc_base(&desc, GET_SMSTATE(u32, smstate, offset + 8)); 2464 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, offset + 4)); 2465 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, offset)); 2466 ctxt->ops->set_segment(ctxt, selector, &desc, 0, n); 2467 return X86EMUL_CONTINUE; 2468} 2469 2470#ifdef CONFIG_X86_64 2471static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, const char *smstate, 2472 int n) 2473{ 2474 struct desc_struct desc; 2475 int offset; 2476 u16 selector; 2477 u32 base3; 2478 2479 offset = 0x7e00 + n * 16; 2480 2481 selector = GET_SMSTATE(u16, smstate, offset); 2482 rsm_set_desc_flags(&desc, GET_SMSTATE(u16, smstate, offset + 2) << 8); 2483 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, offset + 4)); 2484 set_desc_base(&desc, GET_SMSTATE(u32, smstate, offset + 8)); 2485 base3 = GET_SMSTATE(u32, smstate, offset + 12); 2486 2487 ctxt->ops->set_segment(ctxt, selector, &desc, base3, n); 2488 return X86EMUL_CONTINUE; 2489} 2490#endif 2491 2492static int rsm_enter_protected_mode(struct x86_emulate_ctxt *ctxt, 2493 u64 cr0, u64 cr3, u64 cr4) 2494{ 2495 int bad; 2496 u64 pcid; 2497 2498 /* In order to later set CR4.PCIDE, CR3[11:0] must be zero. */ 2499 pcid = 0; 2500 if (cr4 & X86_CR4_PCIDE) { 2501 pcid = cr3 & 0xfff; 2502 cr3 &= ~0xfff; 2503 } 2504 2505 bad = ctxt->ops->set_cr(ctxt, 3, cr3); 2506 if (bad) 2507 return X86EMUL_UNHANDLEABLE; 2508 2509 /* 2510 * First enable PAE, long mode needs it before CR0.PG = 1 is set. 2511 * Then enable protected mode. However, PCID cannot be enabled 2512 * if EFER.LMA=0, so set it separately. 2513 */ 2514 bad = ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE); 2515 if (bad) 2516 return X86EMUL_UNHANDLEABLE; 2517 2518 bad = ctxt->ops->set_cr(ctxt, 0, cr0); 2519 if (bad) 2520 return X86EMUL_UNHANDLEABLE; 2521 2522 if (cr4 & X86_CR4_PCIDE) { 2523 bad = ctxt->ops->set_cr(ctxt, 4, cr4); 2524 if (bad) 2525 return X86EMUL_UNHANDLEABLE; 2526 if (pcid) { 2527 bad = ctxt->ops->set_cr(ctxt, 3, cr3 | pcid); 2528 if (bad) 2529 return X86EMUL_UNHANDLEABLE; 2530 } 2531 2532 } 2533 2534 return X86EMUL_CONTINUE; 2535} 2536 2537static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt, 2538 const char *smstate) 2539{ 2540 struct desc_struct desc; 2541 struct desc_ptr dt; 2542 u16 selector; 2543 u32 val, cr0, cr3, cr4; 2544 int i; 2545 2546 cr0 = GET_SMSTATE(u32, smstate, 0x7ffc); 2547 cr3 = GET_SMSTATE(u32, smstate, 0x7ff8); 2548 ctxt->eflags = GET_SMSTATE(u32, smstate, 0x7ff4) | X86_EFLAGS_FIXED; 2549 ctxt->_eip = GET_SMSTATE(u32, smstate, 0x7ff0); 2550 2551 for (i = 0; i < 8; i++) 2552 *reg_write(ctxt, i) = GET_SMSTATE(u32, smstate, 0x7fd0 + i * 4); 2553 2554 val = GET_SMSTATE(u32, smstate, 0x7fcc); 2555 2556 if (ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1)) 2557 return X86EMUL_UNHANDLEABLE; 2558 2559 val = GET_SMSTATE(u32, smstate, 0x7fc8); 2560 2561 if (ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1)) 2562 return X86EMUL_UNHANDLEABLE; 2563 2564 selector = GET_SMSTATE(u32, smstate, 0x7fc4); 2565 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7f64)); 2566 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7f60)); 2567 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7f5c)); 2568 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_TR); 2569 2570 selector = GET_SMSTATE(u32, smstate, 0x7fc0); 2571 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7f80)); 2572 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7f7c)); 2573 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7f78)); 2574 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_LDTR); 2575 2576 dt.address = GET_SMSTATE(u32, smstate, 0x7f74); 2577 dt.size = GET_SMSTATE(u32, smstate, 0x7f70); 2578 ctxt->ops->set_gdt(ctxt, &dt); 2579 2580 dt.address = GET_SMSTATE(u32, smstate, 0x7f58); 2581 dt.size = GET_SMSTATE(u32, smstate, 0x7f54); 2582 ctxt->ops->set_idt(ctxt, &dt); 2583 2584 for (i = 0; i < 6; i++) { 2585 int r = rsm_load_seg_32(ctxt, smstate, i); 2586 if (r != X86EMUL_CONTINUE) 2587 return r; 2588 } 2589 2590 cr4 = GET_SMSTATE(u32, smstate, 0x7f14); 2591 2592 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smstate, 0x7ef8)); 2593 2594 return rsm_enter_protected_mode(ctxt, cr0, cr3, cr4); 2595} 2596 2597#ifdef CONFIG_X86_64 2598static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt, 2599 const char *smstate) 2600{ 2601 struct desc_struct desc; 2602 struct desc_ptr dt; 2603 u64 val, cr0, cr3, cr4; 2604 u32 base3; 2605 u16 selector; 2606 int i, r; 2607 2608 for (i = 0; i < 16; i++) 2609 *reg_write(ctxt, i) = GET_SMSTATE(u64, smstate, 0x7ff8 - i * 8); 2610 2611 ctxt->_eip = GET_SMSTATE(u64, smstate, 0x7f78); 2612 ctxt->eflags = GET_SMSTATE(u32, smstate, 0x7f70) | X86_EFLAGS_FIXED; 2613 2614 val = GET_SMSTATE(u64, smstate, 0x7f68); 2615 2616 if (ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1)) 2617 return X86EMUL_UNHANDLEABLE; 2618 2619 val = GET_SMSTATE(u64, smstate, 0x7f60); 2620 2621 if (ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1)) 2622 return X86EMUL_UNHANDLEABLE; 2623 2624 cr0 = GET_SMSTATE(u64, smstate, 0x7f58); 2625 cr3 = GET_SMSTATE(u64, smstate, 0x7f50); 2626 cr4 = GET_SMSTATE(u64, smstate, 0x7f48); 2627 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smstate, 0x7f00)); 2628 val = GET_SMSTATE(u64, smstate, 0x7ed0); 2629 2630 if (ctxt->ops->set_msr(ctxt, MSR_EFER, val & ~EFER_LMA)) 2631 return X86EMUL_UNHANDLEABLE; 2632 2633 selector = GET_SMSTATE(u32, smstate, 0x7e90); 2634 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7e92) << 8); 2635 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7e94)); 2636 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7e98)); 2637 base3 = GET_SMSTATE(u32, smstate, 0x7e9c); 2638 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_TR); 2639 2640 dt.size = GET_SMSTATE(u32, smstate, 0x7e84); 2641 dt.address = GET_SMSTATE(u64, smstate, 0x7e88); 2642 ctxt->ops->set_idt(ctxt, &dt); 2643 2644 selector = GET_SMSTATE(u32, smstate, 0x7e70); 2645 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7e72) << 8); 2646 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7e74)); 2647 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7e78)); 2648 base3 = GET_SMSTATE(u32, smstate, 0x7e7c); 2649 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_LDTR); 2650 2651 dt.size = GET_SMSTATE(u32, smstate, 0x7e64); 2652 dt.address = GET_SMSTATE(u64, smstate, 0x7e68); 2653 ctxt->ops->set_gdt(ctxt, &dt); 2654 2655 r = rsm_enter_protected_mode(ctxt, cr0, cr3, cr4); 2656 if (r != X86EMUL_CONTINUE) 2657 return r; 2658 2659 for (i = 0; i < 6; i++) { 2660 r = rsm_load_seg_64(ctxt, smstate, i); 2661 if (r != X86EMUL_CONTINUE) 2662 return r; 2663 } 2664 2665 return X86EMUL_CONTINUE; 2666} 2667#endif 2668 2669static int em_rsm(struct x86_emulate_ctxt *ctxt) 2670{ 2671 unsigned long cr0, cr4, efer; 2672 char buf[512]; 2673 u64 smbase; 2674 int ret; 2675 2676 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_MASK) == 0) 2677 return emulate_ud(ctxt); 2678 2679 smbase = ctxt->ops->get_smbase(ctxt); 2680 2681 ret = ctxt->ops->read_phys(ctxt, smbase + 0xfe00, buf, sizeof(buf)); 2682 if (ret != X86EMUL_CONTINUE) 2683 return X86EMUL_UNHANDLEABLE; 2684 2685 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_INSIDE_NMI_MASK) == 0) 2686 ctxt->ops->set_nmi_mask(ctxt, false); 2687 2688 ctxt->ops->set_hflags(ctxt, ctxt->ops->get_hflags(ctxt) & 2689 ~(X86EMUL_SMM_INSIDE_NMI_MASK | X86EMUL_SMM_MASK)); 2690 2691 /* 2692 * Get back to real mode, to prepare a safe state in which to load 2693 * CR0/CR3/CR4/EFER. It's all a bit more complicated if the vCPU 2694 * supports long mode. 2695 */ 2696 if (emulator_has_longmode(ctxt)) { 2697 struct desc_struct cs_desc; 2698 2699 /* Zero CR4.PCIDE before CR0.PG. */ 2700 cr4 = ctxt->ops->get_cr(ctxt, 4); 2701 if (cr4 & X86_CR4_PCIDE) 2702 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE); 2703 2704 /* A 32-bit code segment is required to clear EFER.LMA. */ 2705 memset(&cs_desc, 0, sizeof(cs_desc)); 2706 cs_desc.type = 0xb; 2707 cs_desc.s = cs_desc.g = cs_desc.p = 1; 2708 ctxt->ops->set_segment(ctxt, 0, &cs_desc, 0, VCPU_SREG_CS); 2709 } 2710 2711 /* For the 64-bit case, this will clear EFER.LMA. */ 2712 cr0 = ctxt->ops->get_cr(ctxt, 0); 2713 if (cr0 & X86_CR0_PE) 2714 ctxt->ops->set_cr(ctxt, 0, cr0 & ~(X86_CR0_PG | X86_CR0_PE)); 2715 2716 if (emulator_has_longmode(ctxt)) { 2717 /* Clear CR4.PAE before clearing EFER.LME. */ 2718 cr4 = ctxt->ops->get_cr(ctxt, 4); 2719 if (cr4 & X86_CR4_PAE) 2720 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PAE); 2721 2722 /* And finally go back to 32-bit mode. */ 2723 efer = 0; 2724 ctxt->ops->set_msr(ctxt, MSR_EFER, efer); 2725 } 2726 2727 /* 2728 * Give pre_leave_smm() a chance to make ISA-specific changes to the 2729 * vCPU state (e.g. enter guest mode) before loading state from the SMM 2730 * state-save area. 2731 */ 2732 if (ctxt->ops->pre_leave_smm(ctxt, buf)) 2733 return X86EMUL_UNHANDLEABLE; 2734 2735#ifdef CONFIG_X86_64 2736 if (emulator_has_longmode(ctxt)) 2737 ret = rsm_load_state_64(ctxt, buf); 2738 else 2739#endif 2740 ret = rsm_load_state_32(ctxt, buf); 2741 2742 if (ret != X86EMUL_CONTINUE) { 2743 /* FIXME: should triple fault */ 2744 return X86EMUL_UNHANDLEABLE; 2745 } 2746 2747 ctxt->ops->post_leave_smm(ctxt); 2748 2749 return X86EMUL_CONTINUE; 2750} 2751 2752static void 2753setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, 2754 struct desc_struct *cs, struct desc_struct *ss) 2755{ 2756 cs->l = 0; /* will be adjusted later */ 2757 set_desc_base(cs, 0); /* flat segment */ 2758 cs->g = 1; /* 4kb granularity */ 2759 set_desc_limit(cs, 0xfffff); /* 4GB limit */ 2760 cs->type = 0x0b; /* Read, Execute, Accessed */ 2761 cs->s = 1; 2762 cs->dpl = 0; /* will be adjusted later */ 2763 cs->p = 1; 2764 cs->d = 1; 2765 cs->avl = 0; 2766 2767 set_desc_base(ss, 0); /* flat segment */ 2768 set_desc_limit(ss, 0xfffff); /* 4GB limit */ 2769 ss->g = 1; /* 4kb granularity */ 2770 ss->s = 1; 2771 ss->type = 0x03; /* Read/Write, Accessed */ 2772 ss->d = 1; /* 32bit stack segment */ 2773 ss->dpl = 0; 2774 ss->p = 1; 2775 ss->l = 0; 2776 ss->avl = 0; 2777} 2778 2779static bool vendor_intel(struct x86_emulate_ctxt *ctxt) 2780{ 2781 u32 eax, ebx, ecx, edx; 2782 2783 eax = ecx = 0; 2784 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true); 2785 return is_guest_vendor_intel(ebx, ecx, edx); 2786} 2787 2788static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) 2789{ 2790 const struct x86_emulate_ops *ops = ctxt->ops; 2791 u32 eax, ebx, ecx, edx; 2792 2793 /* 2794 * syscall should always be enabled in longmode - so only become 2795 * vendor specific (cpuid) if other modes are active... 2796 */ 2797 if (ctxt->mode == X86EMUL_MODE_PROT64) 2798 return true; 2799 2800 eax = 0x00000000; 2801 ecx = 0x00000000; 2802 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true); 2803 /* 2804 * remark: Intel CPUs only support "syscall" in 64bit longmode. Also a 2805 * 64bit guest with a 32bit compat-app running will #UD !! While this 2806 * behaviour can be fixed (by emulating) into AMD response - CPUs of 2807 * AMD can't behave like Intel. 2808 */ 2809 if (is_guest_vendor_intel(ebx, ecx, edx)) 2810 return false; 2811 2812 if (is_guest_vendor_amd(ebx, ecx, edx) || 2813 is_guest_vendor_hygon(ebx, ecx, edx)) 2814 return true; 2815 2816 /* 2817 * default: (not Intel, not AMD, not Hygon), apply Intel's 2818 * stricter rules... 2819 */ 2820 return false; 2821} 2822 2823static int em_syscall(struct x86_emulate_ctxt *ctxt) 2824{ 2825 const struct x86_emulate_ops *ops = ctxt->ops; 2826 struct desc_struct cs, ss; 2827 u64 msr_data; 2828 u16 cs_sel, ss_sel; 2829 u64 efer = 0; 2830 2831 /* syscall is not available in real mode */ 2832 if (ctxt->mode == X86EMUL_MODE_REAL || 2833 ctxt->mode == X86EMUL_MODE_VM86) 2834 return emulate_ud(ctxt); 2835 2836 if (!(em_syscall_is_enabled(ctxt))) 2837 return emulate_ud(ctxt); 2838 2839 ops->get_msr(ctxt, MSR_EFER, &efer); 2840 if (!(efer & EFER_SCE)) 2841 return emulate_ud(ctxt); 2842 2843 setup_syscalls_segments(ctxt, &cs, &ss); 2844 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2845 msr_data >>= 32; 2846 cs_sel = (u16)(msr_data & 0xfffc); 2847 ss_sel = (u16)(msr_data + 8); 2848 2849 if (efer & EFER_LMA) { 2850 cs.d = 0; 2851 cs.l = 1; 2852 } 2853 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2854 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2855 2856 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip; 2857 if (efer & EFER_LMA) { 2858#ifdef CONFIG_X86_64 2859 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags; 2860 2861 ops->get_msr(ctxt, 2862 ctxt->mode == X86EMUL_MODE_PROT64 ? 2863 MSR_LSTAR : MSR_CSTAR, &msr_data); 2864 ctxt->_eip = msr_data; 2865 2866 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); 2867 ctxt->eflags &= ~msr_data; 2868 ctxt->eflags |= X86_EFLAGS_FIXED; 2869#endif 2870 } else { 2871 /* legacy mode */ 2872 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2873 ctxt->_eip = (u32)msr_data; 2874 2875 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2876 } 2877 2878 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 2879 return X86EMUL_CONTINUE; 2880} 2881 2882static int em_sysenter(struct x86_emulate_ctxt *ctxt) 2883{ 2884 const struct x86_emulate_ops *ops = ctxt->ops; 2885 struct desc_struct cs, ss; 2886 u64 msr_data; 2887 u16 cs_sel, ss_sel; 2888 u64 efer = 0; 2889 2890 ops->get_msr(ctxt, MSR_EFER, &efer); 2891 /* inject #GP if in real mode */ 2892 if (ctxt->mode == X86EMUL_MODE_REAL) 2893 return emulate_gp(ctxt, 0); 2894 2895 /* 2896 * Not recognized on AMD in compat mode (but is recognized in legacy 2897 * mode). 2898 */ 2899 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA) 2900 && !vendor_intel(ctxt)) 2901 return emulate_ud(ctxt); 2902 2903 /* sysenter/sysexit have not been tested in 64bit mode. */ 2904 if (ctxt->mode == X86EMUL_MODE_PROT64) 2905 return X86EMUL_UNHANDLEABLE; 2906 2907 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2908 if ((msr_data & 0xfffc) == 0x0) 2909 return emulate_gp(ctxt, 0); 2910 2911 setup_syscalls_segments(ctxt, &cs, &ss); 2912 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2913 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK; 2914 ss_sel = cs_sel + 8; 2915 if (efer & EFER_LMA) { 2916 cs.d = 0; 2917 cs.l = 1; 2918 } 2919 2920 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2921 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2922 2923 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); 2924 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data; 2925 2926 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); 2927 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data : 2928 (u32)msr_data; 2929 if (efer & EFER_LMA) 2930 ctxt->mode = X86EMUL_MODE_PROT64; 2931 2932 return X86EMUL_CONTINUE; 2933} 2934 2935static int em_sysexit(struct x86_emulate_ctxt *ctxt) 2936{ 2937 const struct x86_emulate_ops *ops = ctxt->ops; 2938 struct desc_struct cs, ss; 2939 u64 msr_data, rcx, rdx; 2940 int usermode; 2941 u16 cs_sel = 0, ss_sel = 0; 2942 2943 /* inject #GP if in real mode or Virtual 8086 mode */ 2944 if (ctxt->mode == X86EMUL_MODE_REAL || 2945 ctxt->mode == X86EMUL_MODE_VM86) 2946 return emulate_gp(ctxt, 0); 2947 2948 setup_syscalls_segments(ctxt, &cs, &ss); 2949 2950 if ((ctxt->rex_prefix & 0x8) != 0x0) 2951 usermode = X86EMUL_MODE_PROT64; 2952 else 2953 usermode = X86EMUL_MODE_PROT32; 2954 2955 rcx = reg_read(ctxt, VCPU_REGS_RCX); 2956 rdx = reg_read(ctxt, VCPU_REGS_RDX); 2957 2958 cs.dpl = 3; 2959 ss.dpl = 3; 2960 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2961 switch (usermode) { 2962 case X86EMUL_MODE_PROT32: 2963 cs_sel = (u16)(msr_data + 16); 2964 if ((msr_data & 0xfffc) == 0x0) 2965 return emulate_gp(ctxt, 0); 2966 ss_sel = (u16)(msr_data + 24); 2967 rcx = (u32)rcx; 2968 rdx = (u32)rdx; 2969 break; 2970 case X86EMUL_MODE_PROT64: 2971 cs_sel = (u16)(msr_data + 32); 2972 if (msr_data == 0x0) 2973 return emulate_gp(ctxt, 0); 2974 ss_sel = cs_sel + 8; 2975 cs.d = 0; 2976 cs.l = 1; 2977 if (emul_is_noncanonical_address(rcx, ctxt) || 2978 emul_is_noncanonical_address(rdx, ctxt)) 2979 return emulate_gp(ctxt, 0); 2980 break; 2981 } 2982 cs_sel |= SEGMENT_RPL_MASK; 2983 ss_sel |= SEGMENT_RPL_MASK; 2984 2985 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2986 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2987 2988 ctxt->_eip = rdx; 2989 ctxt->mode = usermode; 2990 *reg_write(ctxt, VCPU_REGS_RSP) = rcx; 2991 2992 return X86EMUL_CONTINUE; 2993} 2994 2995static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) 2996{ 2997 int iopl; 2998 if (ctxt->mode == X86EMUL_MODE_REAL) 2999 return false; 3000 if (ctxt->mode == X86EMUL_MODE_VM86) 3001 return true; 3002 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 3003 return ctxt->ops->cpl(ctxt) > iopl; 3004} 3005 3006#define VMWARE_PORT_VMPORT (0x5658) 3007#define VMWARE_PORT_VMRPC (0x5659) 3008 3009static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, 3010 u16 port, u16 len) 3011{ 3012 const struct x86_emulate_ops *ops = ctxt->ops; 3013 struct desc_struct tr_seg; 3014 u32 base3; 3015 int r; 3016 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; 3017 unsigned mask = (1 << len) - 1; 3018 unsigned long base; 3019 3020 /* 3021 * VMware allows access to these ports even if denied 3022 * by TSS I/O permission bitmap. Mimic behavior. 3023 */ 3024 if (enable_vmware_backdoor && 3025 ((port == VMWARE_PORT_VMPORT) || (port == VMWARE_PORT_VMRPC))) 3026 return true; 3027 3028 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); 3029 if (!tr_seg.p) 3030 return false; 3031 if (desc_limit_scaled(&tr_seg) < 103) 3032 return false; 3033 base = get_desc_base(&tr_seg); 3034#ifdef CONFIG_X86_64 3035 base |= ((u64)base3) << 32; 3036#endif 3037 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL, true); 3038 if (r != X86EMUL_CONTINUE) 3039 return false; 3040 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) 3041 return false; 3042 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL, true); 3043 if (r != X86EMUL_CONTINUE) 3044 return false; 3045 if ((perm >> bit_idx) & mask) 3046 return false; 3047 return true; 3048} 3049 3050static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, 3051 u16 port, u16 len) 3052{ 3053 if (ctxt->perm_ok) 3054 return true; 3055 3056 if (emulator_bad_iopl(ctxt)) 3057 if (!emulator_io_port_access_allowed(ctxt, port, len)) 3058 return false; 3059 3060 ctxt->perm_ok = true; 3061 3062 return true; 3063} 3064 3065static void string_registers_quirk(struct x86_emulate_ctxt *ctxt) 3066{ 3067 /* 3068 * Intel CPUs mask the counter and pointers in quite strange 3069 * manner when ECX is zero due to REP-string optimizations. 3070 */ 3071#ifdef CONFIG_X86_64 3072 if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt)) 3073 return; 3074 3075 *reg_write(ctxt, VCPU_REGS_RCX) = 0; 3076 3077 switch (ctxt->b) { 3078 case 0xa4: /* movsb */ 3079 case 0xa5: /* movsd/w */ 3080 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1; 3081 fallthrough; 3082 case 0xaa: /* stosb */ 3083 case 0xab: /* stosd/w */ 3084 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1; 3085 } 3086#endif 3087} 3088 3089static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, 3090 struct tss_segment_16 *tss) 3091{ 3092 tss->ip = ctxt->_eip; 3093 tss->flag = ctxt->eflags; 3094 tss->ax = reg_read(ctxt, VCPU_REGS_RAX); 3095 tss->cx = reg_read(ctxt, VCPU_REGS_RCX); 3096 tss->dx = reg_read(ctxt, VCPU_REGS_RDX); 3097 tss->bx = reg_read(ctxt, VCPU_REGS_RBX); 3098 tss->sp = reg_read(ctxt, VCPU_REGS_RSP); 3099 tss->bp = reg_read(ctxt, VCPU_REGS_RBP); 3100 tss->si = reg_read(ctxt, VCPU_REGS_RSI); 3101 tss->di = reg_read(ctxt, VCPU_REGS_RDI); 3102 3103 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 3104 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 3105 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 3106 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 3107 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); 3108} 3109 3110static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, 3111 struct tss_segment_16 *tss) 3112{ 3113 int ret; 3114 u8 cpl; 3115 3116 ctxt->_eip = tss->ip; 3117 ctxt->eflags = tss->flag | 2; 3118 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax; 3119 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx; 3120 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx; 3121 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx; 3122 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp; 3123 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp; 3124 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si; 3125 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di; 3126 3127 /* 3128 * SDM says that segment selectors are loaded before segment 3129 * descriptors 3130 */ 3131 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); 3132 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 3133 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 3134 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 3135 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 3136 3137 cpl = tss->cs & 3; 3138 3139 /* 3140 * Now load segment descriptors. If fault happens at this stage 3141 * it is handled in a context of new task 3142 */ 3143 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, 3144 X86_TRANSFER_TASK_SWITCH, NULL); 3145 if (ret != X86EMUL_CONTINUE) 3146 return ret; 3147 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 3148 X86_TRANSFER_TASK_SWITCH, NULL); 3149 if (ret != X86EMUL_CONTINUE) 3150 return ret; 3151 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 3152 X86_TRANSFER_TASK_SWITCH, NULL); 3153 if (ret != X86EMUL_CONTINUE) 3154 return ret; 3155 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 3156 X86_TRANSFER_TASK_SWITCH, NULL); 3157 if (ret != X86EMUL_CONTINUE) 3158 return ret; 3159 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 3160 X86_TRANSFER_TASK_SWITCH, NULL); 3161 if (ret != X86EMUL_CONTINUE) 3162 return ret; 3163 3164 return X86EMUL_CONTINUE; 3165} 3166 3167static int task_switch_16(struct x86_emulate_ctxt *ctxt, 3168 u16 tss_selector, u16 old_tss_sel, 3169 ulong old_tss_base, struct desc_struct *new_desc) 3170{ 3171 struct tss_segment_16 tss_seg; 3172 int ret; 3173 u32 new_tss_base = get_desc_base(new_desc); 3174 3175 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 3176 if (ret != X86EMUL_CONTINUE) 3177 return ret; 3178 3179 save_state_to_tss16(ctxt, &tss_seg); 3180 3181 ret = linear_write_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 3182 if (ret != X86EMUL_CONTINUE) 3183 return ret; 3184 3185 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg)); 3186 if (ret != X86EMUL_CONTINUE) 3187 return ret; 3188 3189 if (old_tss_sel != 0xffff) { 3190 tss_seg.prev_task_link = old_tss_sel; 3191 3192 ret = linear_write_system(ctxt, new_tss_base, 3193 &tss_seg.prev_task_link, 3194 sizeof(tss_seg.prev_task_link)); 3195 if (ret != X86EMUL_CONTINUE) 3196 return ret; 3197 } 3198 3199 return load_state_from_tss16(ctxt, &tss_seg); 3200} 3201 3202static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, 3203 struct tss_segment_32 *tss) 3204{ 3205 /* CR3 and ldt selector are not saved intentionally */ 3206 tss->eip = ctxt->_eip; 3207 tss->eflags = ctxt->eflags; 3208 tss->eax = reg_read(ctxt, VCPU_REGS_RAX); 3209 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX); 3210 tss->edx = reg_read(ctxt, VCPU_REGS_RDX); 3211 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX); 3212 tss->esp = reg_read(ctxt, VCPU_REGS_RSP); 3213 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP); 3214 tss->esi = reg_read(ctxt, VCPU_REGS_RSI); 3215 tss->edi = reg_read(ctxt, VCPU_REGS_RDI); 3216 3217 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 3218 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 3219 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 3220 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 3221 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); 3222 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); 3223} 3224 3225static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, 3226 struct tss_segment_32 *tss) 3227{ 3228 int ret; 3229 u8 cpl; 3230 3231 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) 3232 return emulate_gp(ctxt, 0); 3233 ctxt->_eip = tss->eip; 3234 ctxt->eflags = tss->eflags | 2; 3235 3236 /* General purpose registers */ 3237 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax; 3238 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx; 3239 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx; 3240 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx; 3241 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp; 3242 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp; 3243 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi; 3244 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi; 3245 3246 /* 3247 * SDM says that segment selectors are loaded before segment 3248 * descriptors. This is important because CPL checks will 3249 * use CS.RPL. 3250 */ 3251 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); 3252 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 3253 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 3254 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 3255 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 3256 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); 3257 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); 3258 3259 /* 3260 * If we're switching between Protected Mode and VM86, we need to make 3261 * sure to update the mode before loading the segment descriptors so 3262 * that the selectors are interpreted correctly. 3263 */ 3264 if (ctxt->eflags & X86_EFLAGS_VM) { 3265 ctxt->mode = X86EMUL_MODE_VM86; 3266 cpl = 3; 3267 } else { 3268 ctxt->mode = X86EMUL_MODE_PROT32; 3269 cpl = tss->cs & 3; 3270 } 3271 3272 /* 3273 * Now load segment descriptors. If fault happenes at this stage 3274 * it is handled in a context of new task 3275 */ 3276 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, 3277 cpl, X86_TRANSFER_TASK_SWITCH, NULL); 3278 if (ret != X86EMUL_CONTINUE) 3279 return ret; 3280 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 3281 X86_TRANSFER_TASK_SWITCH, NULL); 3282 if (ret != X86EMUL_CONTINUE) 3283 return ret; 3284 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 3285 X86_TRANSFER_TASK_SWITCH, NULL); 3286 if (ret != X86EMUL_CONTINUE) 3287 return ret; 3288 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 3289 X86_TRANSFER_TASK_SWITCH, NULL); 3290 if (ret != X86EMUL_CONTINUE) 3291 return ret; 3292 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 3293 X86_TRANSFER_TASK_SWITCH, NULL); 3294 if (ret != X86EMUL_CONTINUE) 3295 return ret; 3296 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, 3297 X86_TRANSFER_TASK_SWITCH, NULL); 3298 if (ret != X86EMUL_CONTINUE) 3299 return ret; 3300 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, 3301 X86_TRANSFER_TASK_SWITCH, NULL); 3302 3303 return ret; 3304} 3305 3306static int task_switch_32(struct x86_emulate_ctxt *ctxt, 3307 u16 tss_selector, u16 old_tss_sel, 3308 ulong old_tss_base, struct desc_struct *new_desc) 3309{ 3310 struct tss_segment_32 tss_seg; 3311 int ret; 3312 u32 new_tss_base = get_desc_base(new_desc); 3313 u32 eip_offset = offsetof(struct tss_segment_32, eip); 3314 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector); 3315 3316 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 3317 if (ret != X86EMUL_CONTINUE) 3318 return ret; 3319 3320 save_state_to_tss32(ctxt, &tss_seg); 3321 3322 /* Only GP registers and segment selectors are saved */ 3323 ret = linear_write_system(ctxt, old_tss_base + eip_offset, &tss_seg.eip, 3324 ldt_sel_offset - eip_offset); 3325 if (ret != X86EMUL_CONTINUE) 3326 return ret; 3327 3328 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg)); 3329 if (ret != X86EMUL_CONTINUE) 3330 return ret; 3331 3332 if (old_tss_sel != 0xffff) { 3333 tss_seg.prev_task_link = old_tss_sel; 3334 3335 ret = linear_write_system(ctxt, new_tss_base, 3336 &tss_seg.prev_task_link, 3337 sizeof(tss_seg.prev_task_link)); 3338 if (ret != X86EMUL_CONTINUE) 3339 return ret; 3340 } 3341 3342 return load_state_from_tss32(ctxt, &tss_seg); 3343} 3344 3345static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, 3346 u16 tss_selector, int idt_index, int reason, 3347 bool has_error_code, u32 error_code) 3348{ 3349 const struct x86_emulate_ops *ops = ctxt->ops; 3350 struct desc_struct curr_tss_desc, next_tss_desc; 3351 int ret; 3352 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); 3353 ulong old_tss_base = 3354 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); 3355 u32 desc_limit; 3356 ulong desc_addr, dr7; 3357 3358 /* FIXME: old_tss_base == ~0 ? */ 3359 3360 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr); 3361 if (ret != X86EMUL_CONTINUE) 3362 return ret; 3363 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr); 3364 if (ret != X86EMUL_CONTINUE) 3365 return ret; 3366 3367 /* FIXME: check that next_tss_desc is tss */ 3368 3369 /* 3370 * Check privileges. The three cases are task switch caused by... 3371 * 3372 * 1. jmp/call/int to task gate: Check against DPL of the task gate 3373 * 2. Exception/IRQ/iret: No check is performed 3374 * 3. jmp/call to TSS/task-gate: No check is performed since the 3375 * hardware checks it before exiting. 3376 */ 3377 if (reason == TASK_SWITCH_GATE) { 3378 if (idt_index != -1) { 3379 /* Software interrupts */ 3380 struct desc_struct task_gate_desc; 3381 int dpl; 3382 3383 ret = read_interrupt_descriptor(ctxt, idt_index, 3384 &task_gate_desc); 3385 if (ret != X86EMUL_CONTINUE) 3386 return ret; 3387 3388 dpl = task_gate_desc.dpl; 3389 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) 3390 return emulate_gp(ctxt, (idt_index << 3) | 0x2); 3391 } 3392 } 3393 3394 desc_limit = desc_limit_scaled(&next_tss_desc); 3395 if (!next_tss_desc.p || 3396 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || 3397 desc_limit < 0x2b)) { 3398 return emulate_ts(ctxt, tss_selector & 0xfffc); 3399 } 3400 3401 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { 3402 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ 3403 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); 3404 } 3405 3406 if (reason == TASK_SWITCH_IRET) 3407 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; 3408 3409 /* set back link to prev task only if NT bit is set in eflags 3410 note that old_tss_sel is not used after this point */ 3411 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) 3412 old_tss_sel = 0xffff; 3413 3414 if (next_tss_desc.type & 8) 3415 ret = task_switch_32(ctxt, tss_selector, old_tss_sel, 3416 old_tss_base, &next_tss_desc); 3417 else 3418 ret = task_switch_16(ctxt, tss_selector, old_tss_sel, 3419 old_tss_base, &next_tss_desc); 3420 if (ret != X86EMUL_CONTINUE) 3421 return ret; 3422 3423 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) 3424 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; 3425 3426 if (reason != TASK_SWITCH_IRET) { 3427 next_tss_desc.type |= (1 << 1); /* set busy flag */ 3428 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); 3429 } 3430 3431 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); 3432 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); 3433 3434 if (has_error_code) { 3435 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; 3436 ctxt->lock_prefix = 0; 3437 ctxt->src.val = (unsigned long) error_code; 3438 ret = em_push(ctxt); 3439 } 3440 3441 ops->get_dr(ctxt, 7, &dr7); 3442 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN)); 3443 3444 return ret; 3445} 3446 3447int emulator_task_switch(struct x86_emulate_ctxt *ctxt, 3448 u16 tss_selector, int idt_index, int reason, 3449 bool has_error_code, u32 error_code) 3450{ 3451 int rc; 3452 3453 invalidate_registers(ctxt); 3454 ctxt->_eip = ctxt->eip; 3455 ctxt->dst.type = OP_NONE; 3456 3457 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, 3458 has_error_code, error_code); 3459 3460 if (rc == X86EMUL_CONTINUE) { 3461 ctxt->eip = ctxt->_eip; 3462 writeback_registers(ctxt); 3463 } 3464 3465 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 3466} 3467 3468static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg, 3469 struct operand *op) 3470{ 3471 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count; 3472 3473 register_address_increment(ctxt, reg, df * op->bytes); 3474 op->addr.mem.ea = register_address(ctxt, reg); 3475} 3476 3477static int em_das(struct x86_emulate_ctxt *ctxt) 3478{ 3479 u8 al, old_al; 3480 bool af, cf, old_cf; 3481 3482 cf = ctxt->eflags & X86_EFLAGS_CF; 3483 al = ctxt->dst.val; 3484 3485 old_al = al; 3486 old_cf = cf; 3487 cf = false; 3488 af = ctxt->eflags & X86_EFLAGS_AF; 3489 if ((al & 0x0f) > 9 || af) { 3490 al -= 6; 3491 cf = old_cf | (al >= 250); 3492 af = true; 3493 } else { 3494 af = false; 3495 } 3496 if (old_al > 0x99 || old_cf) { 3497 al -= 0x60; 3498 cf = true; 3499 } 3500 3501 ctxt->dst.val = al; 3502 /* Set PF, ZF, SF */ 3503 ctxt->src.type = OP_IMM; 3504 ctxt->src.val = 0; 3505 ctxt->src.bytes = 1; 3506 fastop(ctxt, em_or); 3507 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); 3508 if (cf) 3509 ctxt->eflags |= X86_EFLAGS_CF; 3510 if (af) 3511 ctxt->eflags |= X86_EFLAGS_AF; 3512 return X86EMUL_CONTINUE; 3513} 3514 3515static int em_aam(struct x86_emulate_ctxt *ctxt) 3516{ 3517 u8 al, ah; 3518 3519 if (ctxt->src.val == 0) 3520 return emulate_de(ctxt); 3521 3522 al = ctxt->dst.val & 0xff; 3523 ah = al / ctxt->src.val; 3524 al %= ctxt->src.val; 3525 3526 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8); 3527 3528 /* Set PF, ZF, SF */ 3529 ctxt->src.type = OP_IMM; 3530 ctxt->src.val = 0; 3531 ctxt->src.bytes = 1; 3532 fastop(ctxt, em_or); 3533 3534 return X86EMUL_CONTINUE; 3535} 3536 3537static int em_aad(struct x86_emulate_ctxt *ctxt) 3538{ 3539 u8 al = ctxt->dst.val & 0xff; 3540 u8 ah = (ctxt->dst.val >> 8) & 0xff; 3541 3542 al = (al + (ah * ctxt->src.val)) & 0xff; 3543 3544 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al; 3545 3546 /* Set PF, ZF, SF */ 3547 ctxt->src.type = OP_IMM; 3548 ctxt->src.val = 0; 3549 ctxt->src.bytes = 1; 3550 fastop(ctxt, em_or); 3551 3552 return X86EMUL_CONTINUE; 3553} 3554 3555static int em_call(struct x86_emulate_ctxt *ctxt) 3556{ 3557 int rc; 3558 long rel = ctxt->src.val; 3559 3560 ctxt->src.val = (unsigned long)ctxt->_eip; 3561 rc = jmp_rel(ctxt, rel); 3562 if (rc != X86EMUL_CONTINUE) 3563 return rc; 3564 return em_push(ctxt); 3565} 3566 3567static int em_call_far(struct x86_emulate_ctxt *ctxt) 3568{ 3569 u16 sel, old_cs; 3570 ulong old_eip; 3571 int rc; 3572 struct desc_struct old_desc, new_desc; 3573 const struct x86_emulate_ops *ops = ctxt->ops; 3574 int cpl = ctxt->ops->cpl(ctxt); 3575 enum x86emul_mode prev_mode = ctxt->mode; 3576 3577 old_eip = ctxt->_eip; 3578 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS); 3579 3580 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 3581 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 3582 X86_TRANSFER_CALL_JMP, &new_desc); 3583 if (rc != X86EMUL_CONTINUE) 3584 return rc; 3585 3586 rc = assign_eip_far(ctxt, ctxt->src.val); 3587 if (rc != X86EMUL_CONTINUE) 3588 goto fail; 3589 3590 ctxt->src.val = old_cs; 3591 rc = em_push(ctxt); 3592 if (rc != X86EMUL_CONTINUE) 3593 goto fail; 3594 3595 ctxt->src.val = old_eip; 3596 rc = em_push(ctxt); 3597 /* If we failed, we tainted the memory, but the very least we should 3598 restore cs */ 3599 if (rc != X86EMUL_CONTINUE) { 3600 pr_warn_once("faulting far call emulation tainted memory\n"); 3601 goto fail; 3602 } 3603 return rc; 3604fail: 3605 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS); 3606 ctxt->mode = prev_mode; 3607 return rc; 3608 3609} 3610 3611static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) 3612{ 3613 int rc; 3614 unsigned long eip; 3615 3616 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 3617 if (rc != X86EMUL_CONTINUE) 3618 return rc; 3619 rc = assign_eip_near(ctxt, eip); 3620 if (rc != X86EMUL_CONTINUE) 3621 return rc; 3622 rsp_increment(ctxt, ctxt->src.val); 3623 return X86EMUL_CONTINUE; 3624} 3625 3626static int em_xchg(struct x86_emulate_ctxt *ctxt) 3627{ 3628 /* Write back the register source. */ 3629 ctxt->src.val = ctxt->dst.val; 3630 write_register_operand(&ctxt->src); 3631 3632 /* Write back the memory destination with implicit LOCK prefix. */ 3633 ctxt->dst.val = ctxt->src.orig_val; 3634 ctxt->lock_prefix = 1; 3635 return X86EMUL_CONTINUE; 3636} 3637 3638static int em_imul_3op(struct x86_emulate_ctxt *ctxt) 3639{ 3640 ctxt->dst.val = ctxt->src2.val; 3641 return fastop(ctxt, em_imul); 3642} 3643 3644static int em_cwd(struct x86_emulate_ctxt *ctxt) 3645{ 3646 ctxt->dst.type = OP_REG; 3647 ctxt->dst.bytes = ctxt->src.bytes; 3648 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 3649 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); 3650 3651 return X86EMUL_CONTINUE; 3652} 3653 3654static int em_rdpid(struct x86_emulate_ctxt *ctxt) 3655{ 3656 u64 tsc_aux = 0; 3657 3658 if (!ctxt->ops->guest_has_rdpid(ctxt)) 3659 return emulate_ud(ctxt); 3660 3661 ctxt->ops->get_msr(ctxt, MSR_TSC_AUX, &tsc_aux); 3662 ctxt->dst.val = tsc_aux; 3663 return X86EMUL_CONTINUE; 3664} 3665 3666static int em_rdtsc(struct x86_emulate_ctxt *ctxt) 3667{ 3668 u64 tsc = 0; 3669 3670 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); 3671 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc; 3672 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32; 3673 return X86EMUL_CONTINUE; 3674} 3675 3676static int em_rdpmc(struct x86_emulate_ctxt *ctxt) 3677{ 3678 u64 pmc; 3679 3680 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc)) 3681 return emulate_gp(ctxt, 0); 3682 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc; 3683 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32; 3684 return X86EMUL_CONTINUE; 3685} 3686 3687static int em_mov(struct x86_emulate_ctxt *ctxt) 3688{ 3689 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr)); 3690 return X86EMUL_CONTINUE; 3691} 3692 3693static int em_movbe(struct x86_emulate_ctxt *ctxt) 3694{ 3695 u16 tmp; 3696 3697 if (!ctxt->ops->guest_has_movbe(ctxt)) 3698 return emulate_ud(ctxt); 3699 3700 switch (ctxt->op_bytes) { 3701 case 2: 3702 /* 3703 * From MOVBE definition: "...When the operand size is 16 bits, 3704 * the upper word of the destination register remains unchanged 3705 * ..." 3706 * 3707 * Both casting ->valptr and ->val to u16 breaks strict aliasing 3708 * rules so we have to do the operation almost per hand. 3709 */ 3710 tmp = (u16)ctxt->src.val; 3711 ctxt->dst.val &= ~0xffffUL; 3712 ctxt->dst.val |= (unsigned long)swab16(tmp); 3713 break; 3714 case 4: 3715 ctxt->dst.val = swab32((u32)ctxt->src.val); 3716 break; 3717 case 8: 3718 ctxt->dst.val = swab64(ctxt->src.val); 3719 break; 3720 default: 3721 BUG(); 3722 } 3723 return X86EMUL_CONTINUE; 3724} 3725 3726static int em_cr_write(struct x86_emulate_ctxt *ctxt) 3727{ 3728 int cr_num = ctxt->modrm_reg; 3729 int r; 3730 3731 if (ctxt->ops->set_cr(ctxt, cr_num, ctxt->src.val)) 3732 return emulate_gp(ctxt, 0); 3733 3734 /* Disable writeback. */ 3735 ctxt->dst.type = OP_NONE; 3736 3737 if (cr_num == 0) { 3738 /* 3739 * CR0 write might have updated CR0.PE and/or CR0.PG 3740 * which can affect the cpu's execution mode. 3741 */ 3742 r = emulator_recalc_and_set_mode(ctxt); 3743 if (r != X86EMUL_CONTINUE) 3744 return r; 3745 } 3746 3747 return X86EMUL_CONTINUE; 3748} 3749 3750static int em_dr_write(struct x86_emulate_ctxt *ctxt) 3751{ 3752 unsigned long val; 3753 3754 if (ctxt->mode == X86EMUL_MODE_PROT64) 3755 val = ctxt->src.val & ~0ULL; 3756 else 3757 val = ctxt->src.val & ~0U; 3758 3759 /* #UD condition is already handled. */ 3760 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) 3761 return emulate_gp(ctxt, 0); 3762 3763 /* Disable writeback. */ 3764 ctxt->dst.type = OP_NONE; 3765 return X86EMUL_CONTINUE; 3766} 3767 3768static int em_wrmsr(struct x86_emulate_ctxt *ctxt) 3769{ 3770 u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX); 3771 u64 msr_data; 3772 int r; 3773 3774 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX) 3775 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32); 3776 r = ctxt->ops->set_msr(ctxt, msr_index, msr_data); 3777 3778 if (r == X86EMUL_IO_NEEDED) 3779 return r; 3780 3781 if (r > 0) 3782 return emulate_gp(ctxt, 0); 3783 3784 return r < 0 ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; 3785} 3786 3787static int em_rdmsr(struct x86_emulate_ctxt *ctxt) 3788{ 3789 u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX); 3790 u64 msr_data; 3791 int r; 3792 3793 r = ctxt->ops->get_msr(ctxt, msr_index, &msr_data); 3794 3795 if (r == X86EMUL_IO_NEEDED) 3796 return r; 3797 3798 if (r) 3799 return emulate_gp(ctxt, 0); 3800 3801 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data; 3802 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32; 3803 return X86EMUL_CONTINUE; 3804} 3805 3806static int em_store_sreg(struct x86_emulate_ctxt *ctxt, int segment) 3807{ 3808 if (segment > VCPU_SREG_GS && 3809 (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3810 ctxt->ops->cpl(ctxt) > 0) 3811 return emulate_gp(ctxt, 0); 3812 3813 ctxt->dst.val = get_segment_selector(ctxt, segment); 3814 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM) 3815 ctxt->dst.bytes = 2; 3816 return X86EMUL_CONTINUE; 3817} 3818 3819static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) 3820{ 3821 if (ctxt->modrm_reg > VCPU_SREG_GS) 3822 return emulate_ud(ctxt); 3823 3824 return em_store_sreg(ctxt, ctxt->modrm_reg); 3825} 3826 3827static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) 3828{ 3829 u16 sel = ctxt->src.val; 3830 3831 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) 3832 return emulate_ud(ctxt); 3833 3834 if (ctxt->modrm_reg == VCPU_SREG_SS) 3835 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 3836 3837 /* Disable writeback. */ 3838 ctxt->dst.type = OP_NONE; 3839 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); 3840} 3841 3842static int em_sldt(struct x86_emulate_ctxt *ctxt) 3843{ 3844 return em_store_sreg(ctxt, VCPU_SREG_LDTR); 3845} 3846 3847static int em_lldt(struct x86_emulate_ctxt *ctxt) 3848{ 3849 u16 sel = ctxt->src.val; 3850 3851 /* Disable writeback. */ 3852 ctxt->dst.type = OP_NONE; 3853 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR); 3854} 3855 3856static int em_str(struct x86_emulate_ctxt *ctxt) 3857{ 3858 return em_store_sreg(ctxt, VCPU_SREG_TR); 3859} 3860 3861static int em_ltr(struct x86_emulate_ctxt *ctxt) 3862{ 3863 u16 sel = ctxt->src.val; 3864 3865 /* Disable writeback. */ 3866 ctxt->dst.type = OP_NONE; 3867 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR); 3868} 3869 3870static int em_invlpg(struct x86_emulate_ctxt *ctxt) 3871{ 3872 int rc; 3873 ulong linear; 3874 3875 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); 3876 if (rc == X86EMUL_CONTINUE) 3877 ctxt->ops->invlpg(ctxt, linear); 3878 /* Disable writeback. */ 3879 ctxt->dst.type = OP_NONE; 3880 return X86EMUL_CONTINUE; 3881} 3882 3883static int em_clts(struct x86_emulate_ctxt *ctxt) 3884{ 3885 ulong cr0; 3886 3887 cr0 = ctxt->ops->get_cr(ctxt, 0); 3888 cr0 &= ~X86_CR0_TS; 3889 ctxt->ops->set_cr(ctxt, 0, cr0); 3890 return X86EMUL_CONTINUE; 3891} 3892 3893static int em_hypercall(struct x86_emulate_ctxt *ctxt) 3894{ 3895 int rc = ctxt->ops->fix_hypercall(ctxt); 3896 3897 if (rc != X86EMUL_CONTINUE) 3898 return rc; 3899 3900 /* Let the processor re-execute the fixed hypercall */ 3901 ctxt->_eip = ctxt->eip; 3902 /* Disable writeback. */ 3903 ctxt->dst.type = OP_NONE; 3904 return X86EMUL_CONTINUE; 3905} 3906 3907static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt, 3908 void (*get)(struct x86_emulate_ctxt *ctxt, 3909 struct desc_ptr *ptr)) 3910{ 3911 struct desc_ptr desc_ptr; 3912 3913 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3914 ctxt->ops->cpl(ctxt) > 0) 3915 return emulate_gp(ctxt, 0); 3916 3917 if (ctxt->mode == X86EMUL_MODE_PROT64) 3918 ctxt->op_bytes = 8; 3919 get(ctxt, &desc_ptr); 3920 if (ctxt->op_bytes == 2) { 3921 ctxt->op_bytes = 4; 3922 desc_ptr.address &= 0x00ffffff; 3923 } 3924 /* Disable writeback. */ 3925 ctxt->dst.type = OP_NONE; 3926 return segmented_write_std(ctxt, ctxt->dst.addr.mem, 3927 &desc_ptr, 2 + ctxt->op_bytes); 3928} 3929 3930static int em_sgdt(struct x86_emulate_ctxt *ctxt) 3931{ 3932 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt); 3933} 3934 3935static int em_sidt(struct x86_emulate_ctxt *ctxt) 3936{ 3937 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt); 3938} 3939 3940static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt) 3941{ 3942 struct desc_ptr desc_ptr; 3943 int rc; 3944 3945 if (ctxt->mode == X86EMUL_MODE_PROT64) 3946 ctxt->op_bytes = 8; 3947 rc = read_descriptor(ctxt, ctxt->src.addr.mem, 3948 &desc_ptr.size, &desc_ptr.address, 3949 ctxt->op_bytes); 3950 if (rc != X86EMUL_CONTINUE) 3951 return rc; 3952 if (ctxt->mode == X86EMUL_MODE_PROT64 && 3953 emul_is_noncanonical_address(desc_ptr.address, ctxt)) 3954 return emulate_gp(ctxt, 0); 3955 if (lgdt) 3956 ctxt->ops->set_gdt(ctxt, &desc_ptr); 3957 else 3958 ctxt->ops->set_idt(ctxt, &desc_ptr); 3959 /* Disable writeback. */ 3960 ctxt->dst.type = OP_NONE; 3961 return X86EMUL_CONTINUE; 3962} 3963 3964static int em_lgdt(struct x86_emulate_ctxt *ctxt) 3965{ 3966 return em_lgdt_lidt(ctxt, true); 3967} 3968 3969static int em_lidt(struct x86_emulate_ctxt *ctxt) 3970{ 3971 return em_lgdt_lidt(ctxt, false); 3972} 3973 3974static int em_smsw(struct x86_emulate_ctxt *ctxt) 3975{ 3976 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3977 ctxt->ops->cpl(ctxt) > 0) 3978 return emulate_gp(ctxt, 0); 3979 3980 if (ctxt->dst.type == OP_MEM) 3981 ctxt->dst.bytes = 2; 3982 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); 3983 return X86EMUL_CONTINUE; 3984} 3985 3986static int em_lmsw(struct x86_emulate_ctxt *ctxt) 3987{ 3988 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) 3989 | (ctxt->src.val & 0x0f)); 3990 ctxt->dst.type = OP_NONE; 3991 return X86EMUL_CONTINUE; 3992} 3993 3994static int em_loop(struct x86_emulate_ctxt *ctxt) 3995{ 3996 int rc = X86EMUL_CONTINUE; 3997 3998 register_address_increment(ctxt, VCPU_REGS_RCX, -1); 3999 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) && 4000 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) 4001 rc = jmp_rel(ctxt, ctxt->src.val); 4002 4003 return rc; 4004} 4005 4006static int em_jcxz(struct x86_emulate_ctxt *ctxt) 4007{ 4008 int rc = X86EMUL_CONTINUE; 4009 4010 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) 4011 rc = jmp_rel(ctxt, ctxt->src.val); 4012 4013 return rc; 4014} 4015 4016static int em_in(struct x86_emulate_ctxt *ctxt) 4017{ 4018 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, 4019 &ctxt->dst.val)) 4020 return X86EMUL_IO_NEEDED; 4021 4022 return X86EMUL_CONTINUE; 4023} 4024 4025static int em_out(struct x86_emulate_ctxt *ctxt) 4026{ 4027 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, 4028 &ctxt->src.val, 1); 4029 /* Disable writeback. */ 4030 ctxt->dst.type = OP_NONE; 4031 return X86EMUL_CONTINUE; 4032} 4033 4034static int em_cli(struct x86_emulate_ctxt *ctxt) 4035{ 4036 if (emulator_bad_iopl(ctxt)) 4037 return emulate_gp(ctxt, 0); 4038 4039 ctxt->eflags &= ~X86_EFLAGS_IF; 4040 return X86EMUL_CONTINUE; 4041} 4042 4043static int em_sti(struct x86_emulate_ctxt *ctxt) 4044{ 4045 if (emulator_bad_iopl(ctxt)) 4046 return emulate_gp(ctxt, 0); 4047 4048 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; 4049 ctxt->eflags |= X86_EFLAGS_IF; 4050 return X86EMUL_CONTINUE; 4051} 4052 4053static int em_cpuid(struct x86_emulate_ctxt *ctxt) 4054{ 4055 u32 eax, ebx, ecx, edx; 4056 u64 msr = 0; 4057 4058 ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr); 4059 if (msr & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 4060 ctxt->ops->cpl(ctxt)) { 4061 return emulate_gp(ctxt, 0); 4062 } 4063 4064 eax = reg_read(ctxt, VCPU_REGS_RAX); 4065 ecx = reg_read(ctxt, VCPU_REGS_RCX); 4066 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 4067 *reg_write(ctxt, VCPU_REGS_RAX) = eax; 4068 *reg_write(ctxt, VCPU_REGS_RBX) = ebx; 4069 *reg_write(ctxt, VCPU_REGS_RCX) = ecx; 4070 *reg_write(ctxt, VCPU_REGS_RDX) = edx; 4071 return X86EMUL_CONTINUE; 4072} 4073 4074static int em_sahf(struct x86_emulate_ctxt *ctxt) 4075{ 4076 u32 flags; 4077 4078 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | 4079 X86_EFLAGS_SF; 4080 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8; 4081 4082 ctxt->eflags &= ~0xffUL; 4083 ctxt->eflags |= flags | X86_EFLAGS_FIXED; 4084 return X86EMUL_CONTINUE; 4085} 4086 4087static int em_lahf(struct x86_emulate_ctxt *ctxt) 4088{ 4089 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL; 4090 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8; 4091 return X86EMUL_CONTINUE; 4092} 4093 4094static int em_bswap(struct x86_emulate_ctxt *ctxt) 4095{ 4096 switch (ctxt->op_bytes) { 4097#ifdef CONFIG_X86_64 4098 case 8: 4099 asm("bswap %0" : "+r"(ctxt->dst.val)); 4100 break; 4101#endif 4102 default: 4103 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val)); 4104 break; 4105 } 4106 return X86EMUL_CONTINUE; 4107} 4108 4109static int em_clflush(struct x86_emulate_ctxt *ctxt) 4110{ 4111 /* emulating clflush regardless of cpuid */ 4112 return X86EMUL_CONTINUE; 4113} 4114 4115static int em_clflushopt(struct x86_emulate_ctxt *ctxt) 4116{ 4117 /* emulating clflushopt regardless of cpuid */ 4118 return X86EMUL_CONTINUE; 4119} 4120 4121static int em_movsxd(struct x86_emulate_ctxt *ctxt) 4122{ 4123 ctxt->dst.val = (s32) ctxt->src.val; 4124 return X86EMUL_CONTINUE; 4125} 4126 4127static int check_fxsr(struct x86_emulate_ctxt *ctxt) 4128{ 4129 if (!ctxt->ops->guest_has_fxsr(ctxt)) 4130 return emulate_ud(ctxt); 4131 4132 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 4133 return emulate_nm(ctxt); 4134 4135 /* 4136 * Don't emulate a case that should never be hit, instead of working 4137 * around a lack of fxsave64/fxrstor64 on old compilers. 4138 */ 4139 if (ctxt->mode >= X86EMUL_MODE_PROT64) 4140 return X86EMUL_UNHANDLEABLE; 4141 4142 return X86EMUL_CONTINUE; 4143} 4144 4145/* 4146 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but does save 4147 * and restore MXCSR. 4148 */ 4149static size_t __fxstate_size(int nregs) 4150{ 4151 return offsetof(struct fxregs_state, xmm_space[0]) + nregs * 16; 4152} 4153 4154static inline size_t fxstate_size(struct x86_emulate_ctxt *ctxt) 4155{ 4156 bool cr4_osfxsr; 4157 if (ctxt->mode == X86EMUL_MODE_PROT64) 4158 return __fxstate_size(16); 4159 4160 cr4_osfxsr = ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR; 4161 return __fxstate_size(cr4_osfxsr ? 8 : 0); 4162} 4163 4164/* 4165 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode, 4166 * 1) 16 bit mode 4167 * 2) 32 bit mode 4168 * - like (1), but FIP and FDP (foo) are only 16 bit. At least Intel CPUs 4169 * preserve whole 32 bit values, though, so (1) and (2) are the same wrt. 4170 * save and restore 4171 * 3) 64-bit mode with REX.W prefix 4172 * - like (2), but XMM 8-15 are being saved and restored 4173 * 4) 64-bit mode without REX.W prefix 4174 * - like (3), but FIP and FDP are 64 bit 4175 * 4176 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the 4177 * desired result. (4) is not emulated. 4178 * 4179 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS 4180 * and FPU DS) should match. 4181 */ 4182static int em_fxsave(struct x86_emulate_ctxt *ctxt) 4183{ 4184 struct fxregs_state fx_state; 4185 int rc; 4186 4187 rc = check_fxsr(ctxt); 4188 if (rc != X86EMUL_CONTINUE) 4189 return rc; 4190 4191 emulator_get_fpu(); 4192 4193 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state)); 4194 4195 emulator_put_fpu(); 4196 4197 if (rc != X86EMUL_CONTINUE) 4198 return rc; 4199 4200 return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state, 4201 fxstate_size(ctxt)); 4202} 4203 4204/* 4205 * FXRSTOR might restore XMM registers not provided by the guest. Fill 4206 * in the host registers (via FXSAVE) instead, so they won't be modified. 4207 * (preemption has to stay disabled until FXRSTOR). 4208 * 4209 * Use noinline to keep the stack for other functions called by callers small. 4210 */ 4211static noinline int fxregs_fixup(struct fxregs_state *fx_state, 4212 const size_t used_size) 4213{ 4214 struct fxregs_state fx_tmp; 4215 int rc; 4216 4217 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_tmp)); 4218 memcpy((void *)fx_state + used_size, (void *)&fx_tmp + used_size, 4219 __fxstate_size(16) - used_size); 4220 4221 return rc; 4222} 4223 4224static int em_fxrstor(struct x86_emulate_ctxt *ctxt) 4225{ 4226 struct fxregs_state fx_state; 4227 int rc; 4228 size_t size; 4229 4230 rc = check_fxsr(ctxt); 4231 if (rc != X86EMUL_CONTINUE) 4232 return rc; 4233 4234 size = fxstate_size(ctxt); 4235 rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, size); 4236 if (rc != X86EMUL_CONTINUE) 4237 return rc; 4238 4239 emulator_get_fpu(); 4240 4241 if (size < __fxstate_size(16)) { 4242 rc = fxregs_fixup(&fx_state, size); 4243 if (rc != X86EMUL_CONTINUE) 4244 goto out; 4245 } 4246 4247 if (fx_state.mxcsr >> 16) { 4248 rc = emulate_gp(ctxt, 0); 4249 goto out; 4250 } 4251 4252 if (rc == X86EMUL_CONTINUE) 4253 rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state)); 4254 4255out: 4256 emulator_put_fpu(); 4257 4258 return rc; 4259} 4260 4261static int em_xsetbv(struct x86_emulate_ctxt *ctxt) 4262{ 4263 u32 eax, ecx, edx; 4264 4265 eax = reg_read(ctxt, VCPU_REGS_RAX); 4266 edx = reg_read(ctxt, VCPU_REGS_RDX); 4267 ecx = reg_read(ctxt, VCPU_REGS_RCX); 4268 4269 if (ctxt->ops->set_xcr(ctxt, ecx, ((u64)edx << 32) | eax)) 4270 return emulate_gp(ctxt, 0); 4271 4272 return X86EMUL_CONTINUE; 4273} 4274 4275static bool valid_cr(int nr) 4276{ 4277 switch (nr) { 4278 case 0: 4279 case 2 ... 4: 4280 case 8: 4281 return true; 4282 default: 4283 return false; 4284 } 4285} 4286 4287static int check_cr_access(struct x86_emulate_ctxt *ctxt) 4288{ 4289 if (!valid_cr(ctxt->modrm_reg)) 4290 return emulate_ud(ctxt); 4291 4292 return X86EMUL_CONTINUE; 4293} 4294 4295static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) 4296{ 4297 unsigned long dr7; 4298 4299 ctxt->ops->get_dr(ctxt, 7, &dr7); 4300 4301 /* Check if DR7.Global_Enable is set */ 4302 return dr7 & (1 << 13); 4303} 4304 4305static int check_dr_read(struct x86_emulate_ctxt *ctxt) 4306{ 4307 int dr = ctxt->modrm_reg; 4308 u64 cr4; 4309 4310 if (dr > 7) 4311 return emulate_ud(ctxt); 4312 4313 cr4 = ctxt->ops->get_cr(ctxt, 4); 4314 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) 4315 return emulate_ud(ctxt); 4316 4317 if (check_dr7_gd(ctxt)) { 4318 ulong dr6; 4319 4320 ctxt->ops->get_dr(ctxt, 6, &dr6); 4321 dr6 &= ~DR_TRAP_BITS; 4322 dr6 |= DR6_BD | DR6_RTM; 4323 ctxt->ops->set_dr(ctxt, 6, dr6); 4324 return emulate_db(ctxt); 4325 } 4326 4327 return X86EMUL_CONTINUE; 4328} 4329 4330static int check_dr_write(struct x86_emulate_ctxt *ctxt) 4331{ 4332 u64 new_val = ctxt->src.val64; 4333 int dr = ctxt->modrm_reg; 4334 4335 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) 4336 return emulate_gp(ctxt, 0); 4337 4338 return check_dr_read(ctxt); 4339} 4340 4341static int check_svme(struct x86_emulate_ctxt *ctxt) 4342{ 4343 u64 efer = 0; 4344 4345 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 4346 4347 if (!(efer & EFER_SVME)) 4348 return emulate_ud(ctxt); 4349 4350 return X86EMUL_CONTINUE; 4351} 4352 4353static int check_svme_pa(struct x86_emulate_ctxt *ctxt) 4354{ 4355 u64 rax = reg_read(ctxt, VCPU_REGS_RAX); 4356 4357 /* Valid physical address? */ 4358 if (rax & 0xffff000000000000ULL) 4359 return emulate_gp(ctxt, 0); 4360 4361 return check_svme(ctxt); 4362} 4363 4364static int check_rdtsc(struct x86_emulate_ctxt *ctxt) 4365{ 4366 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 4367 4368 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) 4369 return emulate_ud(ctxt); 4370 4371 return X86EMUL_CONTINUE; 4372} 4373 4374static int check_rdpmc(struct x86_emulate_ctxt *ctxt) 4375{ 4376 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 4377 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX); 4378 4379 /* 4380 * VMware allows access to these Pseduo-PMCs even when read via RDPMC 4381 * in Ring3 when CR4.PCE=0. 4382 */ 4383 if (enable_vmware_backdoor && is_vmware_backdoor_pmc(rcx)) 4384 return X86EMUL_CONTINUE; 4385 4386 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || 4387 ctxt->ops->check_pmc(ctxt, rcx)) 4388 return emulate_gp(ctxt, 0); 4389 4390 return X86EMUL_CONTINUE; 4391} 4392 4393static int check_perm_in(struct x86_emulate_ctxt *ctxt) 4394{ 4395 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); 4396 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) 4397 return emulate_gp(ctxt, 0); 4398 4399 return X86EMUL_CONTINUE; 4400} 4401 4402static int check_perm_out(struct x86_emulate_ctxt *ctxt) 4403{ 4404 ctxt->src.bytes = min(ctxt->src.bytes, 4u); 4405 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) 4406 return emulate_gp(ctxt, 0); 4407 4408 return X86EMUL_CONTINUE; 4409} 4410 4411#define D(_y) { .flags = (_y) } 4412#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i } 4413#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \ 4414 .intercept = x86_intercept_##_i, .check_perm = (_p) } 4415#define N D(NotImpl) 4416#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } 4417#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) } 4418#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) } 4419#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) } 4420#define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) } 4421#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) } 4422#define I(_f, _e) { .flags = (_f), .u.execute = (_e) } 4423#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) } 4424#define II(_f, _e, _i) \ 4425 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i } 4426#define IIP(_f, _e, _i, _p) \ 4427 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \ 4428 .intercept = x86_intercept_##_i, .check_perm = (_p) } 4429#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } 4430 4431#define D2bv(_f) D((_f) | ByteOp), D(_f) 4432#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) 4433#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) 4434#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e) 4435#define I2bvIP(_f, _e, _i, _p) \ 4436 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) 4437 4438#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \ 4439 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ 4440 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) 4441 4442static const struct opcode group7_rm0[] = { 4443 N, 4444 I(SrcNone | Priv | EmulateOnUD, em_hypercall), 4445 N, N, N, N, N, N, 4446}; 4447 4448static const struct opcode group7_rm1[] = { 4449 DI(SrcNone | Priv, monitor), 4450 DI(SrcNone | Priv, mwait), 4451 N, N, N, N, N, N, 4452}; 4453 4454static const struct opcode group7_rm2[] = { 4455 N, 4456 II(ImplicitOps | Priv, em_xsetbv, xsetbv), 4457 N, N, N, N, N, N, 4458}; 4459 4460static const struct opcode group7_rm3[] = { 4461 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa), 4462 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall), 4463 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa), 4464 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa), 4465 DIP(SrcNone | Prot | Priv, stgi, check_svme), 4466 DIP(SrcNone | Prot | Priv, clgi, check_svme), 4467 DIP(SrcNone | Prot | Priv, skinit, check_svme), 4468 DIP(SrcNone | Prot | Priv, invlpga, check_svme), 4469}; 4470 4471static const struct opcode group7_rm7[] = { 4472 N, 4473 DIP(SrcNone, rdtscp, check_rdtsc), 4474 N, N, N, N, N, N, 4475}; 4476 4477static const struct opcode group1[] = { 4478 F(Lock, em_add), 4479 F(Lock | PageTable, em_or), 4480 F(Lock, em_adc), 4481 F(Lock, em_sbb), 4482 F(Lock | PageTable, em_and), 4483 F(Lock, em_sub), 4484 F(Lock, em_xor), 4485 F(NoWrite, em_cmp), 4486}; 4487 4488static const struct opcode group1A[] = { 4489 I(DstMem | SrcNone | Mov | Stack | IncSP | TwoMemOp, em_pop), N, N, N, N, N, N, N, 4490}; 4491 4492static const struct opcode group2[] = { 4493 F(DstMem | ModRM, em_rol), 4494 F(DstMem | ModRM, em_ror), 4495 F(DstMem | ModRM, em_rcl), 4496 F(DstMem | ModRM, em_rcr), 4497 F(DstMem | ModRM, em_shl), 4498 F(DstMem | ModRM, em_shr), 4499 F(DstMem | ModRM, em_shl), 4500 F(DstMem | ModRM, em_sar), 4501}; 4502 4503static const struct opcode group3[] = { 4504 F(DstMem | SrcImm | NoWrite, em_test), 4505 F(DstMem | SrcImm | NoWrite, em_test), 4506 F(DstMem | SrcNone | Lock, em_not), 4507 F(DstMem | SrcNone | Lock, em_neg), 4508 F(DstXacc | Src2Mem, em_mul_ex), 4509 F(DstXacc | Src2Mem, em_imul_ex), 4510 F(DstXacc | Src2Mem, em_div_ex), 4511 F(DstXacc | Src2Mem, em_idiv_ex), 4512}; 4513 4514static const struct opcode group4[] = { 4515 F(ByteOp | DstMem | SrcNone | Lock, em_inc), 4516 F(ByteOp | DstMem | SrcNone | Lock, em_dec), 4517 N, N, N, N, N, N, 4518}; 4519 4520static const struct opcode group5[] = { 4521 F(DstMem | SrcNone | Lock, em_inc), 4522 F(DstMem | SrcNone | Lock, em_dec), 4523 I(SrcMem | NearBranch, em_call_near_abs), 4524 I(SrcMemFAddr | ImplicitOps, em_call_far), 4525 I(SrcMem | NearBranch, em_jmp_abs), 4526 I(SrcMemFAddr | ImplicitOps, em_jmp_far), 4527 I(SrcMem | Stack | TwoMemOp, em_push), D(Undefined), 4528}; 4529 4530static const struct opcode group6[] = { 4531 II(Prot | DstMem, em_sldt, sldt), 4532 II(Prot | DstMem, em_str, str), 4533 II(Prot | Priv | SrcMem16, em_lldt, lldt), 4534 II(Prot | Priv | SrcMem16, em_ltr, ltr), 4535 N, N, N, N, 4536}; 4537 4538static const struct group_dual group7 = { { 4539 II(Mov | DstMem, em_sgdt, sgdt), 4540 II(Mov | DstMem, em_sidt, sidt), 4541 II(SrcMem | Priv, em_lgdt, lgdt), 4542 II(SrcMem | Priv, em_lidt, lidt), 4543 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4544 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4545 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg), 4546}, { 4547 EXT(0, group7_rm0), 4548 EXT(0, group7_rm1), 4549 EXT(0, group7_rm2), 4550 EXT(0, group7_rm3), 4551 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4552 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4553 EXT(0, group7_rm7), 4554} }; 4555 4556static const struct opcode group8[] = { 4557 N, N, N, N, 4558 F(DstMem | SrcImmByte | NoWrite, em_bt), 4559 F(DstMem | SrcImmByte | Lock | PageTable, em_bts), 4560 F(DstMem | SrcImmByte | Lock, em_btr), 4561 F(DstMem | SrcImmByte | Lock | PageTable, em_btc), 4562}; 4563 4564/* 4565 * The "memory" destination is actually always a register, since we come 4566 * from the register case of group9. 4567 */ 4568static const struct gprefix pfx_0f_c7_7 = { 4569 N, N, N, II(DstMem | ModRM | Op3264 | EmulateOnUD, em_rdpid, rdpid), 4570}; 4571 4572 4573static const struct group_dual group9 = { { 4574 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, 4575}, { 4576 N, N, N, N, N, N, N, 4577 GP(0, &pfx_0f_c7_7), 4578} }; 4579 4580static const struct opcode group11[] = { 4581 I(DstMem | SrcImm | Mov | PageTable, em_mov), 4582 X7(D(Undefined)), 4583}; 4584 4585static const struct gprefix pfx_0f_ae_7 = { 4586 I(SrcMem | ByteOp, em_clflush), I(SrcMem | ByteOp, em_clflushopt), N, N, 4587}; 4588 4589static const struct group_dual group15 = { { 4590 I(ModRM | Aligned16, em_fxsave), 4591 I(ModRM | Aligned16, em_fxrstor), 4592 N, N, N, N, N, GP(0, &pfx_0f_ae_7), 4593}, { 4594 N, N, N, N, N, N, N, N, 4595} }; 4596 4597static const struct gprefix pfx_0f_6f_0f_7f = { 4598 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), 4599}; 4600 4601static const struct instr_dual instr_dual_0f_2b = { 4602 I(0, em_mov), N 4603}; 4604 4605static const struct gprefix pfx_0f_2b = { 4606 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N, 4607}; 4608 4609static const struct gprefix pfx_0f_10_0f_11 = { 4610 I(Unaligned, em_mov), I(Unaligned, em_mov), N, N, 4611}; 4612 4613static const struct gprefix pfx_0f_28_0f_29 = { 4614 I(Aligned, em_mov), I(Aligned, em_mov), N, N, 4615}; 4616 4617static const struct gprefix pfx_0f_e7 = { 4618 N, I(Sse, em_mov), N, N, 4619}; 4620 4621static const struct escape escape_d9 = { { 4622 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw), 4623}, { 4624 /* 0xC0 - 0xC7 */ 4625 N, N, N, N, N, N, N, N, 4626 /* 0xC8 - 0xCF */ 4627 N, N, N, N, N, N, N, N, 4628 /* 0xD0 - 0xC7 */ 4629 N, N, N, N, N, N, N, N, 4630 /* 0xD8 - 0xDF */ 4631 N, N, N, N, N, N, N, N, 4632 /* 0xE0 - 0xE7 */ 4633 N, N, N, N, N, N, N, N, 4634 /* 0xE8 - 0xEF */ 4635 N, N, N, N, N, N, N, N, 4636 /* 0xF0 - 0xF7 */ 4637 N, N, N, N, N, N, N, N, 4638 /* 0xF8 - 0xFF */ 4639 N, N, N, N, N, N, N, N, 4640} }; 4641 4642static const struct escape escape_db = { { 4643 N, N, N, N, N, N, N, N, 4644}, { 4645 /* 0xC0 - 0xC7 */ 4646 N, N, N, N, N, N, N, N, 4647 /* 0xC8 - 0xCF */ 4648 N, N, N, N, N, N, N, N, 4649 /* 0xD0 - 0xC7 */ 4650 N, N, N, N, N, N, N, N, 4651 /* 0xD8 - 0xDF */ 4652 N, N, N, N, N, N, N, N, 4653 /* 0xE0 - 0xE7 */ 4654 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N, 4655 /* 0xE8 - 0xEF */ 4656 N, N, N, N, N, N, N, N, 4657 /* 0xF0 - 0xF7 */ 4658 N, N, N, N, N, N, N, N, 4659 /* 0xF8 - 0xFF */ 4660 N, N, N, N, N, N, N, N, 4661} }; 4662 4663static const struct escape escape_dd = { { 4664 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw), 4665}, { 4666 /* 0xC0 - 0xC7 */ 4667 N, N, N, N, N, N, N, N, 4668 /* 0xC8 - 0xCF */ 4669 N, N, N, N, N, N, N, N, 4670 /* 0xD0 - 0xC7 */ 4671 N, N, N, N, N, N, N, N, 4672 /* 0xD8 - 0xDF */ 4673 N, N, N, N, N, N, N, N, 4674 /* 0xE0 - 0xE7 */ 4675 N, N, N, N, N, N, N, N, 4676 /* 0xE8 - 0xEF */ 4677 N, N, N, N, N, N, N, N, 4678 /* 0xF0 - 0xF7 */ 4679 N, N, N, N, N, N, N, N, 4680 /* 0xF8 - 0xFF */ 4681 N, N, N, N, N, N, N, N, 4682} }; 4683 4684static const struct instr_dual instr_dual_0f_c3 = { 4685 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N 4686}; 4687 4688static const struct mode_dual mode_dual_63 = { 4689 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd) 4690}; 4691 4692static const struct opcode opcode_table[256] = { 4693 /* 0x00 - 0x07 */ 4694 F6ALU(Lock, em_add), 4695 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), 4696 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), 4697 /* 0x08 - 0x0F */ 4698 F6ALU(Lock | PageTable, em_or), 4699 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), 4700 N, 4701 /* 0x10 - 0x17 */ 4702 F6ALU(Lock, em_adc), 4703 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), 4704 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), 4705 /* 0x18 - 0x1F */ 4706 F6ALU(Lock, em_sbb), 4707 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), 4708 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), 4709 /* 0x20 - 0x27 */ 4710 F6ALU(Lock | PageTable, em_and), N, N, 4711 /* 0x28 - 0x2F */ 4712 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), 4713 /* 0x30 - 0x37 */ 4714 F6ALU(Lock, em_xor), N, N, 4715 /* 0x38 - 0x3F */ 4716 F6ALU(NoWrite, em_cmp), N, N, 4717 /* 0x40 - 0x4F */ 4718 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)), 4719 /* 0x50 - 0x57 */ 4720 X8(I(SrcReg | Stack, em_push)), 4721 /* 0x58 - 0x5F */ 4722 X8(I(DstReg | Stack, em_pop)), 4723 /* 0x60 - 0x67 */ 4724 I(ImplicitOps | Stack | No64, em_pusha), 4725 I(ImplicitOps | Stack | No64, em_popa), 4726 N, MD(ModRM, &mode_dual_63), 4727 N, N, N, N, 4728 /* 0x68 - 0x6F */ 4729 I(SrcImm | Mov | Stack, em_push), 4730 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), 4731 I(SrcImmByte | Mov | Stack, em_push), 4732 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), 4733 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */ 4734 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ 4735 /* 0x70 - 0x7F */ 4736 X16(D(SrcImmByte | NearBranch)), 4737 /* 0x80 - 0x87 */ 4738 G(ByteOp | DstMem | SrcImm, group1), 4739 G(DstMem | SrcImm, group1), 4740 G(ByteOp | DstMem | SrcImm | No64, group1), 4741 G(DstMem | SrcImmByte, group1), 4742 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test), 4743 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), 4744 /* 0x88 - 0x8F */ 4745 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), 4746 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), 4747 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), 4748 D(ModRM | SrcMem | NoAccess | DstReg), 4749 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), 4750 G(0, group1A), 4751 /* 0x90 - 0x97 */ 4752 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), 4753 /* 0x98 - 0x9F */ 4754 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), 4755 I(SrcImmFAddr | No64, em_call_far), N, 4756 II(ImplicitOps | Stack, em_pushf, pushf), 4757 II(ImplicitOps | Stack, em_popf, popf), 4758 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf), 4759 /* 0xA0 - 0xA7 */ 4760 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), 4761 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), 4762 I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov), 4763 F2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r), 4764 /* 0xA8 - 0xAF */ 4765 F2bv(DstAcc | SrcImm | NoWrite, em_test), 4766 I2bv(SrcAcc | DstDI | Mov | String, em_mov), 4767 I2bv(SrcSI | DstAcc | Mov | String, em_mov), 4768 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r), 4769 /* 0xB0 - 0xB7 */ 4770 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), 4771 /* 0xB8 - 0xBF */ 4772 X8(I(DstReg | SrcImm64 | Mov, em_mov)), 4773 /* 0xC0 - 0xC7 */ 4774 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2), 4775 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm), 4776 I(ImplicitOps | NearBranch, em_ret), 4777 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), 4778 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), 4779 G(ByteOp, group11), G(0, group11), 4780 /* 0xC8 - 0xCF */ 4781 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave), 4782 I(ImplicitOps | SrcImmU16, em_ret_far_imm), 4783 I(ImplicitOps, em_ret_far), 4784 D(ImplicitOps), DI(SrcImmByte, intn), 4785 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret), 4786 /* 0xD0 - 0xD7 */ 4787 G(Src2One | ByteOp, group2), G(Src2One, group2), 4788 G(Src2CL | ByteOp, group2), G(Src2CL, group2), 4789 I(DstAcc | SrcImmUByte | No64, em_aam), 4790 I(DstAcc | SrcImmUByte | No64, em_aad), 4791 F(DstAcc | ByteOp | No64, em_salc), 4792 I(DstAcc | SrcXLat | ByteOp, em_mov), 4793 /* 0xD8 - 0xDF */ 4794 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N, 4795 /* 0xE0 - 0xE7 */ 4796 X3(I(SrcImmByte | NearBranch, em_loop)), 4797 I(SrcImmByte | NearBranch, em_jcxz), 4798 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), 4799 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), 4800 /* 0xE8 - 0xEF */ 4801 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch), 4802 I(SrcImmFAddr | No64, em_jmp_far), 4803 D(SrcImmByte | ImplicitOps | NearBranch), 4804 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), 4805 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), 4806 /* 0xF0 - 0xF7 */ 4807 N, DI(ImplicitOps, icebp), N, N, 4808 DI(ImplicitOps | Priv, hlt), D(ImplicitOps), 4809 G(ByteOp, group3), G(0, group3), 4810 /* 0xF8 - 0xFF */ 4811 D(ImplicitOps), D(ImplicitOps), 4812 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), 4813 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), 4814}; 4815 4816static const struct opcode twobyte_table[256] = { 4817 /* 0x00 - 0x0F */ 4818 G(0, group6), GD(0, &group7), N, N, 4819 N, I(ImplicitOps | EmulateOnUD, em_syscall), 4820 II(ImplicitOps | Priv, em_clts, clts), N, 4821 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, 4822 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, 4823 /* 0x10 - 0x1F */ 4824 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_10_0f_11), 4825 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_10_0f_11), 4826 N, N, N, N, N, N, 4827 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 4 * prefetch + 4 * reserved NOP */ 4828 D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, 4829 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */ 4830 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */ 4831 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */ 4832 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* NOP + 7 * reserved NOP */ 4833 /* 0x20 - 0x2F */ 4834 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_access), 4835 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read), 4836 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write, 4837 check_cr_access), 4838 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write, 4839 check_dr_write), 4840 N, N, N, N, 4841 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29), 4842 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29), 4843 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b), 4844 N, N, N, N, 4845 /* 0x30 - 0x3F */ 4846 II(ImplicitOps | Priv, em_wrmsr, wrmsr), 4847 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), 4848 II(ImplicitOps | Priv, em_rdmsr, rdmsr), 4849 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), 4850 I(ImplicitOps | EmulateOnUD, em_sysenter), 4851 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit), 4852 N, N, 4853 N, N, N, N, N, N, N, N, 4854 /* 0x40 - 0x4F */ 4855 X16(D(DstReg | SrcMem | ModRM)), 4856 /* 0x50 - 0x5F */ 4857 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4858 /* 0x60 - 0x6F */ 4859 N, N, N, N, 4860 N, N, N, N, 4861 N, N, N, N, 4862 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), 4863 /* 0x70 - 0x7F */ 4864 N, N, N, N, 4865 N, N, N, N, 4866 N, N, N, N, 4867 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), 4868 /* 0x80 - 0x8F */ 4869 X16(D(SrcImm | NearBranch)), 4870 /* 0x90 - 0x9F */ 4871 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), 4872 /* 0xA0 - 0xA7 */ 4873 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), 4874 II(ImplicitOps, em_cpuid, cpuid), 4875 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt), 4876 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld), 4877 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N, 4878 /* 0xA8 - 0xAF */ 4879 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), 4880 II(EmulateOnUD | ImplicitOps, em_rsm, rsm), 4881 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), 4882 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd), 4883 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd), 4884 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul), 4885 /* 0xB0 - 0xB7 */ 4886 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg), 4887 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), 4888 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), 4889 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), 4890 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), 4891 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4892 /* 0xB8 - 0xBF */ 4893 N, N, 4894 G(BitOp, group8), 4895 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), 4896 I(DstReg | SrcMem | ModRM, em_bsf_c), 4897 I(DstReg | SrcMem | ModRM, em_bsr_c), 4898 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4899 /* 0xC0 - 0xC7 */ 4900 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd), 4901 N, ID(0, &instr_dual_0f_c3), 4902 N, N, N, GD(0, &group9), 4903 /* 0xC8 - 0xCF */ 4904 X8(I(DstReg, em_bswap)), 4905 /* 0xD0 - 0xDF */ 4906 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4907 /* 0xE0 - 0xEF */ 4908 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7), 4909 N, N, N, N, N, N, N, N, 4910 /* 0xF0 - 0xFF */ 4911 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N 4912}; 4913 4914static const struct instr_dual instr_dual_0f_38_f0 = { 4915 I(DstReg | SrcMem | Mov, em_movbe), N 4916}; 4917 4918static const struct instr_dual instr_dual_0f_38_f1 = { 4919 I(DstMem | SrcReg | Mov, em_movbe), N 4920}; 4921 4922static const struct gprefix three_byte_0f_38_f0 = { 4923 ID(0, &instr_dual_0f_38_f0), N, N, N 4924}; 4925 4926static const struct gprefix three_byte_0f_38_f1 = { 4927 ID(0, &instr_dual_0f_38_f1), N, N, N 4928}; 4929 4930/* 4931 * Insns below are selected by the prefix which indexed by the third opcode 4932 * byte. 4933 */ 4934static const struct opcode opcode_map_0f_38[256] = { 4935 /* 0x00 - 0x7f */ 4936 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4937 /* 0x80 - 0xef */ 4938 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4939 /* 0xf0 - 0xf1 */ 4940 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0), 4941 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1), 4942 /* 0xf2 - 0xff */ 4943 N, N, X4(N), X8(N) 4944}; 4945 4946#undef D 4947#undef N 4948#undef G 4949#undef GD 4950#undef I 4951#undef GP 4952#undef EXT 4953#undef MD 4954#undef ID 4955 4956#undef D2bv 4957#undef D2bvIP 4958#undef I2bv 4959#undef I2bvIP 4960#undef I6ALU 4961 4962static unsigned imm_size(struct x86_emulate_ctxt *ctxt) 4963{ 4964 unsigned size; 4965 4966 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4967 if (size == 8) 4968 size = 4; 4969 return size; 4970} 4971 4972static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, 4973 unsigned size, bool sign_extension) 4974{ 4975 int rc = X86EMUL_CONTINUE; 4976 4977 op->type = OP_IMM; 4978 op->bytes = size; 4979 op->addr.mem.ea = ctxt->_eip; 4980 /* NB. Immediates are sign-extended as necessary. */ 4981 switch (op->bytes) { 4982 case 1: 4983 op->val = insn_fetch(s8, ctxt); 4984 break; 4985 case 2: 4986 op->val = insn_fetch(s16, ctxt); 4987 break; 4988 case 4: 4989 op->val = insn_fetch(s32, ctxt); 4990 break; 4991 case 8: 4992 op->val = insn_fetch(s64, ctxt); 4993 break; 4994 } 4995 if (!sign_extension) { 4996 switch (op->bytes) { 4997 case 1: 4998 op->val &= 0xff; 4999 break; 5000 case 2: 5001 op->val &= 0xffff; 5002 break; 5003 case 4: 5004 op->val &= 0xffffffff; 5005 break; 5006 } 5007 } 5008done: 5009 return rc; 5010} 5011 5012static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, 5013 unsigned d) 5014{ 5015 int rc = X86EMUL_CONTINUE; 5016 5017 switch (d) { 5018 case OpReg: 5019 decode_register_operand(ctxt, op); 5020 break; 5021 case OpImmUByte: 5022 rc = decode_imm(ctxt, op, 1, false); 5023 break; 5024 case OpMem: 5025 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 5026 mem_common: 5027 *op = ctxt->memop; 5028 ctxt->memopp = op; 5029 if (ctxt->d & BitOp) 5030 fetch_bit_operand(ctxt); 5031 op->orig_val = op->val; 5032 break; 5033 case OpMem64: 5034 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8; 5035 goto mem_common; 5036 case OpAcc: 5037 op->type = OP_REG; 5038 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 5039 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 5040 fetch_register_operand(op); 5041 op->orig_val = op->val; 5042 break; 5043 case OpAccLo: 5044 op->type = OP_REG; 5045 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes; 5046 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 5047 fetch_register_operand(op); 5048 op->orig_val = op->val; 5049 break; 5050 case OpAccHi: 5051 if (ctxt->d & ByteOp) { 5052 op->type = OP_NONE; 5053 break; 5054 } 5055 op->type = OP_REG; 5056 op->bytes = ctxt->op_bytes; 5057 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 5058 fetch_register_operand(op); 5059 op->orig_val = op->val; 5060 break; 5061 case OpDI: 5062 op->type = OP_MEM; 5063 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 5064 op->addr.mem.ea = 5065 register_address(ctxt, VCPU_REGS_RDI); 5066 op->addr.mem.seg = VCPU_SREG_ES; 5067 op->val = 0; 5068 op->count = 1; 5069 break; 5070 case OpDX: 5071 op->type = OP_REG; 5072 op->bytes = 2; 5073 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 5074 fetch_register_operand(op); 5075 break; 5076 case OpCL: 5077 op->type = OP_IMM; 5078 op->bytes = 1; 5079 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff; 5080 break; 5081 case OpImmByte: 5082 rc = decode_imm(ctxt, op, 1, true); 5083 break; 5084 case OpOne: 5085 op->type = OP_IMM; 5086 op->bytes = 1; 5087 op->val = 1; 5088 break; 5089 case OpImm: 5090 rc = decode_imm(ctxt, op, imm_size(ctxt), true); 5091 break; 5092 case OpImm64: 5093 rc = decode_imm(ctxt, op, ctxt->op_bytes, true); 5094 break; 5095 case OpMem8: 5096 ctxt->memop.bytes = 1; 5097 if (ctxt->memop.type == OP_REG) { 5098 ctxt->memop.addr.reg = decode_register(ctxt, 5099 ctxt->modrm_rm, true); 5100 fetch_register_operand(&ctxt->memop); 5101 } 5102 goto mem_common; 5103 case OpMem16: 5104 ctxt->memop.bytes = 2; 5105 goto mem_common; 5106 case OpMem32: 5107 ctxt->memop.bytes = 4; 5108 goto mem_common; 5109 case OpImmU16: 5110 rc = decode_imm(ctxt, op, 2, false); 5111 break; 5112 case OpImmU: 5113 rc = decode_imm(ctxt, op, imm_size(ctxt), false); 5114 break; 5115 case OpSI: 5116 op->type = OP_MEM; 5117 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 5118 op->addr.mem.ea = 5119 register_address(ctxt, VCPU_REGS_RSI); 5120 op->addr.mem.seg = ctxt->seg_override; 5121 op->val = 0; 5122 op->count = 1; 5123 break; 5124 case OpXLat: 5125 op->type = OP_MEM; 5126 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 5127 op->addr.mem.ea = 5128 address_mask(ctxt, 5129 reg_read(ctxt, VCPU_REGS_RBX) + 5130 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff)); 5131 op->addr.mem.seg = ctxt->seg_override; 5132 op->val = 0; 5133 break; 5134 case OpImmFAddr: 5135 op->type = OP_IMM; 5136 op->addr.mem.ea = ctxt->_eip; 5137 op->bytes = ctxt->op_bytes + 2; 5138 insn_fetch_arr(op->valptr, op->bytes, ctxt); 5139 break; 5140 case OpMemFAddr: 5141 ctxt->memop.bytes = ctxt->op_bytes + 2; 5142 goto mem_common; 5143 case OpES: 5144 op->type = OP_IMM; 5145 op->val = VCPU_SREG_ES; 5146 break; 5147 case OpCS: 5148 op->type = OP_IMM; 5149 op->val = VCPU_SREG_CS; 5150 break; 5151 case OpSS: 5152 op->type = OP_IMM; 5153 op->val = VCPU_SREG_SS; 5154 break; 5155 case OpDS: 5156 op->type = OP_IMM; 5157 op->val = VCPU_SREG_DS; 5158 break; 5159 case OpFS: 5160 op->type = OP_IMM; 5161 op->val = VCPU_SREG_FS; 5162 break; 5163 case OpGS: 5164 op->type = OP_IMM; 5165 op->val = VCPU_SREG_GS; 5166 break; 5167 case OpImplicit: 5168 /* Special instructions do their own operand decoding. */ 5169 default: 5170 op->type = OP_NONE; /* Disable writeback. */ 5171 break; 5172 } 5173 5174done: 5175 return rc; 5176} 5177 5178int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) 5179{ 5180 int rc = X86EMUL_CONTINUE; 5181 int mode = ctxt->mode; 5182 int def_op_bytes, def_ad_bytes, goffset, simd_prefix; 5183 bool op_prefix = false; 5184 bool has_seg_override = false; 5185 struct opcode opcode; 5186 u16 dummy; 5187 struct desc_struct desc; 5188 5189 ctxt->memop.type = OP_NONE; 5190 ctxt->memopp = NULL; 5191 ctxt->_eip = ctxt->eip; 5192 ctxt->fetch.ptr = ctxt->fetch.data; 5193 ctxt->fetch.end = ctxt->fetch.data + insn_len; 5194 ctxt->opcode_len = 1; 5195 ctxt->intercept = x86_intercept_none; 5196 if (insn_len > 0) 5197 memcpy(ctxt->fetch.data, insn, insn_len); 5198 else { 5199 rc = __do_insn_fetch_bytes(ctxt, 1); 5200 if (rc != X86EMUL_CONTINUE) 5201 goto done; 5202 } 5203 5204 switch (mode) { 5205 case X86EMUL_MODE_REAL: 5206 case X86EMUL_MODE_VM86: 5207 def_op_bytes = def_ad_bytes = 2; 5208 ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, VCPU_SREG_CS); 5209 if (desc.d) 5210 def_op_bytes = def_ad_bytes = 4; 5211 break; 5212 case X86EMUL_MODE_PROT16: 5213 def_op_bytes = def_ad_bytes = 2; 5214 break; 5215 case X86EMUL_MODE_PROT32: 5216 def_op_bytes = def_ad_bytes = 4; 5217 break; 5218#ifdef CONFIG_X86_64 5219 case X86EMUL_MODE_PROT64: 5220 def_op_bytes = 4; 5221 def_ad_bytes = 8; 5222 break; 5223#endif 5224 default: 5225 return EMULATION_FAILED; 5226 } 5227 5228 ctxt->op_bytes = def_op_bytes; 5229 ctxt->ad_bytes = def_ad_bytes; 5230 5231 /* Legacy prefixes. */ 5232 for (;;) { 5233 switch (ctxt->b = insn_fetch(u8, ctxt)) { 5234 case 0x66: /* operand-size override */ 5235 op_prefix = true; 5236 /* switch between 2/4 bytes */ 5237 ctxt->op_bytes = def_op_bytes ^ 6; 5238 break; 5239 case 0x67: /* address-size override */ 5240 if (mode == X86EMUL_MODE_PROT64) 5241 /* switch between 4/8 bytes */ 5242 ctxt->ad_bytes = def_ad_bytes ^ 12; 5243 else 5244 /* switch between 2/4 bytes */ 5245 ctxt->ad_bytes = def_ad_bytes ^ 6; 5246 break; 5247 case 0x26: /* ES override */ 5248 has_seg_override = true; 5249 ctxt->seg_override = VCPU_SREG_ES; 5250 break; 5251 case 0x2e: /* CS override */ 5252 has_seg_override = true; 5253 ctxt->seg_override = VCPU_SREG_CS; 5254 break; 5255 case 0x36: /* SS override */ 5256 has_seg_override = true; 5257 ctxt->seg_override = VCPU_SREG_SS; 5258 break; 5259 case 0x3e: /* DS override */ 5260 has_seg_override = true; 5261 ctxt->seg_override = VCPU_SREG_DS; 5262 break; 5263 case 0x64: /* FS override */ 5264 has_seg_override = true; 5265 ctxt->seg_override = VCPU_SREG_FS; 5266 break; 5267 case 0x65: /* GS override */ 5268 has_seg_override = true; 5269 ctxt->seg_override = VCPU_SREG_GS; 5270 break; 5271 case 0x40 ... 0x4f: /* REX */ 5272 if (mode != X86EMUL_MODE_PROT64) 5273 goto done_prefixes; 5274 ctxt->rex_prefix = ctxt->b; 5275 continue; 5276 case 0xf0: /* LOCK */ 5277 ctxt->lock_prefix = 1; 5278 break; 5279 case 0xf2: /* REPNE/REPNZ */ 5280 case 0xf3: /* REP/REPE/REPZ */ 5281 ctxt->rep_prefix = ctxt->b; 5282 break; 5283 default: 5284 goto done_prefixes; 5285 } 5286 5287 /* Any legacy prefix after a REX prefix nullifies its effect. */ 5288 5289 ctxt->rex_prefix = 0; 5290 } 5291 5292done_prefixes: 5293 5294 /* REX prefix. */ 5295 if (ctxt->rex_prefix & 8) 5296 ctxt->op_bytes = 8; /* REX.W */ 5297 5298 /* Opcode byte(s). */ 5299 opcode = opcode_table[ctxt->b]; 5300 /* Two-byte opcode? */ 5301 if (ctxt->b == 0x0f) { 5302 ctxt->opcode_len = 2; 5303 ctxt->b = insn_fetch(u8, ctxt); 5304 opcode = twobyte_table[ctxt->b]; 5305 5306 /* 0F_38 opcode map */ 5307 if (ctxt->b == 0x38) { 5308 ctxt->opcode_len = 3; 5309 ctxt->b = insn_fetch(u8, ctxt); 5310 opcode = opcode_map_0f_38[ctxt->b]; 5311 } 5312 } 5313 ctxt->d = opcode.flags; 5314 5315 if (ctxt->d & ModRM) 5316 ctxt->modrm = insn_fetch(u8, ctxt); 5317 5318 /* vex-prefix instructions are not implemented */ 5319 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) && 5320 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) { 5321 ctxt->d = NotImpl; 5322 } 5323 5324 while (ctxt->d & GroupMask) { 5325 switch (ctxt->d & GroupMask) { 5326 case Group: 5327 goffset = (ctxt->modrm >> 3) & 7; 5328 opcode = opcode.u.group[goffset]; 5329 break; 5330 case GroupDual: 5331 goffset = (ctxt->modrm >> 3) & 7; 5332 if ((ctxt->modrm >> 6) == 3) 5333 opcode = opcode.u.gdual->mod3[goffset]; 5334 else 5335 opcode = opcode.u.gdual->mod012[goffset]; 5336 break; 5337 case RMExt: 5338 goffset = ctxt->modrm & 7; 5339 opcode = opcode.u.group[goffset]; 5340 break; 5341 case Prefix: 5342 if (ctxt->rep_prefix && op_prefix) 5343 return EMULATION_FAILED; 5344 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; 5345 switch (simd_prefix) { 5346 case 0x00: opcode = opcode.u.gprefix->pfx_no; break; 5347 case 0x66: opcode = opcode.u.gprefix->pfx_66; break; 5348 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; 5349 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; 5350 } 5351 break; 5352 case Escape: 5353 if (ctxt->modrm > 0xbf) { 5354 size_t size = ARRAY_SIZE(opcode.u.esc->high); 5355 u32 index = array_index_nospec( 5356 ctxt->modrm - 0xc0, size); 5357 5358 opcode = opcode.u.esc->high[index]; 5359 } else { 5360 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7]; 5361 } 5362 break; 5363 case InstrDual: 5364 if ((ctxt->modrm >> 6) == 3) 5365 opcode = opcode.u.idual->mod3; 5366 else 5367 opcode = opcode.u.idual->mod012; 5368 break; 5369 case ModeDual: 5370 if (ctxt->mode == X86EMUL_MODE_PROT64) 5371 opcode = opcode.u.mdual->mode64; 5372 else 5373 opcode = opcode.u.mdual->mode32; 5374 break; 5375 default: 5376 return EMULATION_FAILED; 5377 } 5378 5379 ctxt->d &= ~(u64)GroupMask; 5380 ctxt->d |= opcode.flags; 5381 } 5382 5383 /* Unrecognised? */ 5384 if (ctxt->d == 0) 5385 return EMULATION_FAILED; 5386 5387 ctxt->execute = opcode.u.execute; 5388 5389 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD))) 5390 return EMULATION_FAILED; 5391 5392 if (unlikely(ctxt->d & 5393 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch| 5394 No16))) { 5395 /* 5396 * These are copied unconditionally here, and checked unconditionally 5397 * in x86_emulate_insn. 5398 */ 5399 ctxt->check_perm = opcode.check_perm; 5400 ctxt->intercept = opcode.intercept; 5401 5402 if (ctxt->d & NotImpl) 5403 return EMULATION_FAILED; 5404 5405 if (mode == X86EMUL_MODE_PROT64) { 5406 if (ctxt->op_bytes == 4 && (ctxt->d & Stack)) 5407 ctxt->op_bytes = 8; 5408 else if (ctxt->d & NearBranch) 5409 ctxt->op_bytes = 8; 5410 } 5411 5412 if (ctxt->d & Op3264) { 5413 if (mode == X86EMUL_MODE_PROT64) 5414 ctxt->op_bytes = 8; 5415 else 5416 ctxt->op_bytes = 4; 5417 } 5418 5419 if ((ctxt->d & No16) && ctxt->op_bytes == 2) 5420 ctxt->op_bytes = 4; 5421 5422 if (ctxt->d & Sse) 5423 ctxt->op_bytes = 16; 5424 else if (ctxt->d & Mmx) 5425 ctxt->op_bytes = 8; 5426 } 5427 5428 /* ModRM and SIB bytes. */ 5429 if (ctxt->d & ModRM) { 5430 rc = decode_modrm(ctxt, &ctxt->memop); 5431 if (!has_seg_override) { 5432 has_seg_override = true; 5433 ctxt->seg_override = ctxt->modrm_seg; 5434 } 5435 } else if (ctxt->d & MemAbs) 5436 rc = decode_abs(ctxt, &ctxt->memop); 5437 if (rc != X86EMUL_CONTINUE) 5438 goto done; 5439 5440 if (!has_seg_override) 5441 ctxt->seg_override = VCPU_SREG_DS; 5442 5443 ctxt->memop.addr.mem.seg = ctxt->seg_override; 5444 5445 /* 5446 * Decode and fetch the source operand: register, memory 5447 * or immediate. 5448 */ 5449 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); 5450 if (rc != X86EMUL_CONTINUE) 5451 goto done; 5452 5453 /* 5454 * Decode and fetch the second source operand: register, memory 5455 * or immediate. 5456 */ 5457 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); 5458 if (rc != X86EMUL_CONTINUE) 5459 goto done; 5460 5461 /* Decode and fetch the destination operand: register or memory. */ 5462 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); 5463 5464 if (ctxt->rip_relative && likely(ctxt->memopp)) 5465 ctxt->memopp->addr.mem.ea = address_mask(ctxt, 5466 ctxt->memopp->addr.mem.ea + ctxt->_eip); 5467 5468done: 5469 if (rc == X86EMUL_PROPAGATE_FAULT) 5470 ctxt->have_exception = true; 5471 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; 5472} 5473 5474bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) 5475{ 5476 return ctxt->d & PageTable; 5477} 5478 5479static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) 5480{ 5481 /* The second termination condition only applies for REPE 5482 * and REPNE. Test if the repeat string operation prefix is 5483 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the 5484 * corresponding termination condition according to: 5485 * - if REPE/REPZ and ZF = 0 then done 5486 * - if REPNE/REPNZ and ZF = 1 then done 5487 */ 5488 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || 5489 (ctxt->b == 0xae) || (ctxt->b == 0xaf)) 5490 && (((ctxt->rep_prefix == REPE_PREFIX) && 5491 ((ctxt->eflags & X86_EFLAGS_ZF) == 0)) 5492 || ((ctxt->rep_prefix == REPNE_PREFIX) && 5493 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF)))) 5494 return true; 5495 5496 return false; 5497} 5498 5499static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt) 5500{ 5501 int rc; 5502 5503 emulator_get_fpu(); 5504 rc = asm_safe("fwait"); 5505 emulator_put_fpu(); 5506 5507 if (unlikely(rc != X86EMUL_CONTINUE)) 5508 return emulate_exception(ctxt, MF_VECTOR, 0, false); 5509 5510 return X86EMUL_CONTINUE; 5511} 5512 5513static void fetch_possible_mmx_operand(struct operand *op) 5514{ 5515 if (op->type == OP_MM) 5516 read_mmx_reg(&op->mm_val, op->addr.mm); 5517} 5518 5519static int fastop(struct x86_emulate_ctxt *ctxt, fastop_t fop) 5520{ 5521 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF; 5522 5523 if (!(ctxt->d & ByteOp)) 5524 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE; 5525 5526 asm("push %[flags]; popf; " CALL_NOSPEC " ; pushf; pop %[flags]\n" 5527 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags), 5528 [thunk_target]"+S"(fop), ASM_CALL_CONSTRAINT 5529 : "c"(ctxt->src2.val)); 5530 5531 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK); 5532 if (!fop) /* exception is returned in fop variable */ 5533 return emulate_de(ctxt); 5534 return X86EMUL_CONTINUE; 5535} 5536 5537void init_decode_cache(struct x86_emulate_ctxt *ctxt) 5538{ 5539 memset(&ctxt->rip_relative, 0, 5540 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative); 5541 5542 ctxt->io_read.pos = 0; 5543 ctxt->io_read.end = 0; 5544 ctxt->mem_read.end = 0; 5545} 5546 5547int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) 5548{ 5549 const struct x86_emulate_ops *ops = ctxt->ops; 5550 int rc = X86EMUL_CONTINUE; 5551 int saved_dst_type = ctxt->dst.type; 5552 unsigned emul_flags; 5553 5554 ctxt->mem_read.pos = 0; 5555 5556 /* LOCK prefix is allowed only with some instructions */ 5557 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { 5558 rc = emulate_ud(ctxt); 5559 goto done; 5560 } 5561 5562 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { 5563 rc = emulate_ud(ctxt); 5564 goto done; 5565 } 5566 5567 emul_flags = ctxt->ops->get_hflags(ctxt); 5568 if (unlikely(ctxt->d & 5569 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) { 5570 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) || 5571 (ctxt->d & Undefined)) { 5572 rc = emulate_ud(ctxt); 5573 goto done; 5574 } 5575 5576 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) 5577 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { 5578 rc = emulate_ud(ctxt); 5579 goto done; 5580 } 5581 5582 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { 5583 rc = emulate_nm(ctxt); 5584 goto done; 5585 } 5586 5587 if (ctxt->d & Mmx) { 5588 rc = flush_pending_x87_faults(ctxt); 5589 if (rc != X86EMUL_CONTINUE) 5590 goto done; 5591 /* 5592 * Now that we know the fpu is exception safe, we can fetch 5593 * operands from it. 5594 */ 5595 fetch_possible_mmx_operand(&ctxt->src); 5596 fetch_possible_mmx_operand(&ctxt->src2); 5597 if (!(ctxt->d & Mov)) 5598 fetch_possible_mmx_operand(&ctxt->dst); 5599 } 5600 5601 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) { 5602 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5603 X86_ICPT_PRE_EXCEPT); 5604 if (rc != X86EMUL_CONTINUE) 5605 goto done; 5606 } 5607 5608 /* Instruction can only be executed in protected mode */ 5609 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) { 5610 rc = emulate_ud(ctxt); 5611 goto done; 5612 } 5613 5614 /* Privileged instruction can be executed only in CPL=0 */ 5615 if ((ctxt->d & Priv) && ops->cpl(ctxt)) { 5616 if (ctxt->d & PrivUD) 5617 rc = emulate_ud(ctxt); 5618 else 5619 rc = emulate_gp(ctxt, 0); 5620 goto done; 5621 } 5622 5623 /* Do instruction specific permission checks */ 5624 if (ctxt->d & CheckPerm) { 5625 rc = ctxt->check_perm(ctxt); 5626 if (rc != X86EMUL_CONTINUE) 5627 goto done; 5628 } 5629 5630 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) { 5631 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5632 X86_ICPT_POST_EXCEPT); 5633 if (rc != X86EMUL_CONTINUE) 5634 goto done; 5635 } 5636 5637 if (ctxt->rep_prefix && (ctxt->d & String)) { 5638 /* All REP prefixes have the same first termination condition */ 5639 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) { 5640 string_registers_quirk(ctxt); 5641 ctxt->eip = ctxt->_eip; 5642 ctxt->eflags &= ~X86_EFLAGS_RF; 5643 goto done; 5644 } 5645 } 5646 } 5647 5648 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { 5649 rc = segmented_read(ctxt, ctxt->src.addr.mem, 5650 ctxt->src.valptr, ctxt->src.bytes); 5651 if (rc != X86EMUL_CONTINUE) 5652 goto done; 5653 ctxt->src.orig_val64 = ctxt->src.val64; 5654 } 5655 5656 if (ctxt->src2.type == OP_MEM) { 5657 rc = segmented_read(ctxt, ctxt->src2.addr.mem, 5658 &ctxt->src2.val, ctxt->src2.bytes); 5659 if (rc != X86EMUL_CONTINUE) 5660 goto done; 5661 } 5662 5663 if ((ctxt->d & DstMask) == ImplicitOps) 5664 goto special_insn; 5665 5666 5667 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { 5668 /* optimisation - avoid slow emulated read if Mov */ 5669 rc = segmented_read(ctxt, ctxt->dst.addr.mem, 5670 &ctxt->dst.val, ctxt->dst.bytes); 5671 if (rc != X86EMUL_CONTINUE) { 5672 if (!(ctxt->d & NoWrite) && 5673 rc == X86EMUL_PROPAGATE_FAULT && 5674 ctxt->exception.vector == PF_VECTOR) 5675 ctxt->exception.error_code |= PFERR_WRITE_MASK; 5676 goto done; 5677 } 5678 } 5679 /* Copy full 64-bit value for CMPXCHG8B. */ 5680 ctxt->dst.orig_val64 = ctxt->dst.val64; 5681 5682special_insn: 5683 5684 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) { 5685 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5686 X86_ICPT_POST_MEMACCESS); 5687 if (rc != X86EMUL_CONTINUE) 5688 goto done; 5689 } 5690 5691 if (ctxt->rep_prefix && (ctxt->d & String)) 5692 ctxt->eflags |= X86_EFLAGS_RF; 5693 else 5694 ctxt->eflags &= ~X86_EFLAGS_RF; 5695 5696 if (ctxt->execute) { 5697 if (ctxt->d & Fastop) 5698 rc = fastop(ctxt, ctxt->fop); 5699 else 5700 rc = ctxt->execute(ctxt); 5701 if (rc != X86EMUL_CONTINUE) 5702 goto done; 5703 goto writeback; 5704 } 5705 5706 if (ctxt->opcode_len == 2) 5707 goto twobyte_insn; 5708 else if (ctxt->opcode_len == 3) 5709 goto threebyte_insn; 5710 5711 switch (ctxt->b) { 5712 case 0x70 ... 0x7f: /* jcc (short) */ 5713 if (test_cc(ctxt->b, ctxt->eflags)) 5714 rc = jmp_rel(ctxt, ctxt->src.val); 5715 break; 5716 case 0x8d: /* lea r16/r32, m */ 5717 ctxt->dst.val = ctxt->src.addr.mem.ea; 5718 break; 5719 case 0x90 ... 0x97: /* nop / xchg reg, rax */ 5720 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX)) 5721 ctxt->dst.type = OP_NONE; 5722 else 5723 rc = em_xchg(ctxt); 5724 break; 5725 case 0x98: /* cbw/cwde/cdqe */ 5726 switch (ctxt->op_bytes) { 5727 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; 5728 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; 5729 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; 5730 } 5731 break; 5732 case 0xcc: /* int3 */ 5733 rc = emulate_int(ctxt, 3); 5734 break; 5735 case 0xcd: /* int n */ 5736 rc = emulate_int(ctxt, ctxt->src.val); 5737 break; 5738 case 0xce: /* into */ 5739 if (ctxt->eflags & X86_EFLAGS_OF) 5740 rc = emulate_int(ctxt, 4); 5741 break; 5742 case 0xe9: /* jmp rel */ 5743 case 0xeb: /* jmp rel short */ 5744 rc = jmp_rel(ctxt, ctxt->src.val); 5745 ctxt->dst.type = OP_NONE; /* Disable writeback. */ 5746 break; 5747 case 0xf4: /* hlt */ 5748 ctxt->ops->halt(ctxt); 5749 break; 5750 case 0xf5: /* cmc */ 5751 /* complement carry flag from eflags reg */ 5752 ctxt->eflags ^= X86_EFLAGS_CF; 5753 break; 5754 case 0xf8: /* clc */ 5755 ctxt->eflags &= ~X86_EFLAGS_CF; 5756 break; 5757 case 0xf9: /* stc */ 5758 ctxt->eflags |= X86_EFLAGS_CF; 5759 break; 5760 case 0xfc: /* cld */ 5761 ctxt->eflags &= ~X86_EFLAGS_DF; 5762 break; 5763 case 0xfd: /* std */ 5764 ctxt->eflags |= X86_EFLAGS_DF; 5765 break; 5766 default: 5767 goto cannot_emulate; 5768 } 5769 5770 if (rc != X86EMUL_CONTINUE) 5771 goto done; 5772 5773writeback: 5774 if (ctxt->d & SrcWrite) { 5775 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR); 5776 rc = writeback(ctxt, &ctxt->src); 5777 if (rc != X86EMUL_CONTINUE) 5778 goto done; 5779 } 5780 if (!(ctxt->d & NoWrite)) { 5781 rc = writeback(ctxt, &ctxt->dst); 5782 if (rc != X86EMUL_CONTINUE) 5783 goto done; 5784 } 5785 5786 /* 5787 * restore dst type in case the decoding will be reused 5788 * (happens for string instruction ) 5789 */ 5790 ctxt->dst.type = saved_dst_type; 5791 5792 if ((ctxt->d & SrcMask) == SrcSI) 5793 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src); 5794 5795 if ((ctxt->d & DstMask) == DstDI) 5796 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst); 5797 5798 if (ctxt->rep_prefix && (ctxt->d & String)) { 5799 unsigned int count; 5800 struct read_cache *r = &ctxt->io_read; 5801 if ((ctxt->d & SrcMask) == SrcSI) 5802 count = ctxt->src.count; 5803 else 5804 count = ctxt->dst.count; 5805 register_address_increment(ctxt, VCPU_REGS_RCX, -count); 5806 5807 if (!string_insn_completed(ctxt)) { 5808 /* 5809 * Re-enter guest when pio read ahead buffer is empty 5810 * or, if it is not used, after each 1024 iteration. 5811 */ 5812 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) && 5813 (r->end == 0 || r->end != r->pos)) { 5814 /* 5815 * Reset read cache. Usually happens before 5816 * decode, but since instruction is restarted 5817 * we have to do it here. 5818 */ 5819 ctxt->mem_read.end = 0; 5820 writeback_registers(ctxt); 5821 return EMULATION_RESTART; 5822 } 5823 goto done; /* skip rip writeback */ 5824 } 5825 ctxt->eflags &= ~X86_EFLAGS_RF; 5826 } 5827 5828 ctxt->eip = ctxt->_eip; 5829 if (ctxt->mode != X86EMUL_MODE_PROT64) 5830 ctxt->eip = (u32)ctxt->_eip; 5831 5832done: 5833 if (rc == X86EMUL_PROPAGATE_FAULT) { 5834 WARN_ON(ctxt->exception.vector > 0x1f); 5835 ctxt->have_exception = true; 5836 } 5837 if (rc == X86EMUL_INTERCEPTED) 5838 return EMULATION_INTERCEPTED; 5839 5840 if (rc == X86EMUL_CONTINUE) 5841 writeback_registers(ctxt); 5842 5843 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 5844 5845twobyte_insn: 5846 switch (ctxt->b) { 5847 case 0x09: /* wbinvd */ 5848 (ctxt->ops->wbinvd)(ctxt); 5849 break; 5850 case 0x08: /* invd */ 5851 case 0x0d: /* GrpP (prefetch) */ 5852 case 0x18: /* Grp16 (prefetch/nop) */ 5853 case 0x1f: /* nop */ 5854 break; 5855 case 0x20: /* mov cr, reg */ 5856 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); 5857 break; 5858 case 0x21: /* mov from dr to reg */ 5859 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); 5860 break; 5861 case 0x40 ... 0x4f: /* cmov */ 5862 if (test_cc(ctxt->b, ctxt->eflags)) 5863 ctxt->dst.val = ctxt->src.val; 5864 else if (ctxt->op_bytes != 4) 5865 ctxt->dst.type = OP_NONE; /* no writeback */ 5866 break; 5867 case 0x80 ... 0x8f: /* jnz rel, etc*/ 5868 if (test_cc(ctxt->b, ctxt->eflags)) 5869 rc = jmp_rel(ctxt, ctxt->src.val); 5870 break; 5871 case 0x90 ... 0x9f: /* setcc r/m8 */ 5872 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); 5873 break; 5874 case 0xb6 ... 0xb7: /* movzx */ 5875 ctxt->dst.bytes = ctxt->op_bytes; 5876 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val 5877 : (u16) ctxt->src.val; 5878 break; 5879 case 0xbe ... 0xbf: /* movsx */ 5880 ctxt->dst.bytes = ctxt->op_bytes; 5881 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val : 5882 (s16) ctxt->src.val; 5883 break; 5884 default: 5885 goto cannot_emulate; 5886 } 5887 5888threebyte_insn: 5889 5890 if (rc != X86EMUL_CONTINUE) 5891 goto done; 5892 5893 goto writeback; 5894 5895cannot_emulate: 5896 return EMULATION_FAILED; 5897} 5898 5899void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt) 5900{ 5901 invalidate_registers(ctxt); 5902} 5903 5904void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt) 5905{ 5906 writeback_registers(ctxt); 5907} 5908 5909bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt) 5910{ 5911 if (ctxt->rep_prefix && (ctxt->d & String)) 5912 return false; 5913 5914 if (ctxt->d & TwoMemOp) 5915 return false; 5916 5917 return true; 5918} 5919