1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Support of MSI, HPET and DMAR interrupts. 4 * 5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo 6 * Moved from arch/x86/kernel/apic/io_apic.c. 7 * Jiang Liu <jiang.liu@linux.intel.com> 8 * Convert to hierarchical irqdomain 9 */ 10#include <linux/mm.h> 11#include <linux/interrupt.h> 12#include <linux/irq.h> 13#include <linux/pci.h> 14#include <linux/dmar.h> 15#include <linux/hpet.h> 16#include <linux/msi.h> 17#include <asm/irqdomain.h> 18#include <asm/msidef.h> 19#include <asm/hpet.h> 20#include <asm/hw_irq.h> 21#include <asm/apic.h> 22#include <asm/irq_remapping.h> 23 24struct irq_domain *x86_pci_msi_default_domain __ro_after_init; 25 26static void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg) 27{ 28 msg->address_hi = MSI_ADDR_BASE_HI; 29 30 if (x2apic_enabled()) 31 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid); 32 33 msg->address_lo = 34 MSI_ADDR_BASE_LO | 35 ((apic->irq_dest_mode == 0) ? 36 MSI_ADDR_DEST_MODE_PHYSICAL : 37 MSI_ADDR_DEST_MODE_LOGICAL) | 38 MSI_ADDR_REDIRECTION_CPU | 39 MSI_ADDR_DEST_ID(cfg->dest_apicid); 40 41 msg->data = 42 MSI_DATA_TRIGGER_EDGE | 43 MSI_DATA_LEVEL_ASSERT | 44 MSI_DATA_DELIVERY_FIXED | 45 MSI_DATA_VECTOR(cfg->vector); 46} 47 48void x86_vector_msi_compose_msg(struct irq_data *data, struct msi_msg *msg) 49{ 50 __irq_msi_compose_msg(irqd_cfg(data), msg); 51} 52 53static void irq_msi_update_msg(struct irq_data *irqd, struct irq_cfg *cfg) 54{ 55 struct msi_msg msg[2] = { [1] = { }, }; 56 57 __irq_msi_compose_msg(cfg, msg); 58 irq_data_get_irq_chip(irqd)->irq_write_msi_msg(irqd, msg); 59} 60 61static int 62msi_set_affinity(struct irq_data *irqd, const struct cpumask *mask, bool force) 63{ 64 struct irq_cfg old_cfg, *cfg = irqd_cfg(irqd); 65 struct irq_data *parent = irqd->parent_data; 66 unsigned int cpu; 67 int ret; 68 69 /* Save the current configuration */ 70 cpu = cpumask_first(irq_data_get_effective_affinity_mask(irqd)); 71 old_cfg = *cfg; 72 73 /* Allocate a new target vector */ 74 ret = parent->chip->irq_set_affinity(parent, mask, force); 75 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) 76 return ret; 77 78 /* 79 * For non-maskable and non-remapped MSI interrupts the migration 80 * to a different destination CPU and a different vector has to be 81 * done careful to handle the possible stray interrupt which can be 82 * caused by the non-atomic update of the address/data pair. 83 * 84 * Direct update is possible when: 85 * - The MSI is maskable (remapped MSI does not use this code path)). 86 * The quirk bit is not set in this case. 87 * - The new vector is the same as the old vector 88 * - The old vector is MANAGED_IRQ_SHUTDOWN_VECTOR (interrupt starts up) 89 * - The interrupt is not yet started up 90 * - The new destination CPU is the same as the old destination CPU 91 */ 92 if (!irqd_msi_nomask_quirk(irqd) || 93 cfg->vector == old_cfg.vector || 94 old_cfg.vector == MANAGED_IRQ_SHUTDOWN_VECTOR || 95 !irqd_is_started(irqd) || 96 cfg->dest_apicid == old_cfg.dest_apicid) { 97 irq_msi_update_msg(irqd, cfg); 98 return ret; 99 } 100 101 /* 102 * Paranoia: Validate that the interrupt target is the local 103 * CPU. 104 */ 105 if (WARN_ON_ONCE(cpu != smp_processor_id())) { 106 irq_msi_update_msg(irqd, cfg); 107 return ret; 108 } 109 110 /* 111 * Redirect the interrupt to the new vector on the current CPU 112 * first. This might cause a spurious interrupt on this vector if 113 * the device raises an interrupt right between this update and the 114 * update to the final destination CPU. 115 * 116 * If the vector is in use then the installed device handler will 117 * denote it as spurious which is no harm as this is a rare event 118 * and interrupt handlers have to cope with spurious interrupts 119 * anyway. If the vector is unused, then it is marked so it won't 120 * trigger the 'No irq handler for vector' warning in 121 * common_interrupt(). 122 * 123 * This requires to hold vector lock to prevent concurrent updates to 124 * the affected vector. 125 */ 126 lock_vector_lock(); 127 128 /* 129 * Mark the new target vector on the local CPU if it is currently 130 * unused. Reuse the VECTOR_RETRIGGERED state which is also used in 131 * the CPU hotplug path for a similar purpose. This cannot be 132 * undone here as the current CPU has interrupts disabled and 133 * cannot handle the interrupt before the whole set_affinity() 134 * section is done. In the CPU unplug case, the current CPU is 135 * about to vanish and will not handle any interrupts anymore. The 136 * vector is cleaned up when the CPU comes online again. 137 */ 138 if (IS_ERR_OR_NULL(this_cpu_read(vector_irq[cfg->vector]))) 139 this_cpu_write(vector_irq[cfg->vector], VECTOR_RETRIGGERED); 140 141 /* Redirect it to the new vector on the local CPU temporarily */ 142 old_cfg.vector = cfg->vector; 143 irq_msi_update_msg(irqd, &old_cfg); 144 145 /* Now transition it to the target CPU */ 146 irq_msi_update_msg(irqd, cfg); 147 148 /* 149 * All interrupts after this point are now targeted at the new 150 * vector/CPU. 151 * 152 * Drop vector lock before testing whether the temporary assignment 153 * to the local CPU was hit by an interrupt raised in the device, 154 * because the retrigger function acquires vector lock again. 155 */ 156 unlock_vector_lock(); 157 158 /* 159 * Check whether the transition raced with a device interrupt and 160 * is pending in the local APICs IRR. It is safe to do this outside 161 * of vector lock as the irq_desc::lock of this interrupt is still 162 * held and interrupts are disabled: The check is not accessing the 163 * underlying vector store. It's just checking the local APIC's 164 * IRR. 165 */ 166 if (lapic_vector_set_in_irr(cfg->vector)) 167 irq_data_get_irq_chip(irqd)->irq_retrigger(irqd); 168 169 return ret; 170} 171 172/* 173 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, 174 * which implement the MSI or MSI-X Capability Structure. 175 */ 176static struct irq_chip pci_msi_controller = { 177 .name = "PCI-MSI", 178 .irq_unmask = pci_msi_unmask_irq, 179 .irq_mask = pci_msi_mask_irq, 180 .irq_ack = irq_chip_ack_parent, 181 .irq_retrigger = irq_chip_retrigger_hierarchy, 182 .irq_set_affinity = msi_set_affinity, 183 .flags = IRQCHIP_SKIP_SET_WAKE | 184 IRQCHIP_AFFINITY_PRE_STARTUP, 185}; 186 187int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec, 188 msi_alloc_info_t *arg) 189{ 190 struct pci_dev *pdev = to_pci_dev(dev); 191 struct msi_desc *desc = first_pci_msi_entry(pdev); 192 193 init_irq_alloc_info(arg, NULL); 194 if (desc->msi_attrib.is_msix) { 195 arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSIX; 196 } else { 197 arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSI; 198 arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; 199 } 200 201 return 0; 202} 203EXPORT_SYMBOL_GPL(pci_msi_prepare); 204 205static struct msi_domain_ops pci_msi_domain_ops = { 206 .msi_prepare = pci_msi_prepare, 207}; 208 209static struct msi_domain_info pci_msi_domain_info = { 210 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 211 MSI_FLAG_PCI_MSIX, 212 .ops = &pci_msi_domain_ops, 213 .chip = &pci_msi_controller, 214 .handler = handle_edge_irq, 215 .handler_name = "edge", 216}; 217 218struct irq_domain * __init native_create_pci_msi_domain(void) 219{ 220 struct fwnode_handle *fn; 221 struct irq_domain *d; 222 223 if (disable_apic) 224 return NULL; 225 226 fn = irq_domain_alloc_named_fwnode("PCI-MSI"); 227 if (!fn) 228 return NULL; 229 230 d = pci_msi_create_irq_domain(fn, &pci_msi_domain_info, 231 x86_vector_domain); 232 if (!d) { 233 irq_domain_free_fwnode(fn); 234 pr_warn("Failed to initialize PCI-MSI irqdomain.\n"); 235 } else { 236 d->flags |= IRQ_DOMAIN_MSI_NOMASK_QUIRK; 237 } 238 return d; 239} 240 241void __init x86_create_pci_msi_domain(void) 242{ 243 x86_pci_msi_default_domain = x86_init.irqs.create_pci_msi_domain(); 244} 245 246#ifdef CONFIG_IRQ_REMAP 247static struct irq_chip pci_msi_ir_controller = { 248 .name = "IR-PCI-MSI", 249 .irq_unmask = pci_msi_unmask_irq, 250 .irq_mask = pci_msi_mask_irq, 251 .irq_ack = irq_chip_ack_parent, 252 .irq_retrigger = irq_chip_retrigger_hierarchy, 253 .flags = IRQCHIP_SKIP_SET_WAKE | 254 IRQCHIP_AFFINITY_PRE_STARTUP, 255}; 256 257static struct msi_domain_info pci_msi_ir_domain_info = { 258 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 259 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX, 260 .ops = &pci_msi_domain_ops, 261 .chip = &pci_msi_ir_controller, 262 .handler = handle_edge_irq, 263 .handler_name = "edge", 264}; 265 266struct irq_domain *arch_create_remap_msi_irq_domain(struct irq_domain *parent, 267 const char *name, int id) 268{ 269 struct fwnode_handle *fn; 270 struct irq_domain *d; 271 272 fn = irq_domain_alloc_named_id_fwnode(name, id); 273 if (!fn) 274 return NULL; 275 d = pci_msi_create_irq_domain(fn, &pci_msi_ir_domain_info, parent); 276 if (!d) 277 irq_domain_free_fwnode(fn); 278 return d; 279} 280#endif 281 282#ifdef CONFIG_DMAR_TABLE 283static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg) 284{ 285 dmar_msi_write(data->irq, msg); 286} 287 288static struct irq_chip dmar_msi_controller = { 289 .name = "DMAR-MSI", 290 .irq_unmask = dmar_msi_unmask, 291 .irq_mask = dmar_msi_mask, 292 .irq_ack = irq_chip_ack_parent, 293 .irq_set_affinity = msi_domain_set_affinity, 294 .irq_retrigger = irq_chip_retrigger_hierarchy, 295 .irq_write_msi_msg = dmar_msi_write_msg, 296 .flags = IRQCHIP_SKIP_SET_WAKE | 297 IRQCHIP_AFFINITY_PRE_STARTUP, 298}; 299 300static int dmar_msi_init(struct irq_domain *domain, 301 struct msi_domain_info *info, unsigned int virq, 302 irq_hw_number_t hwirq, msi_alloc_info_t *arg) 303{ 304 irq_domain_set_info(domain, virq, arg->devid, info->chip, NULL, 305 handle_edge_irq, arg->data, "edge"); 306 307 return 0; 308} 309 310static struct msi_domain_ops dmar_msi_domain_ops = { 311 .msi_init = dmar_msi_init, 312}; 313 314static struct msi_domain_info dmar_msi_domain_info = { 315 .ops = &dmar_msi_domain_ops, 316 .chip = &dmar_msi_controller, 317 .flags = MSI_FLAG_USE_DEF_DOM_OPS, 318}; 319 320static struct irq_domain *dmar_get_irq_domain(void) 321{ 322 static struct irq_domain *dmar_domain; 323 static DEFINE_MUTEX(dmar_lock); 324 struct fwnode_handle *fn; 325 326 mutex_lock(&dmar_lock); 327 if (dmar_domain) 328 goto out; 329 330 fn = irq_domain_alloc_named_fwnode("DMAR-MSI"); 331 if (fn) { 332 dmar_domain = msi_create_irq_domain(fn, &dmar_msi_domain_info, 333 x86_vector_domain); 334 if (!dmar_domain) 335 irq_domain_free_fwnode(fn); 336 } 337out: 338 mutex_unlock(&dmar_lock); 339 return dmar_domain; 340} 341 342int dmar_alloc_hwirq(int id, int node, void *arg) 343{ 344 struct irq_domain *domain = dmar_get_irq_domain(); 345 struct irq_alloc_info info; 346 347 if (!domain) 348 return -1; 349 350 init_irq_alloc_info(&info, NULL); 351 info.type = X86_IRQ_ALLOC_TYPE_DMAR; 352 info.devid = id; 353 info.hwirq = id; 354 info.data = arg; 355 356 return irq_domain_alloc_irqs(domain, 1, node, &info); 357} 358 359void dmar_free_hwirq(int irq) 360{ 361 irq_domain_free_irqs(irq, 1); 362} 363#endif 364 365/* 366 * MSI message composition 367 */ 368#ifdef CONFIG_HPET_TIMER 369static inline int hpet_dev_id(struct irq_domain *domain) 370{ 371 struct msi_domain_info *info = msi_get_domain_info(domain); 372 373 return (int)(long)info->data; 374} 375 376static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg) 377{ 378 hpet_msi_write(irq_data_get_irq_handler_data(data), msg); 379} 380 381static struct irq_chip hpet_msi_controller __ro_after_init = { 382 .name = "HPET-MSI", 383 .irq_unmask = hpet_msi_unmask, 384 .irq_mask = hpet_msi_mask, 385 .irq_ack = irq_chip_ack_parent, 386 .irq_set_affinity = msi_domain_set_affinity, 387 .irq_retrigger = irq_chip_retrigger_hierarchy, 388 .irq_write_msi_msg = hpet_msi_write_msg, 389 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_AFFINITY_PRE_STARTUP, 390}; 391 392static int hpet_msi_init(struct irq_domain *domain, 393 struct msi_domain_info *info, unsigned int virq, 394 irq_hw_number_t hwirq, msi_alloc_info_t *arg) 395{ 396 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT); 397 irq_domain_set_info(domain, virq, arg->hwirq, info->chip, NULL, 398 handle_edge_irq, arg->data, "edge"); 399 400 return 0; 401} 402 403static void hpet_msi_free(struct irq_domain *domain, 404 struct msi_domain_info *info, unsigned int virq) 405{ 406 irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT); 407} 408 409static struct msi_domain_ops hpet_msi_domain_ops = { 410 .msi_init = hpet_msi_init, 411 .msi_free = hpet_msi_free, 412}; 413 414static struct msi_domain_info hpet_msi_domain_info = { 415 .ops = &hpet_msi_domain_ops, 416 .chip = &hpet_msi_controller, 417 .flags = MSI_FLAG_USE_DEF_DOM_OPS, 418}; 419 420struct irq_domain *hpet_create_irq_domain(int hpet_id) 421{ 422 struct msi_domain_info *domain_info; 423 struct irq_domain *parent, *d; 424 struct irq_alloc_info info; 425 struct fwnode_handle *fn; 426 427 if (x86_vector_domain == NULL) 428 return NULL; 429 430 domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL); 431 if (!domain_info) 432 return NULL; 433 434 *domain_info = hpet_msi_domain_info; 435 domain_info->data = (void *)(long)hpet_id; 436 437 init_irq_alloc_info(&info, NULL); 438 info.type = X86_IRQ_ALLOC_TYPE_HPET_GET_PARENT; 439 info.devid = hpet_id; 440 parent = irq_remapping_get_irq_domain(&info); 441 if (parent == NULL) 442 parent = x86_vector_domain; 443 else 444 hpet_msi_controller.name = "IR-HPET-MSI"; 445 446 fn = irq_domain_alloc_named_id_fwnode(hpet_msi_controller.name, 447 hpet_id); 448 if (!fn) { 449 kfree(domain_info); 450 return NULL; 451 } 452 453 d = msi_create_irq_domain(fn, domain_info, parent); 454 if (!d) { 455 irq_domain_free_fwnode(fn); 456 kfree(domain_info); 457 } 458 return d; 459} 460 461int hpet_assign_irq(struct irq_domain *domain, struct hpet_channel *hc, 462 int dev_num) 463{ 464 struct irq_alloc_info info; 465 466 init_irq_alloc_info(&info, NULL); 467 info.type = X86_IRQ_ALLOC_TYPE_HPET; 468 info.data = hc; 469 info.devid = hpet_dev_id(domain); 470 info.hwirq = dev_num; 471 472 return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info); 473} 474#endif 475