18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */
28c2ecf20Sopenharmony_ci#ifndef _ASM_X86_PLATFORM_H
38c2ecf20Sopenharmony_ci#define _ASM_X86_PLATFORM_H
48c2ecf20Sopenharmony_ci
58c2ecf20Sopenharmony_ci#include <asm/bootparam.h>
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_cistruct ghcb;
88c2ecf20Sopenharmony_cistruct mpc_bus;
98c2ecf20Sopenharmony_cistruct mpc_cpu;
108c2ecf20Sopenharmony_cistruct pt_regs;
118c2ecf20Sopenharmony_cistruct mpc_table;
128c2ecf20Sopenharmony_cistruct cpuinfo_x86;
138c2ecf20Sopenharmony_cistruct irq_domain;
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_ci/**
168c2ecf20Sopenharmony_ci * struct x86_init_mpparse - platform specific mpparse ops
178c2ecf20Sopenharmony_ci * @setup_ioapic_ids:		platform specific ioapic id override
188c2ecf20Sopenharmony_ci * @find_smp_config:		find the smp configuration
198c2ecf20Sopenharmony_ci * @get_smp_config:		get the smp configuration
208c2ecf20Sopenharmony_ci */
218c2ecf20Sopenharmony_cistruct x86_init_mpparse {
228c2ecf20Sopenharmony_ci	void (*setup_ioapic_ids)(void);
238c2ecf20Sopenharmony_ci	void (*find_smp_config)(void);
248c2ecf20Sopenharmony_ci	void (*get_smp_config)(unsigned int early);
258c2ecf20Sopenharmony_ci};
268c2ecf20Sopenharmony_ci
278c2ecf20Sopenharmony_ci/**
288c2ecf20Sopenharmony_ci * struct x86_init_resources - platform specific resource related ops
298c2ecf20Sopenharmony_ci * @probe_roms:			probe BIOS roms
308c2ecf20Sopenharmony_ci * @reserve_resources:		reserve the standard resources for the
318c2ecf20Sopenharmony_ci *				platform
328c2ecf20Sopenharmony_ci * @memory_setup:		platform specific memory setup
338c2ecf20Sopenharmony_ci *
348c2ecf20Sopenharmony_ci */
358c2ecf20Sopenharmony_cistruct x86_init_resources {
368c2ecf20Sopenharmony_ci	void (*probe_roms)(void);
378c2ecf20Sopenharmony_ci	void (*reserve_resources)(void);
388c2ecf20Sopenharmony_ci	char *(*memory_setup)(void);
398c2ecf20Sopenharmony_ci};
408c2ecf20Sopenharmony_ci
418c2ecf20Sopenharmony_ci/**
428c2ecf20Sopenharmony_ci * struct x86_init_irqs - platform specific interrupt setup
438c2ecf20Sopenharmony_ci * @pre_vector_init:		init code to run before interrupt vectors
448c2ecf20Sopenharmony_ci *				are set up.
458c2ecf20Sopenharmony_ci * @intr_init:			interrupt init code
468c2ecf20Sopenharmony_ci * @intr_mode_select:		interrupt delivery mode selection
478c2ecf20Sopenharmony_ci * @intr_mode_init:		interrupt delivery mode setup
488c2ecf20Sopenharmony_ci * @create_pci_msi_domain:	Create the PCI/MSI interrupt domain
498c2ecf20Sopenharmony_ci */
508c2ecf20Sopenharmony_cistruct x86_init_irqs {
518c2ecf20Sopenharmony_ci	void (*pre_vector_init)(void);
528c2ecf20Sopenharmony_ci	void (*intr_init)(void);
538c2ecf20Sopenharmony_ci	void (*intr_mode_select)(void);
548c2ecf20Sopenharmony_ci	void (*intr_mode_init)(void);
558c2ecf20Sopenharmony_ci	struct irq_domain *(*create_pci_msi_domain)(void);
568c2ecf20Sopenharmony_ci};
578c2ecf20Sopenharmony_ci
588c2ecf20Sopenharmony_ci/**
598c2ecf20Sopenharmony_ci * struct x86_init_oem - oem platform specific customizing functions
608c2ecf20Sopenharmony_ci * @arch_setup:			platform specific architecture setup
618c2ecf20Sopenharmony_ci * @banner:			print a platform specific banner
628c2ecf20Sopenharmony_ci */
638c2ecf20Sopenharmony_cistruct x86_init_oem {
648c2ecf20Sopenharmony_ci	void (*arch_setup)(void);
658c2ecf20Sopenharmony_ci	void (*banner)(void);
668c2ecf20Sopenharmony_ci};
678c2ecf20Sopenharmony_ci
688c2ecf20Sopenharmony_ci/**
698c2ecf20Sopenharmony_ci * struct x86_init_paging - platform specific paging functions
708c2ecf20Sopenharmony_ci * @pagetable_init:	platform specific paging initialization call to setup
718c2ecf20Sopenharmony_ci *			the kernel pagetables and prepare accessors functions.
728c2ecf20Sopenharmony_ci *			Callback must call paging_init(). Called once after the
738c2ecf20Sopenharmony_ci *			direct mapping for phys memory is available.
748c2ecf20Sopenharmony_ci */
758c2ecf20Sopenharmony_cistruct x86_init_paging {
768c2ecf20Sopenharmony_ci	void (*pagetable_init)(void);
778c2ecf20Sopenharmony_ci};
788c2ecf20Sopenharmony_ci
798c2ecf20Sopenharmony_ci/**
808c2ecf20Sopenharmony_ci * struct x86_init_timers - platform specific timer setup
818c2ecf20Sopenharmony_ci * @setup_perpcu_clockev:	set up the per cpu clock event device for the
828c2ecf20Sopenharmony_ci *				boot cpu
838c2ecf20Sopenharmony_ci * @timer_init:			initialize the platform timer (default PIT/HPET)
848c2ecf20Sopenharmony_ci * @wallclock_init:		init the wallclock device
858c2ecf20Sopenharmony_ci */
868c2ecf20Sopenharmony_cistruct x86_init_timers {
878c2ecf20Sopenharmony_ci	void (*setup_percpu_clockev)(void);
888c2ecf20Sopenharmony_ci	void (*timer_init)(void);
898c2ecf20Sopenharmony_ci	void (*wallclock_init)(void);
908c2ecf20Sopenharmony_ci};
918c2ecf20Sopenharmony_ci
928c2ecf20Sopenharmony_ci/**
938c2ecf20Sopenharmony_ci * struct x86_init_iommu - platform specific iommu setup
948c2ecf20Sopenharmony_ci * @iommu_init:			platform specific iommu setup
958c2ecf20Sopenharmony_ci */
968c2ecf20Sopenharmony_cistruct x86_init_iommu {
978c2ecf20Sopenharmony_ci	int (*iommu_init)(void);
988c2ecf20Sopenharmony_ci};
998c2ecf20Sopenharmony_ci
1008c2ecf20Sopenharmony_ci/**
1018c2ecf20Sopenharmony_ci * struct x86_init_pci - platform specific pci init functions
1028c2ecf20Sopenharmony_ci * @arch_init:			platform specific pci arch init call
1038c2ecf20Sopenharmony_ci * @init:			platform specific pci subsystem init
1048c2ecf20Sopenharmony_ci * @init_irq:			platform specific pci irq init
1058c2ecf20Sopenharmony_ci * @fixup_irqs:			platform specific pci irq fixup
1068c2ecf20Sopenharmony_ci */
1078c2ecf20Sopenharmony_cistruct x86_init_pci {
1088c2ecf20Sopenharmony_ci	int (*arch_init)(void);
1098c2ecf20Sopenharmony_ci	int (*init)(void);
1108c2ecf20Sopenharmony_ci	void (*init_irq)(void);
1118c2ecf20Sopenharmony_ci	void (*fixup_irqs)(void);
1128c2ecf20Sopenharmony_ci};
1138c2ecf20Sopenharmony_ci
1148c2ecf20Sopenharmony_ci/**
1158c2ecf20Sopenharmony_ci * struct x86_hyper_init - x86 hypervisor init functions
1168c2ecf20Sopenharmony_ci * @init_platform:		platform setup
1178c2ecf20Sopenharmony_ci * @guest_late_init:		guest late init
1188c2ecf20Sopenharmony_ci * @x2apic_available:		X2APIC detection
1198c2ecf20Sopenharmony_ci * @init_mem_mapping:		setup early mappings during init_mem_mapping()
1208c2ecf20Sopenharmony_ci * @init_after_bootmem:		guest init after boot allocator is finished
1218c2ecf20Sopenharmony_ci */
1228c2ecf20Sopenharmony_cistruct x86_hyper_init {
1238c2ecf20Sopenharmony_ci	void (*init_platform)(void);
1248c2ecf20Sopenharmony_ci	void (*guest_late_init)(void);
1258c2ecf20Sopenharmony_ci	bool (*x2apic_available)(void);
1268c2ecf20Sopenharmony_ci	void (*init_mem_mapping)(void);
1278c2ecf20Sopenharmony_ci	void (*init_after_bootmem)(void);
1288c2ecf20Sopenharmony_ci};
1298c2ecf20Sopenharmony_ci
1308c2ecf20Sopenharmony_ci/**
1318c2ecf20Sopenharmony_ci * struct x86_init_acpi - x86 ACPI init functions
1328c2ecf20Sopenharmony_ci * @set_root_poitner:		set RSDP address
1338c2ecf20Sopenharmony_ci * @get_root_pointer:		get RSDP address
1348c2ecf20Sopenharmony_ci * @reduced_hw_early_init:	hardware reduced platform early init
1358c2ecf20Sopenharmony_ci */
1368c2ecf20Sopenharmony_cistruct x86_init_acpi {
1378c2ecf20Sopenharmony_ci	void (*set_root_pointer)(u64 addr);
1388c2ecf20Sopenharmony_ci	u64 (*get_root_pointer)(void);
1398c2ecf20Sopenharmony_ci	void (*reduced_hw_early_init)(void);
1408c2ecf20Sopenharmony_ci};
1418c2ecf20Sopenharmony_ci
1428c2ecf20Sopenharmony_ci/**
1438c2ecf20Sopenharmony_ci * struct x86_init_ops - functions for platform specific setup
1448c2ecf20Sopenharmony_ci *
1458c2ecf20Sopenharmony_ci */
1468c2ecf20Sopenharmony_cistruct x86_init_ops {
1478c2ecf20Sopenharmony_ci	struct x86_init_resources	resources;
1488c2ecf20Sopenharmony_ci	struct x86_init_mpparse		mpparse;
1498c2ecf20Sopenharmony_ci	struct x86_init_irqs		irqs;
1508c2ecf20Sopenharmony_ci	struct x86_init_oem		oem;
1518c2ecf20Sopenharmony_ci	struct x86_init_paging		paging;
1528c2ecf20Sopenharmony_ci	struct x86_init_timers		timers;
1538c2ecf20Sopenharmony_ci	struct x86_init_iommu		iommu;
1548c2ecf20Sopenharmony_ci	struct x86_init_pci		pci;
1558c2ecf20Sopenharmony_ci	struct x86_hyper_init		hyper;
1568c2ecf20Sopenharmony_ci	struct x86_init_acpi		acpi;
1578c2ecf20Sopenharmony_ci};
1588c2ecf20Sopenharmony_ci
1598c2ecf20Sopenharmony_ci/**
1608c2ecf20Sopenharmony_ci * struct x86_cpuinit_ops - platform specific cpu hotplug setups
1618c2ecf20Sopenharmony_ci * @setup_percpu_clockev:	set up the per cpu clock event device
1628c2ecf20Sopenharmony_ci * @early_percpu_clock_init:	early init of the per cpu clock event device
1638c2ecf20Sopenharmony_ci */
1648c2ecf20Sopenharmony_cistruct x86_cpuinit_ops {
1658c2ecf20Sopenharmony_ci	void (*setup_percpu_clockev)(void);
1668c2ecf20Sopenharmony_ci	void (*early_percpu_clock_init)(void);
1678c2ecf20Sopenharmony_ci	void (*fixup_cpu_id)(struct cpuinfo_x86 *c, int node);
1688c2ecf20Sopenharmony_ci};
1698c2ecf20Sopenharmony_ci
1708c2ecf20Sopenharmony_cistruct timespec64;
1718c2ecf20Sopenharmony_ci
1728c2ecf20Sopenharmony_ci/**
1738c2ecf20Sopenharmony_ci * struct x86_legacy_devices - legacy x86 devices
1748c2ecf20Sopenharmony_ci *
1758c2ecf20Sopenharmony_ci * @pnpbios: this platform can have a PNPBIOS. If this is disabled the platform
1768c2ecf20Sopenharmony_ci * 	is known to never have a PNPBIOS.
1778c2ecf20Sopenharmony_ci *
1788c2ecf20Sopenharmony_ci * These are devices known to require LPC or ISA bus. The definition of legacy
1798c2ecf20Sopenharmony_ci * devices adheres to the ACPI 5.2.9.3 IA-PC Boot Architecture flag
1808c2ecf20Sopenharmony_ci * ACPI_FADT_LEGACY_DEVICES. These devices consist of user visible devices on
1818c2ecf20Sopenharmony_ci * the LPC or ISA bus. User visible devices are devices that have end-user
1828c2ecf20Sopenharmony_ci * accessible connectors (for example, LPT parallel port). Legacy devices on
1838c2ecf20Sopenharmony_ci * the LPC bus consist for example of serial and parallel ports, PS/2 keyboard
1848c2ecf20Sopenharmony_ci * / mouse, and the floppy disk controller. A system that lacks all known
1858c2ecf20Sopenharmony_ci * legacy devices can assume all devices can be detected exclusively via
1868c2ecf20Sopenharmony_ci * standard device enumeration mechanisms including the ACPI namespace.
1878c2ecf20Sopenharmony_ci *
1888c2ecf20Sopenharmony_ci * A system which has does not have ACPI_FADT_LEGACY_DEVICES enabled must not
1898c2ecf20Sopenharmony_ci * have any of the legacy devices enumerated below present.
1908c2ecf20Sopenharmony_ci */
1918c2ecf20Sopenharmony_cistruct x86_legacy_devices {
1928c2ecf20Sopenharmony_ci	int pnpbios;
1938c2ecf20Sopenharmony_ci};
1948c2ecf20Sopenharmony_ci
1958c2ecf20Sopenharmony_ci/**
1968c2ecf20Sopenharmony_ci * enum x86_legacy_i8042_state - i8042 keyboard controller state
1978c2ecf20Sopenharmony_ci * @X86_LEGACY_I8042_PLATFORM_ABSENT: the controller is always absent on
1988c2ecf20Sopenharmony_ci *	given platform/subarch.
1998c2ecf20Sopenharmony_ci * @X86_LEGACY_I8042_FIRMWARE_ABSENT: firmware reports that the controller
2008c2ecf20Sopenharmony_ci *	is absent.
2018c2ecf20Sopenharmony_ci * @X86_LEGACY_i8042_EXPECTED_PRESENT: the controller is likely to be
2028c2ecf20Sopenharmony_ci *	present, the i8042 driver should probe for controller existence.
2038c2ecf20Sopenharmony_ci */
2048c2ecf20Sopenharmony_cienum x86_legacy_i8042_state {
2058c2ecf20Sopenharmony_ci	X86_LEGACY_I8042_PLATFORM_ABSENT,
2068c2ecf20Sopenharmony_ci	X86_LEGACY_I8042_FIRMWARE_ABSENT,
2078c2ecf20Sopenharmony_ci	X86_LEGACY_I8042_EXPECTED_PRESENT,
2088c2ecf20Sopenharmony_ci};
2098c2ecf20Sopenharmony_ci
2108c2ecf20Sopenharmony_ci/**
2118c2ecf20Sopenharmony_ci * struct x86_legacy_features - legacy x86 features
2128c2ecf20Sopenharmony_ci *
2138c2ecf20Sopenharmony_ci * @i8042: indicated if we expect the device to have i8042 controller
2148c2ecf20Sopenharmony_ci *	present.
2158c2ecf20Sopenharmony_ci * @rtc: this device has a CMOS real-time clock present
2168c2ecf20Sopenharmony_ci * @reserve_bios_regions: boot code will search for the EBDA address and the
2178c2ecf20Sopenharmony_ci * 	start of the 640k - 1M BIOS region.  If false, the platform must
2188c2ecf20Sopenharmony_ci * 	ensure that its memory map correctly reserves sub-1MB regions as needed.
2198c2ecf20Sopenharmony_ci * @devices: legacy x86 devices, refer to struct x86_legacy_devices
2208c2ecf20Sopenharmony_ci * 	documentation for further details.
2218c2ecf20Sopenharmony_ci */
2228c2ecf20Sopenharmony_cistruct x86_legacy_features {
2238c2ecf20Sopenharmony_ci	enum x86_legacy_i8042_state i8042;
2248c2ecf20Sopenharmony_ci	int rtc;
2258c2ecf20Sopenharmony_ci	int warm_reset;
2268c2ecf20Sopenharmony_ci	int no_vga;
2278c2ecf20Sopenharmony_ci	int reserve_bios_regions;
2288c2ecf20Sopenharmony_ci	struct x86_legacy_devices devices;
2298c2ecf20Sopenharmony_ci};
2308c2ecf20Sopenharmony_ci
2318c2ecf20Sopenharmony_ci/**
2328c2ecf20Sopenharmony_ci * struct x86_hyper_runtime - x86 hypervisor specific runtime callbacks
2338c2ecf20Sopenharmony_ci *
2348c2ecf20Sopenharmony_ci * @pin_vcpu:			pin current vcpu to specified physical
2358c2ecf20Sopenharmony_ci *				cpu (run rarely)
2368c2ecf20Sopenharmony_ci * @sev_es_hcall_prepare:	Load additional hypervisor-specific
2378c2ecf20Sopenharmony_ci *				state into the GHCB when doing a VMMCALL under
2388c2ecf20Sopenharmony_ci *				SEV-ES. Called from the #VC exception handler.
2398c2ecf20Sopenharmony_ci * @sev_es_hcall_finish:	Copies state from the GHCB back into the
2408c2ecf20Sopenharmony_ci *				processor (or pt_regs). Also runs checks on the
2418c2ecf20Sopenharmony_ci *				state returned from the hypervisor after a
2428c2ecf20Sopenharmony_ci *				VMMCALL under SEV-ES.  Needs to return 'false'
2438c2ecf20Sopenharmony_ci *				if the checks fail.  Called from the #VC
2448c2ecf20Sopenharmony_ci *				exception handler.
2458c2ecf20Sopenharmony_ci */
2468c2ecf20Sopenharmony_cistruct x86_hyper_runtime {
2478c2ecf20Sopenharmony_ci	void (*pin_vcpu)(int cpu);
2488c2ecf20Sopenharmony_ci	void (*sev_es_hcall_prepare)(struct ghcb *ghcb, struct pt_regs *regs);
2498c2ecf20Sopenharmony_ci	bool (*sev_es_hcall_finish)(struct ghcb *ghcb, struct pt_regs *regs);
2508c2ecf20Sopenharmony_ci};
2518c2ecf20Sopenharmony_ci
2528c2ecf20Sopenharmony_ci/**
2538c2ecf20Sopenharmony_ci * struct x86_platform_ops - platform specific runtime functions
2548c2ecf20Sopenharmony_ci * @calibrate_cpu:		calibrate CPU
2558c2ecf20Sopenharmony_ci * @calibrate_tsc:		calibrate TSC, if different from CPU
2568c2ecf20Sopenharmony_ci * @get_wallclock:		get time from HW clock like RTC etc.
2578c2ecf20Sopenharmony_ci * @set_wallclock:		set time back to HW clock
2588c2ecf20Sopenharmony_ci * @is_untracked_pat_range	exclude from PAT logic
2598c2ecf20Sopenharmony_ci * @nmi_init			enable NMI on cpus
2608c2ecf20Sopenharmony_ci * @save_sched_clock_state:	save state for sched_clock() on suspend
2618c2ecf20Sopenharmony_ci * @restore_sched_clock_state:	restore state for sched_clock() on resume
2628c2ecf20Sopenharmony_ci * @apic_post_init:		adjust apic if needed
2638c2ecf20Sopenharmony_ci * @legacy:			legacy features
2648c2ecf20Sopenharmony_ci * @set_legacy_features:	override legacy features. Use of this callback
2658c2ecf20Sopenharmony_ci * 				is highly discouraged. You should only need
2668c2ecf20Sopenharmony_ci * 				this if your hardware platform requires further
2678c2ecf20Sopenharmony_ci * 				custom fine tuning far beyond what may be
2688c2ecf20Sopenharmony_ci * 				possible in x86_early_init_platform_quirks() by
2698c2ecf20Sopenharmony_ci * 				only using the current x86_hardware_subarch
2708c2ecf20Sopenharmony_ci * 				semantics.
2718c2ecf20Sopenharmony_ci * @hyper:			x86 hypervisor specific runtime callbacks
2728c2ecf20Sopenharmony_ci */
2738c2ecf20Sopenharmony_cistruct x86_platform_ops {
2748c2ecf20Sopenharmony_ci	unsigned long (*calibrate_cpu)(void);
2758c2ecf20Sopenharmony_ci	unsigned long (*calibrate_tsc)(void);
2768c2ecf20Sopenharmony_ci	void (*get_wallclock)(struct timespec64 *ts);
2778c2ecf20Sopenharmony_ci	int (*set_wallclock)(const struct timespec64 *ts);
2788c2ecf20Sopenharmony_ci	void (*iommu_shutdown)(void);
2798c2ecf20Sopenharmony_ci	bool (*is_untracked_pat_range)(u64 start, u64 end);
2808c2ecf20Sopenharmony_ci	void (*nmi_init)(void);
2818c2ecf20Sopenharmony_ci	unsigned char (*get_nmi_reason)(void);
2828c2ecf20Sopenharmony_ci	void (*save_sched_clock_state)(void);
2838c2ecf20Sopenharmony_ci	void (*restore_sched_clock_state)(void);
2848c2ecf20Sopenharmony_ci	void (*apic_post_init)(void);
2858c2ecf20Sopenharmony_ci	struct x86_legacy_features legacy;
2868c2ecf20Sopenharmony_ci	void (*set_legacy_features)(void);
2878c2ecf20Sopenharmony_ci	struct x86_hyper_runtime hyper;
2888c2ecf20Sopenharmony_ci};
2898c2ecf20Sopenharmony_ci
2908c2ecf20Sopenharmony_cistruct pci_dev;
2918c2ecf20Sopenharmony_ci
2928c2ecf20Sopenharmony_cistruct x86_msi_ops {
2938c2ecf20Sopenharmony_ci	void (*restore_msi_irqs)(struct pci_dev *dev);
2948c2ecf20Sopenharmony_ci};
2958c2ecf20Sopenharmony_ci
2968c2ecf20Sopenharmony_cistruct x86_apic_ops {
2978c2ecf20Sopenharmony_ci	unsigned int	(*io_apic_read)   (unsigned int apic, unsigned int reg);
2988c2ecf20Sopenharmony_ci	void		(*restore)(void);
2998c2ecf20Sopenharmony_ci};
3008c2ecf20Sopenharmony_ci
3018c2ecf20Sopenharmony_ciextern struct x86_init_ops x86_init;
3028c2ecf20Sopenharmony_ciextern struct x86_cpuinit_ops x86_cpuinit;
3038c2ecf20Sopenharmony_ciextern struct x86_platform_ops x86_platform;
3048c2ecf20Sopenharmony_ciextern struct x86_msi_ops x86_msi;
3058c2ecf20Sopenharmony_ciextern struct x86_apic_ops x86_apic_ops;
3068c2ecf20Sopenharmony_ci
3078c2ecf20Sopenharmony_ciextern void x86_early_init_platform_quirks(void);
3088c2ecf20Sopenharmony_ciextern void x86_init_noop(void);
3098c2ecf20Sopenharmony_ciextern void x86_init_uint_noop(unsigned int unused);
3108c2ecf20Sopenharmony_ciextern bool bool_x86_init_noop(void);
3118c2ecf20Sopenharmony_ciextern void x86_op_int_noop(int cpu);
3128c2ecf20Sopenharmony_ciextern bool x86_pnpbios_disabled(void);
3138c2ecf20Sopenharmony_ci
3148c2ecf20Sopenharmony_ci#endif
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