18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * x86 TSC related functions 48c2ecf20Sopenharmony_ci */ 58c2ecf20Sopenharmony_ci#ifndef _ASM_X86_TSC_H 68c2ecf20Sopenharmony_ci#define _ASM_X86_TSC_H 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci#include <asm/processor.h> 98c2ecf20Sopenharmony_ci#include <asm/cpufeature.h> 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci/* 128c2ecf20Sopenharmony_ci * Standard way to access the cycle counter. 138c2ecf20Sopenharmony_ci */ 148c2ecf20Sopenharmony_citypedef unsigned long long cycles_t; 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ciextern unsigned int cpu_khz; 178c2ecf20Sopenharmony_ciextern unsigned int tsc_khz; 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ciextern void disable_TSC(void); 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_cistatic inline cycles_t get_cycles(void) 228c2ecf20Sopenharmony_ci{ 238c2ecf20Sopenharmony_ci if (!IS_ENABLED(CONFIG_X86_TSC) && 248c2ecf20Sopenharmony_ci !cpu_feature_enabled(X86_FEATURE_TSC)) 258c2ecf20Sopenharmony_ci return 0; 268c2ecf20Sopenharmony_ci return rdtsc(); 278c2ecf20Sopenharmony_ci} 288c2ecf20Sopenharmony_ci#define get_cycles get_cycles 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_ciextern struct system_counterval_t convert_art_to_tsc(u64 art); 318c2ecf20Sopenharmony_ciextern struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns); 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ciextern void tsc_early_init(void); 348c2ecf20Sopenharmony_ciextern void tsc_init(void); 358c2ecf20Sopenharmony_ciextern unsigned long calibrate_delay_is_known(void); 368c2ecf20Sopenharmony_ciextern void mark_tsc_unstable(char *reason); 378c2ecf20Sopenharmony_ciextern int unsynchronized_tsc(void); 388c2ecf20Sopenharmony_ciextern int check_tsc_unstable(void); 398c2ecf20Sopenharmony_ciextern void mark_tsc_async_resets(char *reason); 408c2ecf20Sopenharmony_ciextern unsigned long native_calibrate_cpu_early(void); 418c2ecf20Sopenharmony_ciextern unsigned long native_calibrate_tsc(void); 428c2ecf20Sopenharmony_ciextern unsigned long long native_sched_clock_from_tsc(u64 tsc); 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ciextern int tsc_clocksource_reliable; 458c2ecf20Sopenharmony_ci#ifdef CONFIG_X86_TSC 468c2ecf20Sopenharmony_ciextern bool tsc_async_resets; 478c2ecf20Sopenharmony_ci#else 488c2ecf20Sopenharmony_ci# define tsc_async_resets false 498c2ecf20Sopenharmony_ci#endif 508c2ecf20Sopenharmony_ci 518c2ecf20Sopenharmony_ci/* 528c2ecf20Sopenharmony_ci * Boot-time check whether the TSCs are synchronized across 538c2ecf20Sopenharmony_ci * all CPUs/cores: 548c2ecf20Sopenharmony_ci */ 558c2ecf20Sopenharmony_ci#ifdef CONFIG_X86_TSC 568c2ecf20Sopenharmony_ciextern bool tsc_store_and_check_tsc_adjust(bool bootcpu); 578c2ecf20Sopenharmony_ciextern void tsc_verify_tsc_adjust(bool resume); 588c2ecf20Sopenharmony_ciextern void check_tsc_sync_source(int cpu); 598c2ecf20Sopenharmony_ciextern void check_tsc_sync_target(void); 608c2ecf20Sopenharmony_ci#else 618c2ecf20Sopenharmony_cistatic inline bool tsc_store_and_check_tsc_adjust(bool bootcpu) { return false; } 628c2ecf20Sopenharmony_cistatic inline void tsc_verify_tsc_adjust(bool resume) { } 638c2ecf20Sopenharmony_cistatic inline void check_tsc_sync_source(int cpu) { } 648c2ecf20Sopenharmony_cistatic inline void check_tsc_sync_target(void) { } 658c2ecf20Sopenharmony_ci#endif 668c2ecf20Sopenharmony_ci 678c2ecf20Sopenharmony_ciextern int notsc_setup(char *); 688c2ecf20Sopenharmony_ciextern void tsc_save_sched_clock_state(void); 698c2ecf20Sopenharmony_ciextern void tsc_restore_sched_clock_state(void); 708c2ecf20Sopenharmony_ci 718c2ecf20Sopenharmony_ciunsigned long cpu_khz_from_msr(void); 728c2ecf20Sopenharmony_ci 738c2ecf20Sopenharmony_ci#endif /* _ASM_X86_TSC_H */ 74