18c2ecf20Sopenharmony_ci#ifndef _ASM_X86_PGTABLE_AREAS_H 28c2ecf20Sopenharmony_ci#define _ASM_X86_PGTABLE_AREAS_H 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ci#ifdef CONFIG_X86_32 58c2ecf20Sopenharmony_ci# include <asm/pgtable_32_areas.h> 68c2ecf20Sopenharmony_ci#endif 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci/* Single page reserved for the readonly IDT mapping: */ 98c2ecf20Sopenharmony_ci#define CPU_ENTRY_AREA_RO_IDT CPU_ENTRY_AREA_BASE 108c2ecf20Sopenharmony_ci#define CPU_ENTRY_AREA_PER_CPU (CPU_ENTRY_AREA_RO_IDT + PAGE_SIZE) 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci#define CPU_ENTRY_AREA_RO_IDT_VADDR ((void *)CPU_ENTRY_AREA_RO_IDT) 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci#ifdef CONFIG_X86_32 158c2ecf20Sopenharmony_ci#define CPU_ENTRY_AREA_MAP_SIZE (CPU_ENTRY_AREA_PER_CPU + \ 168c2ecf20Sopenharmony_ci (CPU_ENTRY_AREA_SIZE * NR_CPUS) - \ 178c2ecf20Sopenharmony_ci CPU_ENTRY_AREA_BASE) 188c2ecf20Sopenharmony_ci#else 198c2ecf20Sopenharmony_ci#define CPU_ENTRY_AREA_MAP_SIZE P4D_SIZE 208c2ecf20Sopenharmony_ci#endif 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci#endif /* _ASM_X86_PGTABLE_AREAS_H */ 23