18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */
28c2ecf20Sopenharmony_ci#ifndef _ASM_X86_IRQ_VECTORS_H
38c2ecf20Sopenharmony_ci#define _ASM_X86_IRQ_VECTORS_H
48c2ecf20Sopenharmony_ci
58c2ecf20Sopenharmony_ci#include <linux/threads.h>
68c2ecf20Sopenharmony_ci/*
78c2ecf20Sopenharmony_ci * Linux IRQ vector layout.
88c2ecf20Sopenharmony_ci *
98c2ecf20Sopenharmony_ci * There are 256 IDT entries (per CPU - each entry is 8 bytes) which can
108c2ecf20Sopenharmony_ci * be defined by Linux. They are used as a jump table by the CPU when a
118c2ecf20Sopenharmony_ci * given vector is triggered - by a CPU-external, CPU-internal or
128c2ecf20Sopenharmony_ci * software-triggered event.
138c2ecf20Sopenharmony_ci *
148c2ecf20Sopenharmony_ci * Linux sets the kernel code address each entry jumps to early during
158c2ecf20Sopenharmony_ci * bootup, and never changes them. This is the general layout of the
168c2ecf20Sopenharmony_ci * IDT entries:
178c2ecf20Sopenharmony_ci *
188c2ecf20Sopenharmony_ci *  Vectors   0 ...  31 : system traps and exceptions - hardcoded events
198c2ecf20Sopenharmony_ci *  Vectors  32 ... 127 : device interrupts
208c2ecf20Sopenharmony_ci *  Vector  128         : legacy int80 syscall interface
218c2ecf20Sopenharmony_ci *  Vectors 129 ... LOCAL_TIMER_VECTOR-1
228c2ecf20Sopenharmony_ci *  Vectors LOCAL_TIMER_VECTOR ... 255 : special interrupts
238c2ecf20Sopenharmony_ci *
248c2ecf20Sopenharmony_ci * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table.
258c2ecf20Sopenharmony_ci *
268c2ecf20Sopenharmony_ci * This file enumerates the exact layout of them:
278c2ecf20Sopenharmony_ci */
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_ci#define NMI_VECTOR			0x02
308c2ecf20Sopenharmony_ci#define MCE_VECTOR			0x12
318c2ecf20Sopenharmony_ci
328c2ecf20Sopenharmony_ci/*
338c2ecf20Sopenharmony_ci * IDT vectors usable for external interrupt sources start at 0x20.
348c2ecf20Sopenharmony_ci * (0x80 is the syscall vector, 0x30-0x3f are for ISA)
358c2ecf20Sopenharmony_ci */
368c2ecf20Sopenharmony_ci#define FIRST_EXTERNAL_VECTOR		0x20
378c2ecf20Sopenharmony_ci
388c2ecf20Sopenharmony_ci/*
398c2ecf20Sopenharmony_ci * Reserve the lowest usable vector (and hence lowest priority)  0x20 for
408c2ecf20Sopenharmony_ci * triggering cleanup after irq migration. 0x21-0x2f will still be used
418c2ecf20Sopenharmony_ci * for device interrupts.
428c2ecf20Sopenharmony_ci */
438c2ecf20Sopenharmony_ci#define IRQ_MOVE_CLEANUP_VECTOR		FIRST_EXTERNAL_VECTOR
448c2ecf20Sopenharmony_ci
458c2ecf20Sopenharmony_ci#define IA32_SYSCALL_VECTOR		0x80
468c2ecf20Sopenharmony_ci
478c2ecf20Sopenharmony_ci/*
488c2ecf20Sopenharmony_ci * Vectors 0x30-0x3f are used for ISA interrupts.
498c2ecf20Sopenharmony_ci *   round up to the next 16-vector boundary
508c2ecf20Sopenharmony_ci */
518c2ecf20Sopenharmony_ci#define ISA_IRQ_VECTOR(irq)		(((FIRST_EXTERNAL_VECTOR + 16) & ~15) + irq)
528c2ecf20Sopenharmony_ci
538c2ecf20Sopenharmony_ci/*
548c2ecf20Sopenharmony_ci * Special IRQ vectors used by the SMP architecture, 0xf0-0xff
558c2ecf20Sopenharmony_ci *
568c2ecf20Sopenharmony_ci *  some of the following vectors are 'rare', they are merged
578c2ecf20Sopenharmony_ci *  into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
588c2ecf20Sopenharmony_ci *  TLB, reschedule and local APIC vectors are performance-critical.
598c2ecf20Sopenharmony_ci */
608c2ecf20Sopenharmony_ci
618c2ecf20Sopenharmony_ci#define SPURIOUS_APIC_VECTOR		0xff
628c2ecf20Sopenharmony_ci/*
638c2ecf20Sopenharmony_ci * Sanity check
648c2ecf20Sopenharmony_ci */
658c2ecf20Sopenharmony_ci#if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
668c2ecf20Sopenharmony_ci# error SPURIOUS_APIC_VECTOR definition error
678c2ecf20Sopenharmony_ci#endif
688c2ecf20Sopenharmony_ci
698c2ecf20Sopenharmony_ci#define ERROR_APIC_VECTOR		0xfe
708c2ecf20Sopenharmony_ci#define RESCHEDULE_VECTOR		0xfd
718c2ecf20Sopenharmony_ci#define CALL_FUNCTION_VECTOR		0xfc
728c2ecf20Sopenharmony_ci#define CALL_FUNCTION_SINGLE_VECTOR	0xfb
738c2ecf20Sopenharmony_ci#define THERMAL_APIC_VECTOR		0xfa
748c2ecf20Sopenharmony_ci#define THRESHOLD_APIC_VECTOR		0xf9
758c2ecf20Sopenharmony_ci#define REBOOT_VECTOR			0xf8
768c2ecf20Sopenharmony_ci
778c2ecf20Sopenharmony_ci/*
788c2ecf20Sopenharmony_ci * Generic system vector for platform specific use
798c2ecf20Sopenharmony_ci */
808c2ecf20Sopenharmony_ci#define X86_PLATFORM_IPI_VECTOR		0xf7
818c2ecf20Sopenharmony_ci
828c2ecf20Sopenharmony_ci/*
838c2ecf20Sopenharmony_ci * IRQ work vector:
848c2ecf20Sopenharmony_ci */
858c2ecf20Sopenharmony_ci#define IRQ_WORK_VECTOR			0xf6
868c2ecf20Sopenharmony_ci
878c2ecf20Sopenharmony_ci#define UV_BAU_MESSAGE			0xf5
888c2ecf20Sopenharmony_ci#define DEFERRED_ERROR_VECTOR		0xf4
898c2ecf20Sopenharmony_ci
908c2ecf20Sopenharmony_ci/* Vector on which hypervisor callbacks will be delivered */
918c2ecf20Sopenharmony_ci#define HYPERVISOR_CALLBACK_VECTOR	0xf3
928c2ecf20Sopenharmony_ci
938c2ecf20Sopenharmony_ci/* Vector for KVM to deliver posted interrupt IPI */
948c2ecf20Sopenharmony_ci#ifdef CONFIG_HAVE_KVM
958c2ecf20Sopenharmony_ci#define POSTED_INTR_VECTOR		0xf2
968c2ecf20Sopenharmony_ci#define POSTED_INTR_WAKEUP_VECTOR	0xf1
978c2ecf20Sopenharmony_ci#define POSTED_INTR_NESTED_VECTOR	0xf0
988c2ecf20Sopenharmony_ci#endif
998c2ecf20Sopenharmony_ci
1008c2ecf20Sopenharmony_ci#define MANAGED_IRQ_SHUTDOWN_VECTOR	0xef
1018c2ecf20Sopenharmony_ci
1028c2ecf20Sopenharmony_ci#if IS_ENABLED(CONFIG_HYPERV)
1038c2ecf20Sopenharmony_ci#define HYPERV_REENLIGHTENMENT_VECTOR	0xee
1048c2ecf20Sopenharmony_ci#define HYPERV_STIMER0_VECTOR		0xed
1058c2ecf20Sopenharmony_ci#endif
1068c2ecf20Sopenharmony_ci
1078c2ecf20Sopenharmony_ci#define LOCAL_TIMER_VECTOR		0xec
1088c2ecf20Sopenharmony_ci
1098c2ecf20Sopenharmony_ci#define NR_VECTORS			 256
1108c2ecf20Sopenharmony_ci
1118c2ecf20Sopenharmony_ci#ifdef CONFIG_X86_LOCAL_APIC
1128c2ecf20Sopenharmony_ci#define FIRST_SYSTEM_VECTOR		LOCAL_TIMER_VECTOR
1138c2ecf20Sopenharmony_ci#else
1148c2ecf20Sopenharmony_ci#define FIRST_SYSTEM_VECTOR		NR_VECTORS
1158c2ecf20Sopenharmony_ci#endif
1168c2ecf20Sopenharmony_ci
1178c2ecf20Sopenharmony_ci/*
1188c2ecf20Sopenharmony_ci * Size the maximum number of interrupts.
1198c2ecf20Sopenharmony_ci *
1208c2ecf20Sopenharmony_ci * If the irq_desc[] array has a sparse layout, we can size things
1218c2ecf20Sopenharmony_ci * generously - it scales up linearly with the maximum number of CPUs,
1228c2ecf20Sopenharmony_ci * and the maximum number of IO-APICs, whichever is higher.
1238c2ecf20Sopenharmony_ci *
1248c2ecf20Sopenharmony_ci * In other cases we size more conservatively, to not create too large
1258c2ecf20Sopenharmony_ci * static arrays.
1268c2ecf20Sopenharmony_ci */
1278c2ecf20Sopenharmony_ci
1288c2ecf20Sopenharmony_ci#define NR_IRQS_LEGACY			16
1298c2ecf20Sopenharmony_ci
1308c2ecf20Sopenharmony_ci#define CPU_VECTOR_LIMIT		(64 * NR_CPUS)
1318c2ecf20Sopenharmony_ci#define IO_APIC_VECTOR_LIMIT		(32 * MAX_IO_APICS)
1328c2ecf20Sopenharmony_ci
1338c2ecf20Sopenharmony_ci#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_PCI_MSI)
1348c2ecf20Sopenharmony_ci#define NR_IRQS						\
1358c2ecf20Sopenharmony_ci	(CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ?	\
1368c2ecf20Sopenharmony_ci		(NR_VECTORS + CPU_VECTOR_LIMIT)  :	\
1378c2ecf20Sopenharmony_ci		(NR_VECTORS + IO_APIC_VECTOR_LIMIT))
1388c2ecf20Sopenharmony_ci#elif defined(CONFIG_X86_IO_APIC)
1398c2ecf20Sopenharmony_ci#define	NR_IRQS				(NR_VECTORS + IO_APIC_VECTOR_LIMIT)
1408c2ecf20Sopenharmony_ci#elif defined(CONFIG_PCI_MSI)
1418c2ecf20Sopenharmony_ci#define NR_IRQS				(NR_VECTORS + CPU_VECTOR_LIMIT)
1428c2ecf20Sopenharmony_ci#else
1438c2ecf20Sopenharmony_ci#define NR_IRQS				NR_IRQS_LEGACY
1448c2ecf20Sopenharmony_ci#endif
1458c2ecf20Sopenharmony_ci
1468c2ecf20Sopenharmony_ci#endif /* _ASM_X86_IRQ_VECTORS_H */
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