18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * imr.h: Isolated Memory Region API 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright(c) 2013 Intel Corporation. 68c2ecf20Sopenharmony_ci * Copyright(c) 2015 Bryan O'Donoghue <pure.logic@nexus-software.ie> 78c2ecf20Sopenharmony_ci */ 88c2ecf20Sopenharmony_ci#ifndef _IMR_H 98c2ecf20Sopenharmony_ci#define _IMR_H 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci#include <linux/types.h> 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci/* 148c2ecf20Sopenharmony_ci * IMR agent access mask bits 158c2ecf20Sopenharmony_ci * See section 12.7.4.7 from quark-x1000-datasheet.pdf for register 168c2ecf20Sopenharmony_ci * definitions. 178c2ecf20Sopenharmony_ci */ 188c2ecf20Sopenharmony_ci#define IMR_ESRAM_FLUSH BIT(31) 198c2ecf20Sopenharmony_ci#define IMR_CPU_SNOOP BIT(30) /* Applicable only to write */ 208c2ecf20Sopenharmony_ci#define IMR_RMU BIT(29) 218c2ecf20Sopenharmony_ci#define IMR_VC1_SAI_ID3 BIT(15) 228c2ecf20Sopenharmony_ci#define IMR_VC1_SAI_ID2 BIT(14) 238c2ecf20Sopenharmony_ci#define IMR_VC1_SAI_ID1 BIT(13) 248c2ecf20Sopenharmony_ci#define IMR_VC1_SAI_ID0 BIT(12) 258c2ecf20Sopenharmony_ci#define IMR_VC0_SAI_ID3 BIT(11) 268c2ecf20Sopenharmony_ci#define IMR_VC0_SAI_ID2 BIT(10) 278c2ecf20Sopenharmony_ci#define IMR_VC0_SAI_ID1 BIT(9) 288c2ecf20Sopenharmony_ci#define IMR_VC0_SAI_ID0 BIT(8) 298c2ecf20Sopenharmony_ci#define IMR_CPU_0 BIT(1) /* SMM mode */ 308c2ecf20Sopenharmony_ci#define IMR_CPU BIT(0) /* Non SMM mode */ 318c2ecf20Sopenharmony_ci#define IMR_ACCESS_NONE 0 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci/* 348c2ecf20Sopenharmony_ci * Read/Write access-all bits here include some reserved bits 358c2ecf20Sopenharmony_ci * These are the values firmware uses and are accepted by hardware. 368c2ecf20Sopenharmony_ci * The kernel defines read/write access-all in the same way as firmware 378c2ecf20Sopenharmony_ci * in order to have a consistent and crisp definition across firmware, 388c2ecf20Sopenharmony_ci * bootloader and kernel. 398c2ecf20Sopenharmony_ci */ 408c2ecf20Sopenharmony_ci#define IMR_READ_ACCESS_ALL 0xBFFFFFFF 418c2ecf20Sopenharmony_ci#define IMR_WRITE_ACCESS_ALL 0xFFFFFFFF 428c2ecf20Sopenharmony_ci 438c2ecf20Sopenharmony_ci/* Number of IMRs provided by Quark X1000 SoC */ 448c2ecf20Sopenharmony_ci#define QUARK_X1000_IMR_MAX 0x08 458c2ecf20Sopenharmony_ci#define QUARK_X1000_IMR_REGBASE 0x40 468c2ecf20Sopenharmony_ci 478c2ecf20Sopenharmony_ci/* IMR alignment bits - only bits 31:10 are checked for IMR validity */ 488c2ecf20Sopenharmony_ci#define IMR_ALIGN 0x400 498c2ecf20Sopenharmony_ci#define IMR_MASK (IMR_ALIGN - 1) 508c2ecf20Sopenharmony_ci 518c2ecf20Sopenharmony_ciint imr_add_range(phys_addr_t base, size_t size, 528c2ecf20Sopenharmony_ci unsigned int rmask, unsigned int wmask); 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_ciint imr_remove_range(phys_addr_t base, size_t size); 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_ci#endif /* _IMR_H */ 57