1/* SPDX-License-Identifier: GPL-2.0 */ 2 3/* 4 * This file contains definitions from Hyper-V Hypervisor Top-Level Functional 5 * Specification (TLFS): 6 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7 */ 8 9#ifndef _ASM_X86_HYPERV_TLFS_H 10#define _ASM_X86_HYPERV_TLFS_H 11 12#include <linux/types.h> 13#include <asm/page.h> 14/* 15 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent 16 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). 17 */ 18#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 19#define HYPERV_CPUID_INTERFACE 0x40000001 20#define HYPERV_CPUID_VERSION 0x40000002 21#define HYPERV_CPUID_FEATURES 0x40000003 22#define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 23#define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 24#define HYPERV_CPUID_NESTED_FEATURES 0x4000000A 25 26#define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 27#define HYPERV_CPUID_MIN 0x40000005 28#define HYPERV_CPUID_MAX 0x4000ffff 29 30/* 31 * Group D Features. The bit assignments are custom to each architecture. 32 * On x86/x64 these are HYPERV_CPUID_FEATURES.EDX bits. 33 */ 34/* The MWAIT instruction is available (per section MONITOR / MWAIT) */ 35#define HV_X64_MWAIT_AVAILABLE BIT(0) 36/* Guest debugging support is available */ 37#define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) 38/* Performance Monitor support is available*/ 39#define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) 40/* Support for physical CPU dynamic partitioning events is available*/ 41#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) 42/* 43 * Support for passing hypercall input parameter block via XMM 44 * registers is available 45 */ 46#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE BIT(4) 47/* Support for a virtual guest idle state is available */ 48#define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) 49/* Frequency MSRs available */ 50#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) 51/* Crash MSR available */ 52#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) 53/* Support for debug MSRs available */ 54#define HV_FEATURE_DEBUG_MSRS_AVAILABLE BIT(11) 55/* stimer Direct Mode is available */ 56#define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) 57 58/* 59 * Implementation recommendations. Indicates which behaviors the hypervisor 60 * recommends the OS implement for optimal performance. 61 * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. 62 */ 63/* 64 * Recommend using hypercall for address space switches rather 65 * than MOV to CR3 instruction 66 */ 67#define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) 68/* Recommend using hypercall for local TLB flushes rather 69 * than INVLPG or MOV to CR3 instructions */ 70#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) 71/* 72 * Recommend using hypercall for remote TLB flushes rather 73 * than inter-processor interrupts 74 */ 75#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) 76/* 77 * Recommend using MSRs for accessing APIC registers 78 * EOI, ICR and TPR rather than their memory-mapped counterparts 79 */ 80#define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) 81/* Recommend using the hypervisor-provided MSR to initiate a system RESET */ 82#define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) 83/* 84 * Recommend using relaxed timing for this partition. If used, 85 * the VM should disable any watchdog timeouts that rely on the 86 * timely delivery of external interrupts 87 */ 88#define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) 89 90/* 91 * Recommend not using Auto End-Of-Interrupt feature 92 */ 93#define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) 94 95/* 96 * Recommend using cluster IPI hypercalls. 97 */ 98#define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) 99 100/* Recommend using the newer ExProcessorMasks interface */ 101#define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) 102 103/* Recommend using enlightened VMCS */ 104#define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) 105 106/* 107 * Virtual processor will never share a physical core with another virtual 108 * processor, except for virtual processors that are reported as sibling SMT 109 * threads. 110 */ 111#define HV_X64_NO_NONARCH_CORESHARING BIT(18) 112 113/* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ 114#define HV_X64_NESTED_DIRECT_FLUSH BIT(17) 115#define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) 116#define HV_X64_NESTED_MSR_BITMAP BIT(19) 117 118/* Hyper-V specific model specific registers (MSRs) */ 119 120/* MSR used to identify the guest OS. */ 121#define HV_X64_MSR_GUEST_OS_ID 0x40000000 122 123/* MSR used to setup pages used to communicate with the hypervisor. */ 124#define HV_X64_MSR_HYPERCALL 0x40000001 125 126/* MSR used to provide vcpu index */ 127#define HV_X64_MSR_VP_INDEX 0x40000002 128 129/* MSR used to reset the guest OS. */ 130#define HV_X64_MSR_RESET 0x40000003 131 132/* MSR used to provide vcpu runtime in 100ns units */ 133#define HV_X64_MSR_VP_RUNTIME 0x40000010 134 135/* MSR used to read the per-partition time reference counter */ 136#define HV_X64_MSR_TIME_REF_COUNT 0x40000020 137 138/* A partition's reference time stamp counter (TSC) page */ 139#define HV_X64_MSR_REFERENCE_TSC 0x40000021 140 141/* MSR used to retrieve the TSC frequency */ 142#define HV_X64_MSR_TSC_FREQUENCY 0x40000022 143 144/* MSR used to retrieve the local APIC timer frequency */ 145#define HV_X64_MSR_APIC_FREQUENCY 0x40000023 146 147/* Define the virtual APIC registers */ 148#define HV_X64_MSR_EOI 0x40000070 149#define HV_X64_MSR_ICR 0x40000071 150#define HV_X64_MSR_TPR 0x40000072 151#define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 152 153/* Define synthetic interrupt controller model specific registers. */ 154#define HV_X64_MSR_SCONTROL 0x40000080 155#define HV_X64_MSR_SVERSION 0x40000081 156#define HV_X64_MSR_SIEFP 0x40000082 157#define HV_X64_MSR_SIMP 0x40000083 158#define HV_X64_MSR_EOM 0x40000084 159#define HV_X64_MSR_SINT0 0x40000090 160#define HV_X64_MSR_SINT1 0x40000091 161#define HV_X64_MSR_SINT2 0x40000092 162#define HV_X64_MSR_SINT3 0x40000093 163#define HV_X64_MSR_SINT4 0x40000094 164#define HV_X64_MSR_SINT5 0x40000095 165#define HV_X64_MSR_SINT6 0x40000096 166#define HV_X64_MSR_SINT7 0x40000097 167#define HV_X64_MSR_SINT8 0x40000098 168#define HV_X64_MSR_SINT9 0x40000099 169#define HV_X64_MSR_SINT10 0x4000009A 170#define HV_X64_MSR_SINT11 0x4000009B 171#define HV_X64_MSR_SINT12 0x4000009C 172#define HV_X64_MSR_SINT13 0x4000009D 173#define HV_X64_MSR_SINT14 0x4000009E 174#define HV_X64_MSR_SINT15 0x4000009F 175 176/* 177 * Synthetic Timer MSRs. Four timers per vcpu. 178 */ 179#define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 180#define HV_X64_MSR_STIMER0_COUNT 0x400000B1 181#define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 182#define HV_X64_MSR_STIMER1_COUNT 0x400000B3 183#define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 184#define HV_X64_MSR_STIMER2_COUNT 0x400000B5 185#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 186#define HV_X64_MSR_STIMER3_COUNT 0x400000B7 187 188/* Hyper-V guest idle MSR */ 189#define HV_X64_MSR_GUEST_IDLE 0x400000F0 190 191/* Hyper-V guest crash notification MSR's */ 192#define HV_X64_MSR_CRASH_P0 0x40000100 193#define HV_X64_MSR_CRASH_P1 0x40000101 194#define HV_X64_MSR_CRASH_P2 0x40000102 195#define HV_X64_MSR_CRASH_P3 0x40000103 196#define HV_X64_MSR_CRASH_P4 0x40000104 197#define HV_X64_MSR_CRASH_CTL 0x40000105 198 199/* TSC emulation after migration */ 200#define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 201#define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 202#define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 203 204/* TSC invariant control */ 205#define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118 206 207/* 208 * Declare the MSR used to setup pages used to communicate with the hypervisor. 209 */ 210union hv_x64_msr_hypercall_contents { 211 u64 as_uint64; 212 struct { 213 u64 enable:1; 214 u64 reserved:11; 215 u64 guest_physical_address:52; 216 } __packed; 217}; 218 219struct hv_reenlightenment_control { 220 __u64 vector:8; 221 __u64 reserved1:8; 222 __u64 enabled:1; 223 __u64 reserved2:15; 224 __u64 target_vp:32; 225} __packed; 226 227struct hv_tsc_emulation_control { 228 __u64 enabled:1; 229 __u64 reserved:63; 230} __packed; 231 232struct hv_tsc_emulation_status { 233 __u64 inprogress:1; 234 __u64 reserved:63; 235} __packed; 236 237#define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 238#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 239#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 240 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 241 242#define HV_X64_MSR_CRASH_PARAMS \ 243 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 244 245#define HV_IPI_LOW_VECTOR 0x10 246#define HV_IPI_HIGH_VECTOR 0xff 247 248#define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 249#define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 250#define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ 251 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 252 253/* Hyper-V Enlightened VMCS version mask in nested features CPUID */ 254#define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff 255 256#define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 257#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 258 259 260/* Define hypervisor message types. */ 261enum hv_message_type { 262 HVMSG_NONE = 0x00000000, 263 264 /* Memory access messages. */ 265 HVMSG_UNMAPPED_GPA = 0x80000000, 266 HVMSG_GPA_INTERCEPT = 0x80000001, 267 268 /* Timer notification messages. */ 269 HVMSG_TIMER_EXPIRED = 0x80000010, 270 271 /* Error messages. */ 272 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, 273 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, 274 HVMSG_UNSUPPORTED_FEATURE = 0x80000022, 275 276 /* Trace buffer complete messages. */ 277 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, 278 279 /* Platform-specific processor intercept messages. */ 280 HVMSG_X64_IOPORT_INTERCEPT = 0x80010000, 281 HVMSG_X64_MSR_INTERCEPT = 0x80010001, 282 HVMSG_X64_CPUID_INTERCEPT = 0x80010002, 283 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, 284 HVMSG_X64_APIC_EOI = 0x80010004, 285 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005 286}; 287 288struct hv_nested_enlightenments_control { 289 struct { 290 __u32 directhypercall:1; 291 __u32 reserved:31; 292 } features; 293 struct { 294 __u32 reserved; 295 } hypercallControls; 296} __packed; 297 298/* Define virtual processor assist page structure. */ 299struct hv_vp_assist_page { 300 __u32 apic_assist; 301 __u32 reserved1; 302 __u64 vtl_control[3]; 303 struct hv_nested_enlightenments_control nested_control; 304 __u8 enlighten_vmentry; 305 __u8 reserved2[7]; 306 __u64 current_nested_vmcs; 307} __packed; 308 309struct hv_enlightened_vmcs { 310 u32 revision_id; 311 u32 abort; 312 313 u16 host_es_selector; 314 u16 host_cs_selector; 315 u16 host_ss_selector; 316 u16 host_ds_selector; 317 u16 host_fs_selector; 318 u16 host_gs_selector; 319 u16 host_tr_selector; 320 321 u16 padding16_1; 322 323 u64 host_ia32_pat; 324 u64 host_ia32_efer; 325 326 u64 host_cr0; 327 u64 host_cr3; 328 u64 host_cr4; 329 330 u64 host_ia32_sysenter_esp; 331 u64 host_ia32_sysenter_eip; 332 u64 host_rip; 333 u32 host_ia32_sysenter_cs; 334 335 u32 pin_based_vm_exec_control; 336 u32 vm_exit_controls; 337 u32 secondary_vm_exec_control; 338 339 u64 io_bitmap_a; 340 u64 io_bitmap_b; 341 u64 msr_bitmap; 342 343 u16 guest_es_selector; 344 u16 guest_cs_selector; 345 u16 guest_ss_selector; 346 u16 guest_ds_selector; 347 u16 guest_fs_selector; 348 u16 guest_gs_selector; 349 u16 guest_ldtr_selector; 350 u16 guest_tr_selector; 351 352 u32 guest_es_limit; 353 u32 guest_cs_limit; 354 u32 guest_ss_limit; 355 u32 guest_ds_limit; 356 u32 guest_fs_limit; 357 u32 guest_gs_limit; 358 u32 guest_ldtr_limit; 359 u32 guest_tr_limit; 360 u32 guest_gdtr_limit; 361 u32 guest_idtr_limit; 362 363 u32 guest_es_ar_bytes; 364 u32 guest_cs_ar_bytes; 365 u32 guest_ss_ar_bytes; 366 u32 guest_ds_ar_bytes; 367 u32 guest_fs_ar_bytes; 368 u32 guest_gs_ar_bytes; 369 u32 guest_ldtr_ar_bytes; 370 u32 guest_tr_ar_bytes; 371 372 u64 guest_es_base; 373 u64 guest_cs_base; 374 u64 guest_ss_base; 375 u64 guest_ds_base; 376 u64 guest_fs_base; 377 u64 guest_gs_base; 378 u64 guest_ldtr_base; 379 u64 guest_tr_base; 380 u64 guest_gdtr_base; 381 u64 guest_idtr_base; 382 383 u64 padding64_1[3]; 384 385 u64 vm_exit_msr_store_addr; 386 u64 vm_exit_msr_load_addr; 387 u64 vm_entry_msr_load_addr; 388 389 u64 cr3_target_value0; 390 u64 cr3_target_value1; 391 u64 cr3_target_value2; 392 u64 cr3_target_value3; 393 394 u32 page_fault_error_code_mask; 395 u32 page_fault_error_code_match; 396 397 u32 cr3_target_count; 398 u32 vm_exit_msr_store_count; 399 u32 vm_exit_msr_load_count; 400 u32 vm_entry_msr_load_count; 401 402 u64 tsc_offset; 403 u64 virtual_apic_page_addr; 404 u64 vmcs_link_pointer; 405 406 u64 guest_ia32_debugctl; 407 u64 guest_ia32_pat; 408 u64 guest_ia32_efer; 409 410 u64 guest_pdptr0; 411 u64 guest_pdptr1; 412 u64 guest_pdptr2; 413 u64 guest_pdptr3; 414 415 u64 guest_pending_dbg_exceptions; 416 u64 guest_sysenter_esp; 417 u64 guest_sysenter_eip; 418 419 u32 guest_activity_state; 420 u32 guest_sysenter_cs; 421 422 u64 cr0_guest_host_mask; 423 u64 cr4_guest_host_mask; 424 u64 cr0_read_shadow; 425 u64 cr4_read_shadow; 426 u64 guest_cr0; 427 u64 guest_cr3; 428 u64 guest_cr4; 429 u64 guest_dr7; 430 431 u64 host_fs_base; 432 u64 host_gs_base; 433 u64 host_tr_base; 434 u64 host_gdtr_base; 435 u64 host_idtr_base; 436 u64 host_rsp; 437 438 u64 ept_pointer; 439 440 u16 virtual_processor_id; 441 u16 padding16_2[3]; 442 443 u64 padding64_2[5]; 444 u64 guest_physical_address; 445 446 u32 vm_instruction_error; 447 u32 vm_exit_reason; 448 u32 vm_exit_intr_info; 449 u32 vm_exit_intr_error_code; 450 u32 idt_vectoring_info_field; 451 u32 idt_vectoring_error_code; 452 u32 vm_exit_instruction_len; 453 u32 vmx_instruction_info; 454 455 u64 exit_qualification; 456 u64 exit_io_instruction_ecx; 457 u64 exit_io_instruction_esi; 458 u64 exit_io_instruction_edi; 459 u64 exit_io_instruction_eip; 460 461 u64 guest_linear_address; 462 u64 guest_rsp; 463 u64 guest_rflags; 464 465 u32 guest_interruptibility_info; 466 u32 cpu_based_vm_exec_control; 467 u32 exception_bitmap; 468 u32 vm_entry_controls; 469 u32 vm_entry_intr_info_field; 470 u32 vm_entry_exception_error_code; 471 u32 vm_entry_instruction_len; 472 u32 tpr_threshold; 473 474 u64 guest_rip; 475 476 u32 hv_clean_fields; 477 u32 padding32_1; 478 u32 hv_synthetic_controls; 479 struct { 480 u32 nested_flush_hypercall:1; 481 u32 msr_bitmap:1; 482 u32 reserved:30; 483 } __packed hv_enlightenments_control; 484 u32 hv_vp_id; 485 u32 padding32_2; 486 u64 hv_vm_id; 487 u64 partition_assist_page; 488 u64 padding64_4[4]; 489 u64 guest_bndcfgs; 490 u64 padding64_5[7]; 491 u64 xss_exit_bitmap; 492 u64 padding64_6[7]; 493} __packed; 494 495#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE 0 496#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0) 497#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1) 498#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2) 499#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3) 500#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4) 501#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5) 502#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6) 503#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7) 504#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8) 505#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9) 506#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10) 507#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11) 508#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12) 509#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13) 510#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14) 511#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15) 512 513#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL 0xFFFF 514 515struct hv_partition_assist_pg { 516 u32 tlb_lock_count; 517}; 518 519 520#include <asm-generic/hyperv-tlfs.h> 521 522#endif 523