18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci#ifndef _ASM_X86_GART_H 38c2ecf20Sopenharmony_ci#define _ASM_X86_GART_H 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ci#include <asm/e820/api.h> 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciextern void set_up_gart_resume(u32, u32); 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ciextern int fallback_aper_order; 108c2ecf20Sopenharmony_ciextern int fallback_aper_force; 118c2ecf20Sopenharmony_ciextern int fix_aperture; 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci/* PTE bits. */ 148c2ecf20Sopenharmony_ci#define GPTE_VALID 1 158c2ecf20Sopenharmony_ci#define GPTE_COHERENT 2 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci/* Aperture control register bits. */ 188c2ecf20Sopenharmony_ci#define GARTEN (1<<0) 198c2ecf20Sopenharmony_ci#define DISGARTCPU (1<<4) 208c2ecf20Sopenharmony_ci#define DISGARTIO (1<<5) 218c2ecf20Sopenharmony_ci#define DISTLBWALKPRB (1<<6) 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci/* GART cache control register bits. */ 248c2ecf20Sopenharmony_ci#define INVGART (1<<0) 258c2ecf20Sopenharmony_ci#define GARTPTEERR (1<<1) 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci/* K8 On-cpu GART registers */ 288c2ecf20Sopenharmony_ci#define AMD64_GARTAPERTURECTL 0x90 298c2ecf20Sopenharmony_ci#define AMD64_GARTAPERTUREBASE 0x94 308c2ecf20Sopenharmony_ci#define AMD64_GARTTABLEBASE 0x98 318c2ecf20Sopenharmony_ci#define AMD64_GARTCACHECTL 0x9c 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci#ifdef CONFIG_GART_IOMMU 348c2ecf20Sopenharmony_ciextern int gart_iommu_aperture; 358c2ecf20Sopenharmony_ciextern int gart_iommu_aperture_allowed; 368c2ecf20Sopenharmony_ciextern int gart_iommu_aperture_disabled; 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ciextern void early_gart_iommu_check(void); 398c2ecf20Sopenharmony_ciextern int gart_iommu_init(void); 408c2ecf20Sopenharmony_ciextern void __init gart_parse_options(char *); 418c2ecf20Sopenharmony_ciextern int gart_iommu_hole_init(void); 428c2ecf20Sopenharmony_ci 438c2ecf20Sopenharmony_ci#else 448c2ecf20Sopenharmony_ci#define gart_iommu_aperture 0 458c2ecf20Sopenharmony_ci#define gart_iommu_aperture_allowed 0 468c2ecf20Sopenharmony_ci#define gart_iommu_aperture_disabled 1 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_cistatic inline void early_gart_iommu_check(void) 498c2ecf20Sopenharmony_ci{ 508c2ecf20Sopenharmony_ci} 518c2ecf20Sopenharmony_cistatic inline void gart_parse_options(char *options) 528c2ecf20Sopenharmony_ci{ 538c2ecf20Sopenharmony_ci} 548c2ecf20Sopenharmony_cistatic inline int gart_iommu_hole_init(void) 558c2ecf20Sopenharmony_ci{ 568c2ecf20Sopenharmony_ci return -ENODEV; 578c2ecf20Sopenharmony_ci} 588c2ecf20Sopenharmony_ci#endif 598c2ecf20Sopenharmony_ci 608c2ecf20Sopenharmony_ciextern int agp_amd64_init(void); 618c2ecf20Sopenharmony_ci 628c2ecf20Sopenharmony_cistatic inline void gart_set_size_and_enable(struct pci_dev *dev, u32 order) 638c2ecf20Sopenharmony_ci{ 648c2ecf20Sopenharmony_ci u32 ctl; 658c2ecf20Sopenharmony_ci 668c2ecf20Sopenharmony_ci /* 678c2ecf20Sopenharmony_ci * Don't enable translation but enable GART IO and CPU accesses. 688c2ecf20Sopenharmony_ci * Also, set DISTLBWALKPRB since GART tables memory is UC. 698c2ecf20Sopenharmony_ci */ 708c2ecf20Sopenharmony_ci ctl = order << 1; 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_ci pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); 738c2ecf20Sopenharmony_ci} 748c2ecf20Sopenharmony_ci 758c2ecf20Sopenharmony_cistatic inline void enable_gart_translation(struct pci_dev *dev, u64 addr) 768c2ecf20Sopenharmony_ci{ 778c2ecf20Sopenharmony_ci u32 tmp, ctl; 788c2ecf20Sopenharmony_ci 798c2ecf20Sopenharmony_ci /* address of the mappings table */ 808c2ecf20Sopenharmony_ci addr >>= 12; 818c2ecf20Sopenharmony_ci tmp = (u32) addr<<4; 828c2ecf20Sopenharmony_ci tmp &= ~0xf; 838c2ecf20Sopenharmony_ci pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp); 848c2ecf20Sopenharmony_ci 858c2ecf20Sopenharmony_ci /* Enable GART translation for this hammer. */ 868c2ecf20Sopenharmony_ci pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); 878c2ecf20Sopenharmony_ci ctl |= GARTEN | DISTLBWALKPRB; 888c2ecf20Sopenharmony_ci ctl &= ~(DISGARTCPU | DISGARTIO); 898c2ecf20Sopenharmony_ci pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); 908c2ecf20Sopenharmony_ci} 918c2ecf20Sopenharmony_ci 928c2ecf20Sopenharmony_cistatic inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size) 938c2ecf20Sopenharmony_ci{ 948c2ecf20Sopenharmony_ci if (!aper_base) 958c2ecf20Sopenharmony_ci return 0; 968c2ecf20Sopenharmony_ci 978c2ecf20Sopenharmony_ci if (aper_base + aper_size > 0x100000000ULL) { 988c2ecf20Sopenharmony_ci printk(KERN_INFO "Aperture beyond 4GB. Ignoring.\n"); 998c2ecf20Sopenharmony_ci return 0; 1008c2ecf20Sopenharmony_ci } 1018c2ecf20Sopenharmony_ci if (e820__mapped_any(aper_base, aper_base + aper_size, E820_TYPE_RAM)) { 1028c2ecf20Sopenharmony_ci printk(KERN_INFO "Aperture pointing to e820 RAM. Ignoring.\n"); 1038c2ecf20Sopenharmony_ci return 0; 1048c2ecf20Sopenharmony_ci } 1058c2ecf20Sopenharmony_ci if (aper_size < min_size) { 1068c2ecf20Sopenharmony_ci printk(KERN_INFO "Aperture too small (%d MB) than (%d MB)\n", 1078c2ecf20Sopenharmony_ci aper_size>>20, min_size>>20); 1088c2ecf20Sopenharmony_ci return 0; 1098c2ecf20Sopenharmony_ci } 1108c2ecf20Sopenharmony_ci 1118c2ecf20Sopenharmony_ci return 1; 1128c2ecf20Sopenharmony_ci} 1138c2ecf20Sopenharmony_ci 1148c2ecf20Sopenharmony_ci#endif /* _ASM_X86_GART_H */ 115