1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_X86_APICDEF_H 3#define _ASM_X86_APICDEF_H 4 5/* 6 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.) 7 * 8 * Alan Cox <Alan.Cox@linux.org>, 1995. 9 * Ingo Molnar <mingo@redhat.com>, 1999, 2000 10 */ 11 12#define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000 13#define APIC_DEFAULT_PHYS_BASE 0xfee00000 14 15/* 16 * This is the IO-APIC register space as specified 17 * by Intel docs: 18 */ 19#define IO_APIC_SLOT_SIZE 1024 20 21#define APIC_ID 0x20 22 23#define APIC_LVR 0x30 24#define APIC_LVR_MASK 0xFF00FF 25#define APIC_LVR_DIRECTED_EOI (1 << 24) 26#define GET_APIC_VERSION(x) ((x) & 0xFFu) 27#define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu) 28#ifdef CONFIG_X86_32 29# define APIC_INTEGRATED(x) ((x) & 0xF0u) 30#else 31# define APIC_INTEGRATED(x) (1) 32#endif 33#define APIC_XAPIC(x) ((x) >= 0x14) 34#define APIC_EXT_SPACE(x) ((x) & 0x80000000) 35#define APIC_TASKPRI 0x80 36#define APIC_TPRI_MASK 0xFFu 37#define APIC_ARBPRI 0x90 38#define APIC_ARBPRI_MASK 0xFFu 39#define APIC_PROCPRI 0xA0 40#define APIC_EOI 0xB0 41#define APIC_EOI_ACK 0x0 /* Docs say 0 for future compat. */ 42#define APIC_RRR 0xC0 43#define APIC_LDR 0xD0 44#define APIC_LDR_MASK (0xFFu << 24) 45#define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu) 46#define SET_APIC_LOGICAL_ID(x) (((x) << 24)) 47#define APIC_ALL_CPUS 0xFFu 48#define APIC_DFR 0xE0 49#define APIC_DFR_CLUSTER 0x0FFFFFFFul 50#define APIC_DFR_FLAT 0xFFFFFFFFul 51#define APIC_SPIV 0xF0 52#define APIC_SPIV_DIRECTED_EOI (1 << 12) 53#define APIC_SPIV_FOCUS_DISABLED (1 << 9) 54#define APIC_SPIV_APIC_ENABLED (1 << 8) 55#define APIC_ISR 0x100 56#define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */ 57#define APIC_TMR 0x180 58#define APIC_IRR 0x200 59#define APIC_ESR 0x280 60#define APIC_ESR_SEND_CS 0x00001 61#define APIC_ESR_RECV_CS 0x00002 62#define APIC_ESR_SEND_ACC 0x00004 63#define APIC_ESR_RECV_ACC 0x00008 64#define APIC_ESR_SENDILL 0x00020 65#define APIC_ESR_RECVILL 0x00040 66#define APIC_ESR_ILLREGA 0x00080 67#define APIC_LVTCMCI 0x2f0 68#define APIC_ICR 0x300 69#define APIC_DEST_SELF 0x40000 70#define APIC_DEST_ALLINC 0x80000 71#define APIC_DEST_ALLBUT 0xC0000 72#define APIC_ICR_RR_MASK 0x30000 73#define APIC_ICR_RR_INVALID 0x00000 74#define APIC_ICR_RR_INPROG 0x10000 75#define APIC_ICR_RR_VALID 0x20000 76#define APIC_INT_LEVELTRIG 0x08000 77#define APIC_INT_ASSERT 0x04000 78#define APIC_ICR_BUSY 0x01000 79#define APIC_DEST_LOGICAL 0x00800 80#define APIC_DEST_PHYSICAL 0x00000 81#define APIC_DM_FIXED 0x00000 82#define APIC_DM_FIXED_MASK 0x00700 83#define APIC_DM_LOWEST 0x00100 84#define APIC_DM_SMI 0x00200 85#define APIC_DM_REMRD 0x00300 86#define APIC_DM_NMI 0x00400 87#define APIC_DM_INIT 0x00500 88#define APIC_DM_STARTUP 0x00600 89#define APIC_DM_EXTINT 0x00700 90#define APIC_VECTOR_MASK 0x000FF 91#define APIC_ICR2 0x310 92#define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF) 93#define SET_APIC_DEST_FIELD(x) ((x) << 24) 94#define APIC_LVTT 0x320 95#define APIC_LVTTHMR 0x330 96#define APIC_LVTPC 0x340 97#define APIC_LVT0 0x350 98#define APIC_LVT_TIMER_BASE_MASK (0x3 << 18) 99#define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3) 100#define SET_APIC_TIMER_BASE(x) (((x) << 18)) 101#define APIC_TIMER_BASE_CLKIN 0x0 102#define APIC_TIMER_BASE_TMBASE 0x1 103#define APIC_TIMER_BASE_DIV 0x2 104#define APIC_LVT_TIMER_ONESHOT (0 << 17) 105#define APIC_LVT_TIMER_PERIODIC (1 << 17) 106#define APIC_LVT_TIMER_TSCDEADLINE (2 << 17) 107#define APIC_LVT_MASKED (1 << 16) 108#define APIC_LVT_LEVEL_TRIGGER (1 << 15) 109#define APIC_LVT_REMOTE_IRR (1 << 14) 110#define APIC_INPUT_POLARITY (1 << 13) 111#define APIC_SEND_PENDING (1 << 12) 112#define APIC_MODE_MASK 0x700 113#define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7) 114#define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8)) 115#define APIC_MODE_FIXED 0x0 116#define APIC_MODE_NMI 0x4 117#define APIC_MODE_EXTINT 0x7 118#define APIC_LVT1 0x360 119#define APIC_LVTERR 0x370 120#define APIC_TMICT 0x380 121#define APIC_TMCCT 0x390 122#define APIC_TDCR 0x3E0 123#define APIC_SELF_IPI 0x3F0 124#define APIC_TDR_DIV_TMBASE (1 << 2) 125#define APIC_TDR_DIV_1 0xB 126#define APIC_TDR_DIV_2 0x0 127#define APIC_TDR_DIV_4 0x1 128#define APIC_TDR_DIV_8 0x2 129#define APIC_TDR_DIV_16 0x3 130#define APIC_TDR_DIV_32 0x8 131#define APIC_TDR_DIV_64 0x9 132#define APIC_TDR_DIV_128 0xA 133#define APIC_EFEAT 0x400 134#define APIC_ECTRL 0x410 135#define APIC_EILVTn(n) (0x500 + 0x10 * n) 136#define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */ 137#define APIC_EILVT_NR_AMD_10H 4 138#define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H 139#define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) 140#define APIC_EILVT_MSG_FIX 0x0 141#define APIC_EILVT_MSG_SMI 0x2 142#define APIC_EILVT_MSG_NMI 0x4 143#define APIC_EILVT_MSG_EXT 0x7 144#define APIC_EILVT_MASKED (1 << 16) 145 146#define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) 147#define APIC_BASE_MSR 0x800 148#define XAPIC_ENABLE (1UL << 11) 149#define X2APIC_ENABLE (1UL << 10) 150 151#ifdef CONFIG_X86_32 152# define MAX_IO_APICS 64 153# define MAX_LOCAL_APIC 256 154#else 155# define MAX_IO_APICS 128 156# define MAX_LOCAL_APIC 32768 157#endif 158 159/* 160 * All x86-64 systems are xAPIC compatible. 161 * In the following, "apicid" is a physical APIC ID. 162 */ 163#define XAPIC_DEST_CPUS_SHIFT 4 164#define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1) 165#define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT) 166#define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK) 167#define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT) 168#define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK) 169#define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT) 170 171/* 172 * the local APIC register structure, memory mapped. Not terribly well 173 * tested, but we might eventually use this one in the future - the 174 * problem why we cannot use it right now is the P5 APIC, it has an 175 * errata which cannot take 8-bit reads and writes, only 32-bit ones ... 176 */ 177#define u32 unsigned int 178 179struct local_apic { 180 181/*000*/ struct { u32 __reserved[4]; } __reserved_01; 182 183/*010*/ struct { u32 __reserved[4]; } __reserved_02; 184 185/*020*/ struct { /* APIC ID Register */ 186 u32 __reserved_1 : 24, 187 phys_apic_id : 4, 188 __reserved_2 : 4; 189 u32 __reserved[3]; 190 } id; 191 192/*030*/ const 193 struct { /* APIC Version Register */ 194 u32 version : 8, 195 __reserved_1 : 8, 196 max_lvt : 8, 197 __reserved_2 : 8; 198 u32 __reserved[3]; 199 } version; 200 201/*040*/ struct { u32 __reserved[4]; } __reserved_03; 202 203/*050*/ struct { u32 __reserved[4]; } __reserved_04; 204 205/*060*/ struct { u32 __reserved[4]; } __reserved_05; 206 207/*070*/ struct { u32 __reserved[4]; } __reserved_06; 208 209/*080*/ struct { /* Task Priority Register */ 210 u32 priority : 8, 211 __reserved_1 : 24; 212 u32 __reserved_2[3]; 213 } tpr; 214 215/*090*/ const 216 struct { /* Arbitration Priority Register */ 217 u32 priority : 8, 218 __reserved_1 : 24; 219 u32 __reserved_2[3]; 220 } apr; 221 222/*0A0*/ const 223 struct { /* Processor Priority Register */ 224 u32 priority : 8, 225 __reserved_1 : 24; 226 u32 __reserved_2[3]; 227 } ppr; 228 229/*0B0*/ struct { /* End Of Interrupt Register */ 230 u32 eoi; 231 u32 __reserved[3]; 232 } eoi; 233 234/*0C0*/ struct { u32 __reserved[4]; } __reserved_07; 235 236/*0D0*/ struct { /* Logical Destination Register */ 237 u32 __reserved_1 : 24, 238 logical_dest : 8; 239 u32 __reserved_2[3]; 240 } ldr; 241 242/*0E0*/ struct { /* Destination Format Register */ 243 u32 __reserved_1 : 28, 244 model : 4; 245 u32 __reserved_2[3]; 246 } dfr; 247 248/*0F0*/ struct { /* Spurious Interrupt Vector Register */ 249 u32 spurious_vector : 8, 250 apic_enabled : 1, 251 focus_cpu : 1, 252 __reserved_2 : 22; 253 u32 __reserved_3[3]; 254 } svr; 255 256/*100*/ struct { /* In Service Register */ 257/*170*/ u32 bitfield; 258 u32 __reserved[3]; 259 } isr [8]; 260 261/*180*/ struct { /* Trigger Mode Register */ 262/*1F0*/ u32 bitfield; 263 u32 __reserved[3]; 264 } tmr [8]; 265 266/*200*/ struct { /* Interrupt Request Register */ 267/*270*/ u32 bitfield; 268 u32 __reserved[3]; 269 } irr [8]; 270 271/*280*/ union { /* Error Status Register */ 272 struct { 273 u32 send_cs_error : 1, 274 receive_cs_error : 1, 275 send_accept_error : 1, 276 receive_accept_error : 1, 277 __reserved_1 : 1, 278 send_illegal_vector : 1, 279 receive_illegal_vector : 1, 280 illegal_register_address : 1, 281 __reserved_2 : 24; 282 u32 __reserved_3[3]; 283 } error_bits; 284 struct { 285 u32 errors; 286 u32 __reserved_3[3]; 287 } all_errors; 288 } esr; 289 290/*290*/ struct { u32 __reserved[4]; } __reserved_08; 291 292/*2A0*/ struct { u32 __reserved[4]; } __reserved_09; 293 294/*2B0*/ struct { u32 __reserved[4]; } __reserved_10; 295 296/*2C0*/ struct { u32 __reserved[4]; } __reserved_11; 297 298/*2D0*/ struct { u32 __reserved[4]; } __reserved_12; 299 300/*2E0*/ struct { u32 __reserved[4]; } __reserved_13; 301 302/*2F0*/ struct { u32 __reserved[4]; } __reserved_14; 303 304/*300*/ struct { /* Interrupt Command Register 1 */ 305 u32 vector : 8, 306 delivery_mode : 3, 307 destination_mode : 1, 308 delivery_status : 1, 309 __reserved_1 : 1, 310 level : 1, 311 trigger : 1, 312 __reserved_2 : 2, 313 shorthand : 2, 314 __reserved_3 : 12; 315 u32 __reserved_4[3]; 316 } icr1; 317 318/*310*/ struct { /* Interrupt Command Register 2 */ 319 union { 320 u32 __reserved_1 : 24, 321 phys_dest : 4, 322 __reserved_2 : 4; 323 u32 __reserved_3 : 24, 324 logical_dest : 8; 325 } dest; 326 u32 __reserved_4[3]; 327 } icr2; 328 329/*320*/ struct { /* LVT - Timer */ 330 u32 vector : 8, 331 __reserved_1 : 4, 332 delivery_status : 1, 333 __reserved_2 : 3, 334 mask : 1, 335 timer_mode : 1, 336 __reserved_3 : 14; 337 u32 __reserved_4[3]; 338 } lvt_timer; 339 340/*330*/ struct { /* LVT - Thermal Sensor */ 341 u32 vector : 8, 342 delivery_mode : 3, 343 __reserved_1 : 1, 344 delivery_status : 1, 345 __reserved_2 : 3, 346 mask : 1, 347 __reserved_3 : 15; 348 u32 __reserved_4[3]; 349 } lvt_thermal; 350 351/*340*/ struct { /* LVT - Performance Counter */ 352 u32 vector : 8, 353 delivery_mode : 3, 354 __reserved_1 : 1, 355 delivery_status : 1, 356 __reserved_2 : 3, 357 mask : 1, 358 __reserved_3 : 15; 359 u32 __reserved_4[3]; 360 } lvt_pc; 361 362/*350*/ struct { /* LVT - LINT0 */ 363 u32 vector : 8, 364 delivery_mode : 3, 365 __reserved_1 : 1, 366 delivery_status : 1, 367 polarity : 1, 368 remote_irr : 1, 369 trigger : 1, 370 mask : 1, 371 __reserved_2 : 15; 372 u32 __reserved_3[3]; 373 } lvt_lint0; 374 375/*360*/ struct { /* LVT - LINT1 */ 376 u32 vector : 8, 377 delivery_mode : 3, 378 __reserved_1 : 1, 379 delivery_status : 1, 380 polarity : 1, 381 remote_irr : 1, 382 trigger : 1, 383 mask : 1, 384 __reserved_2 : 15; 385 u32 __reserved_3[3]; 386 } lvt_lint1; 387 388/*370*/ struct { /* LVT - Error */ 389 u32 vector : 8, 390 __reserved_1 : 4, 391 delivery_status : 1, 392 __reserved_2 : 3, 393 mask : 1, 394 __reserved_3 : 15; 395 u32 __reserved_4[3]; 396 } lvt_error; 397 398/*380*/ struct { /* Timer Initial Count Register */ 399 u32 initial_count; 400 u32 __reserved_2[3]; 401 } timer_icr; 402 403/*390*/ const 404 struct { /* Timer Current Count Register */ 405 u32 curr_count; 406 u32 __reserved_2[3]; 407 } timer_ccr; 408 409/*3A0*/ struct { u32 __reserved[4]; } __reserved_16; 410 411/*3B0*/ struct { u32 __reserved[4]; } __reserved_17; 412 413/*3C0*/ struct { u32 __reserved[4]; } __reserved_18; 414 415/*3D0*/ struct { u32 __reserved[4]; } __reserved_19; 416 417/*3E0*/ struct { /* Timer Divide Configuration Register */ 418 u32 divisor : 4, 419 __reserved_1 : 28; 420 u32 __reserved_2[3]; 421 } timer_dcr; 422 423/*3F0*/ struct { u32 __reserved[4]; } __reserved_20; 424 425} __attribute__ ((packed)); 426 427#undef u32 428 429#ifdef CONFIG_X86_32 430 #define BAD_APICID 0xFFu 431#else 432 #define BAD_APICID 0xFFFFu 433#endif 434 435enum ioapic_irq_destination_types { 436 dest_Fixed = 0, 437 dest_LowestPrio = 1, 438 dest_SMI = 2, 439 dest__reserved_1 = 3, 440 dest_NMI = 4, 441 dest_INIT = 5, 442 dest__reserved_2 = 6, 443 dest_ExtINT = 7 444}; 445 446#endif /* _ASM_X86_APICDEF_H */ 447