18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * apb_timer.h: Driver for Langwell APB timer based on Synopsis DesignWare 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * (C) Copyright 2009 Intel Corporation 68c2ecf20Sopenharmony_ci * Author: Jacob Pan (jacob.jun.pan@intel.com) 78c2ecf20Sopenharmony_ci * 88c2ecf20Sopenharmony_ci * Note: 98c2ecf20Sopenharmony_ci */ 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci#ifndef ASM_X86_APBT_H 128c2ecf20Sopenharmony_ci#define ASM_X86_APBT_H 138c2ecf20Sopenharmony_ci#include <linux/sfi.h> 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci#ifdef CONFIG_APB_TIMER 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci/* default memory mapped register base */ 188c2ecf20Sopenharmony_ci#define LNW_SCU_ADDR 0xFF100000 198c2ecf20Sopenharmony_ci#define LNW_EXT_TIMER_OFFSET 0x1B800 208c2ecf20Sopenharmony_ci#define APBT_DEFAULT_BASE (LNW_SCU_ADDR+LNW_EXT_TIMER_OFFSET) 218c2ecf20Sopenharmony_ci#define LNW_EXT_TIMER_PGOFFSET 0x800 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci/* APBT clock speed range from PCLK to fabric base, 25-100MHz */ 248c2ecf20Sopenharmony_ci#define APBT_MAX_FREQ 50000000 258c2ecf20Sopenharmony_ci#define APBT_MIN_FREQ 1000000 268c2ecf20Sopenharmony_ci#define APBT_MMAP_SIZE 1024 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ciextern void apbt_time_init(void); 298c2ecf20Sopenharmony_ciextern void apbt_setup_secondary_clock(void); 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ciextern struct sfi_timer_table_entry *sfi_get_mtmr(int hint); 328c2ecf20Sopenharmony_ciextern void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr); 338c2ecf20Sopenharmony_ciextern int sfi_mtimer_num; 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ci#else /* CONFIG_APB_TIMER */ 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_cistatic inline void apbt_time_init(void) { } 388c2ecf20Sopenharmony_ci 398c2ecf20Sopenharmony_ci#endif 408c2ecf20Sopenharmony_ci#endif /* ASM_X86_APBT_H */ 41