1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_AMD_NB_H
3#define _ASM_X86_AMD_NB_H
4
5#include <linux/ioport.h>
6#include <linux/pci.h>
7#include <linux/refcount.h>
8
9struct amd_nb_bus_dev_range {
10	u8 bus;
11	u8 dev_base;
12	u8 dev_limit;
13};
14
15extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
16
17extern bool early_is_amd_nb(u32 value);
18extern struct resource *amd_get_mmconfig_range(struct resource *res);
19extern int amd_cache_northbridges(void);
20extern void amd_flush_garts(void);
21extern int amd_numa_init(void);
22extern int amd_get_subcaches(int);
23extern int amd_set_subcaches(int, unsigned long);
24
25extern int amd_smn_read(u16 node, u32 address, u32 *value);
26extern int amd_smn_write(u16 node, u32 address, u32 value);
27extern int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo);
28
29struct amd_l3_cache {
30	unsigned indices;
31	u8	 subcaches[4];
32};
33
34struct threshold_block {
35	unsigned int	 block;			/* Number within bank */
36	unsigned int	 bank;			/* MCA bank the block belongs to */
37	unsigned int	 cpu;			/* CPU which controls MCA bank */
38	u32		 address;		/* MSR address for the block */
39	u16		 interrupt_enable;	/* Enable/Disable APIC interrupt */
40	bool		 interrupt_capable;	/* Bank can generate an interrupt. */
41
42	u16		 threshold_limit;	/*
43						 * Value upon which threshold
44						 * interrupt is generated.
45						 */
46
47	struct kobject	 kobj;			/* sysfs object */
48	struct list_head miscj;			/*
49						 * List of threshold blocks
50						 * within a bank.
51						 */
52};
53
54struct threshold_bank {
55	struct kobject		*kobj;
56	struct threshold_block	*blocks;
57
58	/* initialized to the number of CPUs on the node sharing this bank */
59	refcount_t		cpus;
60	unsigned int		shared;
61};
62
63struct amd_northbridge {
64	struct pci_dev *root;
65	struct pci_dev *misc;
66	struct pci_dev *link;
67	struct amd_l3_cache l3_cache;
68	struct threshold_bank *bank4;
69};
70
71struct amd_northbridge_info {
72	u16 num;
73	u64 flags;
74	struct amd_northbridge *nb;
75};
76
77#define AMD_NB_GART			BIT(0)
78#define AMD_NB_L3_INDEX_DISABLE		BIT(1)
79#define AMD_NB_L3_PARTITIONING		BIT(2)
80
81#ifdef CONFIG_AMD_NB
82
83u16 amd_nb_num(void);
84bool amd_nb_has_feature(unsigned int feature);
85struct amd_northbridge *node_to_amd_nb(int node);
86
87static inline u16 amd_pci_dev_to_node_id(struct pci_dev *pdev)
88{
89	struct pci_dev *misc;
90	int i;
91
92	for (i = 0; i != amd_nb_num(); i++) {
93		misc = node_to_amd_nb(i)->misc;
94
95		if (pci_domain_nr(misc->bus) == pci_domain_nr(pdev->bus) &&
96		    PCI_SLOT(misc->devfn) == PCI_SLOT(pdev->devfn))
97			return i;
98	}
99
100	WARN(1, "Unable to find AMD Northbridge id for %s\n", pci_name(pdev));
101	return 0;
102}
103
104static inline bool amd_gart_present(void)
105{
106	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
107		return false;
108
109	/* GART present only on Fam15h, upto model 0fh */
110	if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||
111	    (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10))
112		return true;
113
114	return false;
115}
116
117#else
118
119#define amd_nb_num(x)		0
120#define amd_nb_has_feature(x)	false
121#define node_to_amd_nb(x)	NULL
122#define amd_gart_present(x)	false
123
124#endif
125
126
127#endif /* _ASM_X86_AMD_NB_H */
128