18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci#ifndef __UM_CACHE_H 38c2ecf20Sopenharmony_ci#define __UM_CACHE_H 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci#if defined(CONFIG_UML_X86) && !defined(CONFIG_64BIT) 78c2ecf20Sopenharmony_ci# define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT) 88c2ecf20Sopenharmony_ci#elif defined(CONFIG_UML_X86) /* 64-bit */ 98c2ecf20Sopenharmony_ci# define L1_CACHE_SHIFT 6 /* Should be 7 on Intel */ 108c2ecf20Sopenharmony_ci#else 118c2ecf20Sopenharmony_ci/* XXX: this was taken from x86, now it's completely random. Luckily only 128c2ecf20Sopenharmony_ci * affects SMP padding. */ 138c2ecf20Sopenharmony_ci# define L1_CACHE_SHIFT 5 148c2ecf20Sopenharmony_ci#endif 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci#endif 19