1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __SPARC64_MMU_CONTEXT_H
3#define __SPARC64_MMU_CONTEXT_H
4
5/* Derived heavily from Linus's Alpha/AXP ASN code... */
6
7#ifndef __ASSEMBLY__
8
9#include <linux/spinlock.h>
10#include <linux/mm_types.h>
11#include <linux/smp.h>
12#include <linux/sched.h>
13
14#include <asm/spitfire.h>
15#include <asm/adi_64.h>
16#include <asm-generic/mm_hooks.h>
17#include <asm/percpu.h>
18
19static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
20{
21}
22
23extern spinlock_t ctx_alloc_lock;
24extern unsigned long tlb_context_cache;
25extern unsigned long mmu_context_bmap[];
26
27DECLARE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm);
28void get_new_mmu_context(struct mm_struct *mm);
29int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
30void destroy_context(struct mm_struct *mm);
31
32void __tsb_context_switch(unsigned long pgd_pa,
33			  struct tsb_config *tsb_base,
34			  struct tsb_config *tsb_huge,
35			  unsigned long tsb_descr_pa,
36			  unsigned long secondary_ctx);
37
38static inline void tsb_context_switch_ctx(struct mm_struct *mm,
39					  unsigned long ctx)
40{
41	__tsb_context_switch(__pa(mm->pgd),
42			     &mm->context.tsb_block[MM_TSB_BASE],
43#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
44			     (mm->context.tsb_block[MM_TSB_HUGE].tsb ?
45			      &mm->context.tsb_block[MM_TSB_HUGE] :
46			      NULL)
47#else
48			     NULL
49#endif
50			     , __pa(&mm->context.tsb_descr[MM_TSB_BASE]),
51			     ctx);
52}
53
54#define tsb_context_switch(X) tsb_context_switch_ctx(X, 0)
55
56void tsb_grow(struct mm_struct *mm,
57	      unsigned long tsb_index,
58	      unsigned long mm_rss);
59#ifdef CONFIG_SMP
60void smp_tsb_sync(struct mm_struct *mm);
61#else
62#define smp_tsb_sync(__mm) do { } while (0)
63#endif
64
65/* Set MMU context in the actual hardware. */
66#define load_secondary_context(__mm) \
67	__asm__ __volatile__( \
68	"\n661:	stxa		%0, [%1] %2\n" \
69	"	.section	.sun4v_1insn_patch, \"ax\"\n" \
70	"	.word		661b\n" \
71	"	stxa		%0, [%1] %3\n" \
72	"	.previous\n" \
73	"	flush		%%g6\n" \
74	: /* No outputs */ \
75	: "r" (CTX_HWBITS((__mm)->context)), \
76	  "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU), "i" (ASI_MMU))
77
78void __flush_tlb_mm(unsigned long, unsigned long);
79
80/* Switch the current MM context. */
81static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk)
82{
83	unsigned long ctx_valid, flags;
84	int cpu = smp_processor_id();
85
86	per_cpu(per_cpu_secondary_mm, cpu) = mm;
87	if (unlikely(mm == &init_mm))
88		return;
89
90	spin_lock_irqsave(&mm->context.lock, flags);
91	ctx_valid = CTX_VALID(mm->context);
92	if (!ctx_valid)
93		get_new_mmu_context(mm);
94
95	/* We have to be extremely careful here or else we will miss
96	 * a TSB grow if we switch back and forth between a kernel
97	 * thread and an address space which has it's TSB size increased
98	 * on another processor.
99	 *
100	 * It is possible to play some games in order to optimize the
101	 * switch, but the safest thing to do is to unconditionally
102	 * perform the secondary context load and the TSB context switch.
103	 *
104	 * For reference the bad case is, for address space "A":
105	 *
106	 *		CPU 0			CPU 1
107	 *	run address space A
108	 *	set cpu0's bits in cpu_vm_mask
109	 *	switch to kernel thread, borrow
110	 *	address space A via entry_lazy_tlb
111	 *					run address space A
112	 *					set cpu1's bit in cpu_vm_mask
113	 *					flush_tlb_pending()
114	 *					reset cpu_vm_mask to just cpu1
115	 *					TSB grow
116	 *	run address space A
117	 *	context was valid, so skip
118	 *	TSB context switch
119	 *
120	 * At that point cpu0 continues to use a stale TSB, the one from
121	 * before the TSB grow performed on cpu1.  cpu1 did not cross-call
122	 * cpu0 to update it's TSB because at that point the cpu_vm_mask
123	 * only had cpu1 set in it.
124	 */
125	tsb_context_switch_ctx(mm, CTX_HWBITS(mm->context));
126
127	/* Any time a processor runs a context on an address space
128	 * for the first time, we must flush that context out of the
129	 * local TLB.
130	 */
131	if (!ctx_valid || !cpumask_test_cpu(cpu, mm_cpumask(mm))) {
132		cpumask_set_cpu(cpu, mm_cpumask(mm));
133		__flush_tlb_mm(CTX_HWBITS(mm->context),
134			       SECONDARY_CONTEXT);
135	}
136	spin_unlock_irqrestore(&mm->context.lock, flags);
137}
138
139#define deactivate_mm(tsk,mm)	do { } while (0)
140#define activate_mm(active_mm, mm) switch_mm(active_mm, mm, NULL)
141
142#define  __HAVE_ARCH_START_CONTEXT_SWITCH
143static inline void arch_start_context_switch(struct task_struct *prev)
144{
145	/* Save the current state of MCDPER register for the process
146	 * we are switching from
147	 */
148	if (adi_capable()) {
149		register unsigned long tmp_mcdper;
150
151		__asm__ __volatile__(
152			".word 0x83438000\n\t"	/* rd  %mcdper, %g1 */
153			"mov %%g1, %0\n\t"
154			: "=r" (tmp_mcdper)
155			:
156			: "g1");
157		if (tmp_mcdper)
158			set_tsk_thread_flag(prev, TIF_MCDPER);
159		else
160			clear_tsk_thread_flag(prev, TIF_MCDPER);
161	}
162}
163
164#define finish_arch_post_lock_switch	finish_arch_post_lock_switch
165static inline void finish_arch_post_lock_switch(void)
166{
167	/* Restore the state of MCDPER register for the new process
168	 * just switched to.
169	 */
170	if (adi_capable()) {
171		register unsigned long tmp_mcdper;
172
173		tmp_mcdper = test_thread_flag(TIF_MCDPER);
174		__asm__ __volatile__(
175			"mov %0, %%g1\n\t"
176			".word 0x9d800001\n\t"	/* wr %g0, %g1, %mcdper" */
177			".word 0xaf902001\n\t"	/* wrpr %g0, 1, %pmcdper */
178			:
179			: "ir" (tmp_mcdper)
180			: "g1");
181		if (current && current->mm && current->mm->context.adi) {
182			struct pt_regs *regs;
183
184			regs = task_pt_regs(current);
185			regs->tstate |= TSTATE_MCDE;
186		}
187	}
188}
189
190#endif /* !(__ASSEMBLY__) */
191
192#endif /* !(__SPARC64_MMU_CONTEXT_H) */
193