18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci#ifndef _SPARC64_ESTATE_H 38c2ecf20Sopenharmony_ci#define _SPARC64_ESTATE_H 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ci/* UltraSPARC-III E-cache Error Enable */ 68c2ecf20Sopenharmony_ci#define ESTATE_ERROR_FMT 0x0000000000040000 /* Force MTAG ECC */ 78c2ecf20Sopenharmony_ci#define ESTATE_ERROR_FMESS 0x000000000003c000 /* Forced MTAG ECC val */ 88c2ecf20Sopenharmony_ci#define ESTATE_ERROR_FMD 0x0000000000002000 /* Force DATA ECC */ 98c2ecf20Sopenharmony_ci#define ESTATE_ERROR_FDECC 0x0000000000001ff0 /* Forced DATA ECC val */ 108c2ecf20Sopenharmony_ci#define ESTATE_ERROR_UCEEN 0x0000000000000008 /* See below */ 118c2ecf20Sopenharmony_ci#define ESTATE_ERROR_NCEEN 0x0000000000000002 /* See below */ 128c2ecf20Sopenharmony_ci#define ESTATE_ERROR_CEEN 0x0000000000000001 /* See below */ 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci/* UCEEN enables the fast_ECC_error trap for: 1) software correctable E-cache 158c2ecf20Sopenharmony_ci * errors 2) uncorrectable E-cache errors. Such events only occur on reads 168c2ecf20Sopenharmony_ci * of the E-cache by the local processor for: 1) data loads 2) instruction 178c2ecf20Sopenharmony_ci * fetches 3) atomic operations. Such events _cannot_ occur for: 1) merge 188c2ecf20Sopenharmony_ci * 2) writeback 2) copyout. The AFSR bits associated with these traps are 198c2ecf20Sopenharmony_ci * UCC and UCU. 208c2ecf20Sopenharmony_ci */ 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci/* NCEEN enables instruction_access_error, data_access_error, and ECC_error traps 238c2ecf20Sopenharmony_ci * for uncorrectable ECC errors and system errors. 248c2ecf20Sopenharmony_ci * 258c2ecf20Sopenharmony_ci * Uncorrectable system bus data error or MTAG ECC error, system bus TimeOUT, 268c2ecf20Sopenharmony_ci * or system bus BusERR: 278c2ecf20Sopenharmony_ci * 1) As the result of an instruction fetch, will generate instruction_access_error 288c2ecf20Sopenharmony_ci * 2) As the result of a load etc. will generate data_access_error. 298c2ecf20Sopenharmony_ci * 3) As the result of store merge completion, writeback, or copyout will 308c2ecf20Sopenharmony_ci * generate a disrupting ECC_error trap. 318c2ecf20Sopenharmony_ci * 4) As the result of such errors on instruction vector fetch can generate any 328c2ecf20Sopenharmony_ci * of the 3 trap types. 338c2ecf20Sopenharmony_ci * 348c2ecf20Sopenharmony_ci * The AFSR bits associated with these traps are EMU, EDU, WDU, CPU, IVU, UE, 358c2ecf20Sopenharmony_ci * BERR, and TO. 368c2ecf20Sopenharmony_ci */ 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci/* CEEN enables the ECC_error trap for hardware corrected ECC errors. System bus 398c2ecf20Sopenharmony_ci * reads resulting in a hardware corrected data or MTAG ECC error will generate an 408c2ecf20Sopenharmony_ci * ECC_error disrupting trap with this bit enabled. 418c2ecf20Sopenharmony_ci * 428c2ecf20Sopenharmony_ci * This same trap will also be generated when a hardware corrected ECC error results 438c2ecf20Sopenharmony_ci * during store merge, writeback, and copyout operations. 448c2ecf20Sopenharmony_ci */ 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci/* In general, if the trap enable bits above are disabled the AFSR bits will still 478c2ecf20Sopenharmony_ci * log the events even though the trap will not be generated by the processor. 488c2ecf20Sopenharmony_ci */ 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci#endif /* _SPARC64_ESTATE_H */ 51