18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci#ifndef __SPARC64_BARRIER_H 38c2ecf20Sopenharmony_ci#define __SPARC64_BARRIER_H 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ci/* These are here in an effort to more fully work around Spitfire Errata 68c2ecf20Sopenharmony_ci * #51. Essentially, if a memory barrier occurs soon after a mispredicted 78c2ecf20Sopenharmony_ci * branch, the chip can stop executing instructions until a trap occurs. 88c2ecf20Sopenharmony_ci * Therefore, if interrupts are disabled, the chip can hang forever. 98c2ecf20Sopenharmony_ci * 108c2ecf20Sopenharmony_ci * It used to be believed that the memory barrier had to be right in the 118c2ecf20Sopenharmony_ci * delay slot, but a case has been traced recently wherein the memory barrier 128c2ecf20Sopenharmony_ci * was one instruction after the branch delay slot and the chip still hung. 138c2ecf20Sopenharmony_ci * The offending sequence was the following in sym_wakeup_done() of the 148c2ecf20Sopenharmony_ci * sym53c8xx_2 driver: 158c2ecf20Sopenharmony_ci * 168c2ecf20Sopenharmony_ci * call sym_ccb_from_dsa, 0 178c2ecf20Sopenharmony_ci * movge %icc, 0, %l0 188c2ecf20Sopenharmony_ci * brz,pn %o0, .LL1303 198c2ecf20Sopenharmony_ci * mov %o0, %l2 208c2ecf20Sopenharmony_ci * membar #LoadLoad 218c2ecf20Sopenharmony_ci * 228c2ecf20Sopenharmony_ci * The branch has to be mispredicted for the bug to occur. Therefore, we put 238c2ecf20Sopenharmony_ci * the memory barrier explicitly into a "branch always, predicted taken" 248c2ecf20Sopenharmony_ci * delay slot to avoid the problem case. 258c2ecf20Sopenharmony_ci */ 268c2ecf20Sopenharmony_ci#define membar_safe(type) \ 278c2ecf20Sopenharmony_cido { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \ 288c2ecf20Sopenharmony_ci " membar " type "\n" \ 298c2ecf20Sopenharmony_ci "1:\n" \ 308c2ecf20Sopenharmony_ci : : : "memory"); \ 318c2ecf20Sopenharmony_ci} while (0) 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci/* The kernel always executes in TSO memory model these days, 348c2ecf20Sopenharmony_ci * and furthermore most sparc64 chips implement more stringent 358c2ecf20Sopenharmony_ci * memory ordering than required by the specifications. 368c2ecf20Sopenharmony_ci */ 378c2ecf20Sopenharmony_ci#define mb() membar_safe("#StoreLoad") 388c2ecf20Sopenharmony_ci#define rmb() __asm__ __volatile__("":::"memory") 398c2ecf20Sopenharmony_ci#define wmb() __asm__ __volatile__("":::"memory") 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci#define __smp_store_release(p, v) \ 428c2ecf20Sopenharmony_cido { \ 438c2ecf20Sopenharmony_ci compiletime_assert_atomic_type(*p); \ 448c2ecf20Sopenharmony_ci barrier(); \ 458c2ecf20Sopenharmony_ci WRITE_ONCE(*p, v); \ 468c2ecf20Sopenharmony_ci} while (0) 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ci#define __smp_load_acquire(p) \ 498c2ecf20Sopenharmony_ci({ \ 508c2ecf20Sopenharmony_ci typeof(*p) ___p1 = READ_ONCE(*p); \ 518c2ecf20Sopenharmony_ci compiletime_assert_atomic_type(*p); \ 528c2ecf20Sopenharmony_ci barrier(); \ 538c2ecf20Sopenharmony_ci ___p1; \ 548c2ecf20Sopenharmony_ci}) 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_ci#define __smp_mb__before_atomic() barrier() 578c2ecf20Sopenharmony_ci#define __smp_mb__after_atomic() barrier() 588c2ecf20Sopenharmony_ci 598c2ecf20Sopenharmony_ci#include <asm-generic/barrier.h> 608c2ecf20Sopenharmony_ci 618c2ecf20Sopenharmony_ci#endif /* !(__SPARC64_BARRIER_H) */ 62