1// SPDX-License-Identifier: GPL-2.0 2/* 3 * arch/sh/kernel/cpu/sh4a/clock-sh7785.c 4 * 5 * SH7785 support for the clock framework 6 * 7 * Copyright (C) 2007 - 2010 Paul Mundt 8 */ 9#include <linux/init.h> 10#include <linux/kernel.h> 11#include <linux/clk.h> 12#include <linux/io.h> 13#include <linux/cpufreq.h> 14#include <linux/clkdev.h> 15#include <asm/clock.h> 16#include <asm/freq.h> 17#include <cpu/sh7785.h> 18 19/* 20 * Default rate for the root input clock, reset this with clk_set_rate() 21 * from the platform code. 22 */ 23static struct clk extal_clk = { 24 .rate = 33333333, 25}; 26 27static unsigned long pll_recalc(struct clk *clk) 28{ 29 int multiplier; 30 31 multiplier = test_mode_pin(MODE_PIN4) ? 36 : 72; 32 33 return clk->parent->rate * multiplier; 34} 35 36static struct sh_clk_ops pll_clk_ops = { 37 .recalc = pll_recalc, 38}; 39 40static struct clk pll_clk = { 41 .ops = &pll_clk_ops, 42 .parent = &extal_clk, 43 .flags = CLK_ENABLE_ON_INIT, 44}; 45 46static struct clk *clks[] = { 47 &extal_clk, 48 &pll_clk, 49}; 50 51static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, 52 24, 32, 36, 48 }; 53 54static struct clk_div_mult_table div4_div_mult_table = { 55 .divisors = div2, 56 .nr_divisors = ARRAY_SIZE(div2), 57}; 58 59static struct clk_div4_table div4_table = { 60 .div_mult_table = &div4_div_mult_table, 61}; 62 63enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, 64 DIV4_DU, DIV4_P, DIV4_NR }; 65 66#define DIV4(_bit, _mask, _flags) \ 67 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) 68 69struct clk div4_clks[DIV4_NR] = { 70 [DIV4_P] = DIV4(0, 0x0f80, 0), 71 [DIV4_DU] = DIV4(4, 0x0ff0, 0), 72 [DIV4_GA] = DIV4(8, 0x0030, 0), 73 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT), 74 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT), 75 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT), 76 [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT), 77 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT), 78}; 79 80#define MSTPCR0 0xffc80030 81#define MSTPCR1 0xffc80034 82 83enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, 84 MSTP021, MSTP020, MSTP017, MSTP016, 85 MSTP013, MSTP012, MSTP009, MSTP008, MSTP003, MSTP002, 86 MSTP119, MSTP117, MSTP105, MSTP104, MSTP100, 87 MSTP_NR }; 88 89static struct clk mstp_clks[MSTP_NR] = { 90 /* MSTPCR0 */ 91 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), 92 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), 93 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), 94 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), 95 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), 96 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), 97 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), 98 [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0), 99 [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0), 100 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), 101 [MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0), 102 [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0), 103 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), 104 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), 105 [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0), 106 [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0), 107 108 /* MSTPCR1 */ 109 [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0), 110 [MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0), 111 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0), 112 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0), 113 [MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0), 114}; 115 116static struct clk_lookup lookups[] = { 117 /* main clocks */ 118 CLKDEV_CON_ID("extal", &extal_clk), 119 CLKDEV_CON_ID("pll_clk", &pll_clk), 120 121 /* DIV4 clocks */ 122 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), 123 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]), 124 CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]), 125 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]), 126 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 127 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 128 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), 129 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 130 131 /* MSTP32 clocks */ 132 CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP029]), 133 CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[MSTP028]), 134 CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP027]), 135 CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP026]), 136 CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP025]), 137 CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP024]), 138 139 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]), 140 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]), 141 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]), 142 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]), 143 CLKDEV_CON_ID("mmcif_fck", &mstp_clks[MSTP013]), 144 CLKDEV_CON_ID("flctl_fck", &mstp_clks[MSTP012]), 145 146 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP008]), 147 CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP009]), 148 149 CLKDEV_CON_ID("siof_fck", &mstp_clks[MSTP003]), 150 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]), 151 CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]), 152 CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP117]), 153 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]), 154 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]), 155 CLKDEV_CON_ID("gdta_fck", &mstp_clks[MSTP100]), 156}; 157 158int __init arch_clk_init(void) 159{ 160 int i, ret = 0; 161 162 for (i = 0; i < ARRAY_SIZE(clks); i++) 163 ret |= clk_register(clks[i]); 164 165 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 166 167 if (!ret) 168 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), 169 &div4_table); 170 if (!ret) 171 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); 172 173 return ret; 174} 175