18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 28c2ecf20Sopenharmony_ci#ifndef __ASM_SH_CPU_FEATURES_H 38c2ecf20Sopenharmony_ci#define __ASM_SH_CPU_FEATURES_H 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ci/* 68c2ecf20Sopenharmony_ci * Processor flags 78c2ecf20Sopenharmony_ci * 88c2ecf20Sopenharmony_ci * Note: When adding a new flag, keep cpu_flags[] in 98c2ecf20Sopenharmony_ci * arch/sh/kernel/setup.c in sync so symbolic name 108c2ecf20Sopenharmony_ci * mapping of the processor flags has a chance of being 118c2ecf20Sopenharmony_ci * reasonably accurate. 128c2ecf20Sopenharmony_ci * 138c2ecf20Sopenharmony_ci * These flags are also available through the ELF 148c2ecf20Sopenharmony_ci * auxiliary vector as AT_HWCAP. 158c2ecf20Sopenharmony_ci */ 168c2ecf20Sopenharmony_ci#define CPU_HAS_FPU 0x0001 /* Hardware FPU support */ 178c2ecf20Sopenharmony_ci#define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */ 188c2ecf20Sopenharmony_ci#define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */ 198c2ecf20Sopenharmony_ci#define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */ 208c2ecf20Sopenharmony_ci#define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */ 218c2ecf20Sopenharmony_ci#define CPU_HAS_PTEA 0x0020 /* PTEA register */ 228c2ecf20Sopenharmony_ci#define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */ 238c2ecf20Sopenharmony_ci#define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */ 248c2ecf20Sopenharmony_ci#define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */ 258c2ecf20Sopenharmony_ci#define CPU_HAS_PTEAEX 0x0200 /* PTE ASID Extension support */ 268c2ecf20Sopenharmony_ci#define CPU_HAS_CAS_L 0x0400 /* cas.l atomic compare-and-swap */ 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ci#endif /* __ASM_SH_CPU_FEATURES_H */ 29