18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 28c2ecf20Sopenharmony_ci * 38c2ecf20Sopenharmony_ci * include/asm-sh/cpu-sh4/sq.h 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (C) 2001, 2002, 2003 Paul Mundt 68c2ecf20Sopenharmony_ci * Copyright (C) 2001, 2002 M. R. Brown 78c2ecf20Sopenharmony_ci */ 88c2ecf20Sopenharmony_ci#ifndef __ASM_CPU_SH4_SQ_H 98c2ecf20Sopenharmony_ci#define __ASM_CPU_SH4_SQ_H 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci#include <asm/addrspace.h> 128c2ecf20Sopenharmony_ci#include <asm/page.h> 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci/* 158c2ecf20Sopenharmony_ci * Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be 168c2ecf20Sopenharmony_ci * mapped to any physical address space. Since data is written (and aligned) 178c2ecf20Sopenharmony_ci * to 32-byte boundaries, we need to be sure that all allocations are aligned. 188c2ecf20Sopenharmony_ci */ 198c2ecf20Sopenharmony_ci#define SQ_SIZE 32 208c2ecf20Sopenharmony_ci#define SQ_ALIGN_MASK (~(SQ_SIZE - 1)) 218c2ecf20Sopenharmony_ci#define SQ_ALIGN(addr) (((addr)+SQ_SIZE-1) & SQ_ALIGN_MASK) 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci#define SQ_QACR0 (P4SEG_REG_BASE + 0x38) 248c2ecf20Sopenharmony_ci#define SQ_QACR1 (P4SEG_REG_BASE + 0x3c) 258c2ecf20Sopenharmony_ci#define SQ_ADDRMAX (P4SEG_STORE_QUE + 0x04000000) 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci/* arch/sh/kernel/cpu/sh4/sq.c */ 288c2ecf20Sopenharmony_ciunsigned long sq_remap(unsigned long phys, unsigned int size, 298c2ecf20Sopenharmony_ci const char *name, pgprot_t prot); 308c2ecf20Sopenharmony_civoid sq_unmap(unsigned long vaddr); 318c2ecf20Sopenharmony_civoid sq_flush_range(unsigned long start, unsigned int len); 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci#endif /* __ASM_CPU_SH4_SQ_H */ 34