18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 28c2ecf20Sopenharmony_ci * 38c2ecf20Sopenharmony_ci * SH3 CPU-specific DMA definitions, used by both DMA drivers 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> 68c2ecf20Sopenharmony_ci */ 78c2ecf20Sopenharmony_ci#ifndef CPU_DMA_REGISTER_H 88c2ecf20Sopenharmony_ci#define CPU_DMA_REGISTER_H 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci#define CHCR_TS_LOW_MASK 0x18 118c2ecf20Sopenharmony_ci#define CHCR_TS_LOW_SHIFT 3 128c2ecf20Sopenharmony_ci#define CHCR_TS_HIGH_MASK 0 138c2ecf20Sopenharmony_ci#define CHCR_TS_HIGH_SHIFT 0 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci#define DMAOR_INIT DMAOR_DME 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci/* 188c2ecf20Sopenharmony_ci * The SuperH DMAC supports a number of transmit sizes, we list them here, 198c2ecf20Sopenharmony_ci * with their respective values as they appear in the CHCR registers. 208c2ecf20Sopenharmony_ci */ 218c2ecf20Sopenharmony_cienum { 228c2ecf20Sopenharmony_ci XMIT_SZ_8BIT, 238c2ecf20Sopenharmony_ci XMIT_SZ_16BIT, 248c2ecf20Sopenharmony_ci XMIT_SZ_32BIT, 258c2ecf20Sopenharmony_ci XMIT_SZ_128BIT, 268c2ecf20Sopenharmony_ci}; 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ci/* log2(size / 8) - used to calculate number of transfers */ 298c2ecf20Sopenharmony_ci#define TS_SHIFT { \ 308c2ecf20Sopenharmony_ci [XMIT_SZ_8BIT] = 0, \ 318c2ecf20Sopenharmony_ci [XMIT_SZ_16BIT] = 1, \ 328c2ecf20Sopenharmony_ci [XMIT_SZ_32BIT] = 2, \ 338c2ecf20Sopenharmony_ci [XMIT_SZ_128BIT] = 4, \ 348c2ecf20Sopenharmony_ci} 358c2ecf20Sopenharmony_ci 368c2ecf20Sopenharmony_ci#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT) 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci#endif 39