18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci#ifndef __ASM_SH_PCI_H 38c2ecf20Sopenharmony_ci#define __ASM_SH_PCI_H 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ci/* Can be used to override the logic in pci_scan_bus for skipping 68c2ecf20Sopenharmony_ci already-configured bus numbers - to be used for buggy BIOSes 78c2ecf20Sopenharmony_ci or architectures with incomplete PCI setup by the loader */ 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci#define pcibios_assign_all_busses() 1 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci/* 128c2ecf20Sopenharmony_ci * A board can define one or more PCI channels that represent built-in (or 138c2ecf20Sopenharmony_ci * external) PCI controllers. 148c2ecf20Sopenharmony_ci */ 158c2ecf20Sopenharmony_cistruct pci_channel { 168c2ecf20Sopenharmony_ci struct pci_channel *next; 178c2ecf20Sopenharmony_ci struct pci_bus *bus; 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci struct pci_ops *pci_ops; 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci struct resource *resources; 228c2ecf20Sopenharmony_ci unsigned int nr_resources; 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci unsigned long io_offset; 258c2ecf20Sopenharmony_ci unsigned long mem_offset; 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci unsigned long reg_base; 288c2ecf20Sopenharmony_ci unsigned long io_map_base; 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_ci unsigned int index; 318c2ecf20Sopenharmony_ci unsigned int need_domain_info; 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci /* Optional error handling */ 348c2ecf20Sopenharmony_ci struct timer_list err_timer, serr_timer; 358c2ecf20Sopenharmony_ci unsigned int err_irq, serr_irq; 368c2ecf20Sopenharmony_ci}; 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci/* arch/sh/drivers/pci/pci.c */ 398c2ecf20Sopenharmony_ciextern raw_spinlock_t pci_config_lock; 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ciextern int register_pci_controller(struct pci_channel *hose); 428c2ecf20Sopenharmony_ciextern void pcibios_report_status(unsigned int status_mask, int warn); 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ci/* arch/sh/drivers/pci/common.c */ 458c2ecf20Sopenharmony_ciextern int early_read_config_byte(struct pci_channel *hose, int top_bus, 468c2ecf20Sopenharmony_ci int bus, int devfn, int offset, u8 *value); 478c2ecf20Sopenharmony_ciextern int early_read_config_word(struct pci_channel *hose, int top_bus, 488c2ecf20Sopenharmony_ci int bus, int devfn, int offset, u16 *value); 498c2ecf20Sopenharmony_ciextern int early_read_config_dword(struct pci_channel *hose, int top_bus, 508c2ecf20Sopenharmony_ci int bus, int devfn, int offset, u32 *value); 518c2ecf20Sopenharmony_ciextern int early_write_config_byte(struct pci_channel *hose, int top_bus, 528c2ecf20Sopenharmony_ci int bus, int devfn, int offset, u8 value); 538c2ecf20Sopenharmony_ciextern int early_write_config_word(struct pci_channel *hose, int top_bus, 548c2ecf20Sopenharmony_ci int bus, int devfn, int offset, u16 value); 558c2ecf20Sopenharmony_ciextern int early_write_config_dword(struct pci_channel *hose, int top_bus, 568c2ecf20Sopenharmony_ci int bus, int devfn, int offset, u32 value); 578c2ecf20Sopenharmony_ciextern void pcibios_enable_timers(struct pci_channel *hose); 588c2ecf20Sopenharmony_ciextern unsigned int pcibios_handle_status_errors(unsigned long addr, 598c2ecf20Sopenharmony_ci unsigned int status, struct pci_channel *hose); 608c2ecf20Sopenharmony_ciextern int pci_is_66mhz_capable(struct pci_channel *hose, 618c2ecf20Sopenharmony_ci int top_bus, int current_bus); 628c2ecf20Sopenharmony_ci 638c2ecf20Sopenharmony_ciextern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM; 648c2ecf20Sopenharmony_ci 658c2ecf20Sopenharmony_ci#define HAVE_PCI_MMAP 668c2ecf20Sopenharmony_ci#define ARCH_GENERIC_PCI_MMAP_RESOURCE 678c2ecf20Sopenharmony_ci 688c2ecf20Sopenharmony_ci/* Dynamic DMA mapping stuff. 698c2ecf20Sopenharmony_ci * SuperH has everything mapped statically like x86. 708c2ecf20Sopenharmony_ci */ 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_ci#ifdef CONFIG_PCI 738c2ecf20Sopenharmony_ci/* 748c2ecf20Sopenharmony_ci * None of the SH PCI controllers support MWI, it is always treated as a 758c2ecf20Sopenharmony_ci * direct memory write. 768c2ecf20Sopenharmony_ci */ 778c2ecf20Sopenharmony_ci#define PCI_DISABLE_MWI 788c2ecf20Sopenharmony_ci#endif 798c2ecf20Sopenharmony_ci 808c2ecf20Sopenharmony_ci/* Board-specific fixup routines. */ 818c2ecf20Sopenharmony_ciint pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin); 828c2ecf20Sopenharmony_ci 838c2ecf20Sopenharmony_ci#define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index 848c2ecf20Sopenharmony_ci 858c2ecf20Sopenharmony_cistatic inline int pci_proc_domain(struct pci_bus *bus) 868c2ecf20Sopenharmony_ci{ 878c2ecf20Sopenharmony_ci struct pci_channel *hose = bus->sysdata; 888c2ecf20Sopenharmony_ci return hose->need_domain_info; 898c2ecf20Sopenharmony_ci} 908c2ecf20Sopenharmony_ci 918c2ecf20Sopenharmony_ci/* Chances are this interrupt is wired PC-style ... */ 928c2ecf20Sopenharmony_cistatic inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) 938c2ecf20Sopenharmony_ci{ 948c2ecf20Sopenharmony_ci return channel ? 15 : 14; 958c2ecf20Sopenharmony_ci} 968c2ecf20Sopenharmony_ci 978c2ecf20Sopenharmony_ci#endif /* __ASM_SH_PCI_H */ 98