18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima 48c2ecf20Sopenharmony_ci * Copyright (C) 2002 Paul Mundt 58c2ecf20Sopenharmony_ci */ 68c2ecf20Sopenharmony_ci#ifndef __ASM_SH_BARRIER_H 78c2ecf20Sopenharmony_ci#define __ASM_SH_BARRIER_H 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci#if defined(CONFIG_CPU_SH4A) 108c2ecf20Sopenharmony_ci#include <asm/cache_insns.h> 118c2ecf20Sopenharmony_ci#endif 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci/* 148c2ecf20Sopenharmony_ci * A brief note on ctrl_barrier(), the control register write barrier. 158c2ecf20Sopenharmony_ci * 168c2ecf20Sopenharmony_ci * Legacy SH cores typically require a sequence of 8 nops after 178c2ecf20Sopenharmony_ci * modification of a control register in order for the changes to take 188c2ecf20Sopenharmony_ci * effect. On newer cores (like the sh4a and sh5) this is accomplished 198c2ecf20Sopenharmony_ci * with icbi. 208c2ecf20Sopenharmony_ci * 218c2ecf20Sopenharmony_ci * Also note that on sh4a in the icbi case we can forego a synco for the 228c2ecf20Sopenharmony_ci * write barrier, as it's not necessary for control registers. 238c2ecf20Sopenharmony_ci * 248c2ecf20Sopenharmony_ci * Historically we have only done this type of barrier for the MMUCR, but 258c2ecf20Sopenharmony_ci * it's also necessary for the CCR, so we make it generic here instead. 268c2ecf20Sopenharmony_ci */ 278c2ecf20Sopenharmony_ci#if defined(CONFIG_CPU_SH4A) 288c2ecf20Sopenharmony_ci#define mb() __asm__ __volatile__ ("synco": : :"memory") 298c2ecf20Sopenharmony_ci#define rmb() mb() 308c2ecf20Sopenharmony_ci#define wmb() mb() 318c2ecf20Sopenharmony_ci#define ctrl_barrier() __icbi(PAGE_OFFSET) 328c2ecf20Sopenharmony_ci#else 338c2ecf20Sopenharmony_ci#if defined(CONFIG_CPU_J2) && defined(CONFIG_SMP) 348c2ecf20Sopenharmony_ci#define __smp_mb() do { int tmp = 0; __asm__ __volatile__ ("cas.l %0,%0,@%1" : "+r"(tmp) : "z"(&tmp) : "memory", "t"); } while(0) 358c2ecf20Sopenharmony_ci#define __smp_rmb() __smp_mb() 368c2ecf20Sopenharmony_ci#define __smp_wmb() __smp_mb() 378c2ecf20Sopenharmony_ci#endif 388c2ecf20Sopenharmony_ci#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop") 398c2ecf20Sopenharmony_ci#endif 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci#define __smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0) 428c2ecf20Sopenharmony_ci 438c2ecf20Sopenharmony_ci#include <asm-generic/barrier.h> 448c2ecf20Sopenharmony_ci 458c2ecf20Sopenharmony_ci#endif /* __ASM_SH_BARRIER_H */ 46